include/configs/hmi1001.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15
  16 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU       */
  17 #define CONFIG_HMI1001          1       /* HMI1001 board                */
  18
  19 #ifndef CONFIG_SYS_TEXT_BASE
  20 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  21 #endif
  22
  23 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  24
  25 #define CONFIG_BOARD_EARLY_INIT_R
  26
  27 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  28
  29 /*
  30  * Serial console configuration
  31  */
  32 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  33 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  34 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  35
  36 /* Partitions */
  37 #define CONFIG_DOS_PARTITION
  38
  39
  40 /*
  41  * BOOTP options
  42  */
  43 #define CONFIG_BOOTP_BOOTFILESIZE
  44 #define CONFIG_BOOTP_BOOTPATH
  45 #define CONFIG_BOOTP_GATEWAY
  46 #define CONFIG_BOOTP_HOSTNAME
  47
  48
  49 /*
  50  * Command line configuration.
  51  */
  52 #include <config_cmd_default.h>
  53
  54 #define CONFIG_CMD_DATE
  55 #define CONFIG_CMD_DISPLAY
  56 #define CONFIG_CMD_DHCP
  57 #define CONFIG_CMD_EEPROM
  58 #define CONFIG_CMD_I2C
  59 #define CONFIG_CMD_IDE
  60 #define CONFIG_CMD_NFS
  61 #define CONFIG_CMD_PCI
  62 #define CONFIG_CMD_SNTP
  63
  64
  65 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  66
  67 #if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
  68 #   define CONFIG_SYS_LOWBOOT           1
  69 #endif
  70
  71 /*
  72  * Autobooting
  73  */
  74 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  75
  76 #define CONFIG_PREBOOT  "echo;" \
  77         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
  78         "echo"
  79
  80 #undef  CONFIG_BOOTARGS
  81
  82 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  83         "netdev=eth0\0"                                                 \
  84         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
  85                 "nfsroot=${serverip}:${rootpath}\0"                     \
  86         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
  87         "addip=setenv bootargs ${bootargs} "                            \
  88                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
  89                 ":${hostname}:${netdev}:off panic=1\0"                  \
  90         "flash_nfs=run nfsargs addip;"                                  \
  91                 "bootm ${kernel_addr}\0"                                \
  92         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
  93         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  94         ""
  95
  96 #define CONFIG_BOOTCOMMAND      "run net_nfs"
  97
  98 #define CONFIG_MISC_INIT_R      1
  99
 100 /*
 101  * IPB Bus clocking configuration.
 102  */
 103 #undef CONFIG_SYS_IPBCLK_EQUALS_XLBCLK          /* define for 133MHz speed */
 104
 105 /*
 106  * I2C configuration
 107  */
 108 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 109 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 110
 111 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 112 #define CONFIG_SYS_I2C_SLAVE            0x7F
 113
 114 /*
 115  * EEPROM configuration
 116  */
 117 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
 118 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 119 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
 120 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 121
 122 /*
 123  * RTC configuration
 124  */
 125 #define CONFIG_RTC_PCF8563
 126 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 127
 128 /*
 129  * Flash configuration
 130  */
 131 #define CONFIG_SYS_FLASH_BASE           0xFF800000
 132
 133 #define CONFIG_SYS_FLASH_SIZE           0x00800000 /* 8 MByte */
 134 #define CONFIG_SYS_MAX_FLASH_SECT       67      /* max num of sects on one chip */
 135
 136 #define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
 137 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
 138                                            (= chip selects) */
 139 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout (in ms)  */
 140 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (in ms)  */
 141
 142 #define CONFIG_FLASH_CFI_DRIVER
 143 #define CONFIG_SYS_FLASH_CFI
 144 #define CONFIG_SYS_FLASH_EMPTY_INFO
 145 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
 146
 147 /*
 148  * Environment settings
 149  */
 150 #define CONFIG_ENV_IS_IN_FLASH  1
 151 #define CONFIG_ENV_SIZE         0x4000
 152 #define CONFIG_ENV_SECT_SIZE    0x20000
 153 #define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 154 #define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
 155
 156 /*
 157  * Memory map
 158  */
 159 #define CONFIG_SYS_MBAR         0xF0000000
 160 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 161 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 162 #define CONFIG_SYS_DISPLAY_BASE 0x80600000
 163 #define CONFIG_SYS_STATUS1_BASE 0x80600200
 164 #define CONFIG_SYS_STATUS2_BASE 0x80600300
 165
 166 /* Settings for XLB = 132 MHz */
 167 #define SDRAM_DDR        1
 168 #define SDRAM_MODE      0x018D0000
 169 #define SDRAM_EMODE     0x40090000
 170 #define SDRAM_CONTROL   0x714f0f00
 171 #define SDRAM_CONFIG1   0x73722930
 172 #define SDRAM_CONFIG2   0x47770000
 173 #define SDRAM_TAPDELAY  0x10000000
 174
 175 /* Use ON-Chip SRAM until RAM will be available */
 176 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 177
 178 /* preserve space for the post_word at end of on-chip SRAM */
 179 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 180
 181 #ifdef CONFIG_POST
 182 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 183 #else
 184 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 185 #endif
 186
 187 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 188 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 189
 190 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 191 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 192 #   define CONFIG_SYS_RAMBOOT           1
 193 #endif
 194
 195 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)     /* Reserve 192 kB for Monitor   */
 196 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 128 kB for malloc()  */
 197 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 198
 199 /*
 200  * Ethernet configuration
 201  */
 202 #define CONFIG_MPC5xxx_FEC      1
 203 #define CONFIG_MPC5xxx_FEC_MII100
 204 #define CONFIG_PHY_ADDR         0x00
 205 #define CONFIG_MII              1               /* MII PHY management           */
 206
 207 /*
 208  * GPIO configuration
 209  */
 210 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01051004
 211
 212 /*
 213  * Miscellaneous configurable options
 214  */
 215 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 216 #if defined(CONFIG_CMD_KGDB)
 217 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 218 #else
 219 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 220 #endif
 221 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 222 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 223 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 224
 225 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 226 #if defined(CONFIG_CMD_KGDB)
 227 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 228 #endif
 229
 230 /* Enable an alternate, more extensive memory test */
 231 #define CONFIG_SYS_ALT_MEMTEST
 232
 233 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 234 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 235
 236 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 237
 238 /*
 239  * Enable loopw command.
 240  */
 241 #define CONFIG_LOOPW
 242
 243 /*
 244  * Various low-level settings
 245  */
 246 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 247 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 248
 249 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 250 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 251 #define CONFIG_SYS_BOOTCS_CFG           0x0004FB00
 252 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 253 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 254
 255 /* 8Mbit SRAM @0x80100000 */
 256 #define CONFIG_SYS_CS1_START            0x80100000
 257 #define CONFIG_SYS_CS1_SIZE             0x00100000
 258 #define CONFIG_SYS_CS1_CFG              0x19B00
 259
 260 /* FRAM 32Kbyte @0x80700000 */
 261 #define CONFIG_SYS_CS2_START            0x80700000
 262 #define CONFIG_SYS_CS2_SIZE             0x00008000
 263 #define CONFIG_SYS_CS2_CFG              0x19800
 264
 265 /* Display H1, Status Inputs, EPLD @0x80600000 */
 266 #define CONFIG_SYS_CS3_START            0x80600000
 267 #define CONFIG_SYS_CS3_SIZE             0x00100000
 268 #define CONFIG_SYS_CS3_CFG              0x00019800
 269
 270 #define CONFIG_SYS_CS_BURST             0x00000000
 271 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 272
 273 /*-----------------------------------------------------------------------
 274  * IDE/ATA stuff Supports IDE harddisk
 275  *-----------------------------------------------------------------------
 276  */
 277
 278 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 279
 280 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 281 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 282
 283 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 284 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 2 drives per IDE bus    */
 285
 286 #define CONFIG_IDE_PREINIT      1
 287
 288 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 289
 290 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 291
 292 /* Offset for data I/O                  */
 293 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 294
 295 /* Offset for normal register accesses  */
 296 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 297
 298 /* Offset for alternate registers       */
 299 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 300
 301 /* Interval between registers                                                */
 302 #define CONFIG_SYS_ATA_STRIDE          4
 303
 304 #define CONFIG_ATAPI            1
 305
 306 #define CONFIG_VIDEO_SMI_LYNXEM
 307 #define CONFIG_CFB_CONSOLE
 308 #define CONFIG_VGA_AS_SINGLE_DEVICE
 309 #define CONFIG_VIDEO_LOGO
 310
 311 /*
 312  * PCI Mapping:
 313  * 0x40000000 - 0x4fffffff - PCI Memory
 314  * 0x50000000 - 0x50ffffff - PCI IO Space
 315  */
 316 #define CONFIG_PCI              1
 317 #define CONFIG_PCI_PNP          1
 318 #define CONFIG_PCI_SCAN_SHOW    1
 319 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
 320
 321 #define CONFIG_PCI_MEM_BUS      0x40000000
 322 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
 323 #define CONFIG_PCI_MEM_SIZE     0x10000000
 324
 325 #define CONFIG_PCI_IO_BUS       0x50000000
 326 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
 327 #define CONFIG_PCI_IO_SIZE      0x01000000
 328
 329 #define CONFIG_SYS_ISA_IO               CONFIG_PCI_IO_BUS
 330
 331 /*---------------------------------------------------------------------*/
 332 /* Display addresses                                                   */
 333 /*---------------------------------------------------------------------*/
 334
 335 #define CONFIG_PDSP188x
 336 #define CONFIG_SYS_DISP_CHR_RAM (CONFIG_SYS_DISPLAY_BASE + 0x38)
 337 #define CONFIG_SYS_DISP_CWORD           (CONFIG_SYS_DISPLAY_BASE + 0x30)
 338
 339 #endif /* __CONFIG_H */