include/configs/hrcon.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2014
   4  * Dirk Eibach,  Guntermann & Drunck GmbH, dirk.eibach@gdsys.cc
   5  *
   6  */
   7
   8 #ifndef __CONFIG_H
   9 #define __CONFIG_H
  10
  11 #include <linux/stringify.h>
  12
  13 /*
  14  * High Level Configuration Options
  15  */
  16 #define CONFIG_E300             1 /* E300 family */
  17
  18 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC83xx_ESDHC_ADDR
  19
  20 /*
  21  * SERDES
  22  */
  23 #define CONFIG_FSL_SERDES
  24 #define CONFIG_FSL_SERDES1      0xe3000
  25
  26 /*
  27  * DDR Setup
  28  */
  29 #define CONFIG_SYS_SDRAM_BASE           0x00000000 /* DDR is system memory */
  30 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05
  31 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_EN \
  32                                 | DDRCDR_PZ_LOZ \
  33                                 | DDRCDR_NZ_LOZ \
  34                                 | DDRCDR_ODT \
  35                                 | DDRCDR_Q_DRN)
  36                                 /* 0x7b880001 */
  37 /*
  38  * Manually set up DDR parameters
  39  * consist of one chip NT5TU64M16HG from NANYA
  40  */
  41
  42 #define CONFIG_SYS_DDR_SIZE             128 /* MB */
  43
  44 #define CONFIG_SYS_DDR_CS0_BNDS 0x00000007
  45 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN \
  46                                 | CSCONFIG_ODT_RD_NEVER \
  47                                 | CSCONFIG_ODT_WR_ONLY_CURRENT \
  48                                 | CSCONFIG_BANK_BIT_3 \
  49                                 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
  50                                 /* 0x80010102 */
  51 #define CONFIG_SYS_DDR_TIMING_3 0
  52 #define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
  53                                 | (0 << TIMING_CFG0_WRT_SHIFT) \
  54                                 | (0 << TIMING_CFG0_RRT_SHIFT) \
  55                                 | (0 << TIMING_CFG0_WWT_SHIFT) \
  56                                 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
  57                                 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
  58                                 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
  59                                 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
  60                                 /* 0x00260802 */
  61 #define CONFIG_SYS_DDR_TIMING_1 ((2 << TIMING_CFG1_PRETOACT_SHIFT) \
  62                                 | (6 << TIMING_CFG1_ACTTOPRE_SHIFT) \
  63                                 | (2 << TIMING_CFG1_ACTTORW_SHIFT) \
  64                                 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
  65                                 | (9 << TIMING_CFG1_REFREC_SHIFT) \
  66                                 | (2 << TIMING_CFG1_WRREC_SHIFT) \
  67                                 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
  68                                 | (2 << TIMING_CFG1_WRTORD_SHIFT))
  69                                 /* 0x26279222 */
  70 #define CONFIG_SYS_DDR_TIMING_2 ((0 << TIMING_CFG2_ADD_LAT_SHIFT) \
  71                                 | (4 << TIMING_CFG2_CPO_SHIFT) \
  72                                 | (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) \
  73                                 | (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) \
  74                                 | (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) \
  75                                 | (3 << TIMING_CFG2_CKE_PLS_SHIFT) \
  76                                 | (5 << TIMING_CFG2_FOUR_ACT_SHIFT))
  77                                 /* 0x021848c5 */
  78 #define CONFIG_SYS_DDR_INTERVAL ((0x0824 << SDRAM_INTERVAL_REFINT_SHIFT) \
  79                                 | (0x0100 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
  80                                 /* 0x08240100 */
  81 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SREN \
  82                                 | SDRAM_CFG_SDRAM_TYPE_DDR2 \
  83                                 | SDRAM_CFG_DBW_16)
  84                                 /* 0x43100000 */
  85
  86 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000 /* 1 posted refresh */
  87 #define CONFIG_SYS_DDR_MODE             ((0x0440 << SDRAM_MODE_ESD_SHIFT) \
  88                                 | (0x0242 << SDRAM_MODE_SD_SHIFT))
  89                                 /* ODT 150ohm CL=4, AL=0 on SDRAM */
  90 #define CONFIG_SYS_DDR_MODE2            0x00000000
  91
  92 /*
  93  * Memory test
  94  */
  95
  96 /*
  97  * The reserved memory
  98  */
  99 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 100
 101 #define CONFIG_SYS_MONITOR_LEN  (384 * 1024) /* Reserve 384 kB for Mon */
 102 #define CONFIG_SYS_MALLOC_LEN   (512 * 1024) /* Reserved for malloc */
 103
 104 /*
 105  * Initial RAM Base Address Setup
 106  */
 107 #define CONFIG_SYS_INIT_RAM_LOCK        1
 108 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 109 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 110 #define CONFIG_SYS_GBL_DATA_OFFSET      \
 111         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 112
 113 /*
 114  * FLASH on the Local Bus
 115  */
 116 #if 1
 117 #define CONFIG_SYS_FLASH_CFI_WIDTH      FLASH_CFI_16BIT
 118 #define CONFIG_FLASH_CFI_LEGACY
 119 #define CONFIG_SYS_FLASH_LEGACY_512Kx16
 120 #endif
 121
 122 #define CONFIG_SYS_FLASH_BASE           0xFE000000 /* FLASH base address */
 123 #define CONFIG_SYS_FLASH_SIZE           8 /* FLASH size is up to 8M */
 124
 125
 126 #define CONFIG_SYS_MAX_FLASH_BANKS      1 /* number of banks */
 127 #define CONFIG_SYS_MAX_FLASH_SECT       135
 128
 129 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000 /* Flash Erase Timeout (ms) */
 130 #define CONFIG_SYS_FLASH_WRITE_TOUT     500 /* Flash Write Timeout (ms) */
 131
 132 #define CONFIG_SYS_FPGA_DONE(k)         0x0010
 133
 134 #define CONFIG_SYS_FPGA_COUNT           1
 135
 136 #define CONFIG_SYS_MCLINK_MAX           3
 137
 138 #define CONFIG_SYS_FPGA_PTR \
 139         { (struct ihs_fpga *)CONFIG_SYS_FPGA0_BASE, NULL, NULL, NULL }
 140
 141 /*
 142  * Serial Port
 143  */
 144 #define CONFIG_SYS_NS16550_SERIAL
 145 #define CONFIG_SYS_NS16550_REG_SIZE     1
 146 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 147
 148 #define CONFIG_SYS_BAUDRATE_TABLE  \
 149         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 150
 151 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x4500)
 152 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x4600)
 153
 154 /* Pass open firmware flat tree */
 155
 156 /* I2C */
 157 #define CONFIG_SYS_I2C
 158 #define CONFIG_SYS_I2C_FSL
 159 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 160 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 161 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 162
 163 #define CONFIG_PCA953X                  /* NXP PCA9554 */
 164 #define CONFIG_PCA9698                  /* NXP PCA9698 */
 165
 166 #define CONFIG_SYS_I2C_IHS
 167 #define CONFIG_SYS_I2C_IHS_CH0
 168 #define CONFIG_SYS_I2C_IHS_SPEED_0              50000
 169 #define CONFIG_SYS_I2C_IHS_SLAVE_0              0x7F
 170 #define CONFIG_SYS_I2C_IHS_CH1
 171 #define CONFIG_SYS_I2C_IHS_SPEED_1              50000
 172 #define CONFIG_SYS_I2C_IHS_SLAVE_1              0x7F
 173 #define CONFIG_SYS_I2C_IHS_CH2
 174 #define CONFIG_SYS_I2C_IHS_SPEED_2              50000
 175 #define CONFIG_SYS_I2C_IHS_SLAVE_2              0x7F
 176 #define CONFIG_SYS_I2C_IHS_CH3
 177 #define CONFIG_SYS_I2C_IHS_SPEED_3              50000
 178 #define CONFIG_SYS_I2C_IHS_SLAVE_3              0x7F
 179
 180 #ifdef CONFIG_HRCON_DH
 181 #define CONFIG_SYS_I2C_IHS_DUAL
 182 #define CONFIG_SYS_I2C_IHS_CH0_1
 183 #define CONFIG_SYS_I2C_IHS_SPEED_0_1            50000
 184 #define CONFIG_SYS_I2C_IHS_SLAVE_0_1            0x7F
 185 #define CONFIG_SYS_I2C_IHS_CH1_1
 186 #define CONFIG_SYS_I2C_IHS_SPEED_1_1            50000
 187 #define CONFIG_SYS_I2C_IHS_SLAVE_1_1            0x7F
 188 #define CONFIG_SYS_I2C_IHS_CH2_1
 189 #define CONFIG_SYS_I2C_IHS_SPEED_2_1            50000
 190 #define CONFIG_SYS_I2C_IHS_SLAVE_2_1            0x7F
 191 #define CONFIG_SYS_I2C_IHS_CH3_1
 192 #define CONFIG_SYS_I2C_IHS_SPEED_3_1            50000
 193 #define CONFIG_SYS_I2C_IHS_SLAVE_3_1            0x7F
 194 #endif
 195
 196 /*
 197  * Software (bit-bang) I2C driver configuration
 198  */
 199 #define CONFIG_SYS_I2C_SOFT
 200 #define CONFIG_SYS_I2C_SOFT_SPEED               50000
 201 #define CONFIG_SYS_I2C_SOFT_SLAVE               0x7F
 202 #define I2C_SOFT_DECLARATIONS2
 203 #define CONFIG_SYS_I2C_SOFT_SPEED_2             50000
 204 #define CONFIG_SYS_I2C_SOFT_SLAVE_2             0x7F
 205 #define I2C_SOFT_DECLARATIONS3
 206 #define CONFIG_SYS_I2C_SOFT_SPEED_3             50000
 207 #define CONFIG_SYS_I2C_SOFT_SLAVE_3             0x7F
 208 #define I2C_SOFT_DECLARATIONS4
 209 #define CONFIG_SYS_I2C_SOFT_SPEED_4             50000
 210 #define CONFIG_SYS_I2C_SOFT_SLAVE_4             0x7F
 211 #define I2C_SOFT_DECLARATIONS5
 212 #define CONFIG_SYS_I2C_SOFT_SPEED_5             50000
 213 #define CONFIG_SYS_I2C_SOFT_SLAVE_5             0x7F
 214 #define I2C_SOFT_DECLARATIONS6
 215 #define CONFIG_SYS_I2C_SOFT_SPEED_6             50000
 216 #define CONFIG_SYS_I2C_SOFT_SLAVE_6             0x7F
 217 #define I2C_SOFT_DECLARATIONS7
 218 #define CONFIG_SYS_I2C_SOFT_SPEED_7             50000
 219 #define CONFIG_SYS_I2C_SOFT_SLAVE_7             0x7F
 220 #define I2C_SOFT_DECLARATIONS8
 221 #define CONFIG_SYS_I2C_SOFT_SPEED_8             50000
 222 #define CONFIG_SYS_I2C_SOFT_SLAVE_8             0x7F
 223
 224 #ifdef CONFIG_HRCON_DH
 225 #define I2C_SOFT_DECLARATIONS9
 226 #define CONFIG_SYS_I2C_SOFT_SPEED_9             50000
 227 #define CONFIG_SYS_I2C_SOFT_SLAVE_9             0x7F
 228 #define I2C_SOFT_DECLARATIONS10
 229 #define CONFIG_SYS_I2C_SOFT_SPEED_10            50000
 230 #define CONFIG_SYS_I2C_SOFT_SLAVE_10            0x7F
 231 #define I2C_SOFT_DECLARATIONS11
 232 #define CONFIG_SYS_I2C_SOFT_SPEED_11            50000
 233 #define CONFIG_SYS_I2C_SOFT_SLAVE_11            0x7F
 234 #define I2C_SOFT_DECLARATIONS12
 235 #define CONFIG_SYS_I2C_SOFT_SPEED_12            50000
 236 #define CONFIG_SYS_I2C_SOFT_SLAVE_12            0x7F
 237 #endif
 238
 239 #ifdef CONFIG_HRCON_DH
 240 #define CONFIG_SYS_ICS8N3QV01_I2C               {13, 14, 15, 16, 17, 18, 19, 20}
 241 #define CONFIG_SYS_DP501_I2C                    {1, 3, 5, 7, 2, 4, 6, 8}
 242 #define CONFIG_HRCON_FANS                       { {10, 0x4c}, {11, 0x4c}, \
 243                                                   {12, 0x4c} }
 244 #else
 245 #define CONFIG_SYS_ICS8N3QV01_I2C               {9, 10, 11, 12}
 246 #define CONFIG_SYS_DP501_I2C                    {1, 2, 3, 4}
 247 #define CONFIG_HRCON_FANS                       { {6, 0x4c}, {7, 0x4c}, \
 248                                                   {8, 0x4c} }
 249 #endif
 250
 251 #ifndef __ASSEMBLY__
 252 void fpga_gpio_set(unsigned int bus, int pin);
 253 void fpga_gpio_clear(unsigned int bus, int pin);
 254 int fpga_gpio_get(unsigned int bus, int pin);
 255 void fpga_control_set(unsigned int bus, int pin);
 256 void fpga_control_clear(unsigned int bus, int pin);
 257 #endif
 258
 259 #define I2C_SDA_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0040 : 0x0200)
 260 #define I2C_SCL_GPIO    ((I2C_ADAP_HWNR > 3) ? 0x0020 : 0x0100)
 261 #define I2C_FPGA_IDX    (I2C_ADAP_HWNR % 4)
 262
 263 #ifdef CONFIG_HRCON_DH
 264 #define I2C_ACTIVE \
 265         do { \
 266                 if (I2C_ADAP_HWNR > 7) \
 267                         fpga_control_set(I2C_FPGA_IDX, 0x0004); \
 268                 else \
 269                         fpga_control_clear(I2C_FPGA_IDX, 0x0004); \
 270         } while (0)
 271 #else
 272 #define I2C_ACTIVE      { }
 273 #endif
 274 #define I2C_TRISTATE    { }
 275 #define I2C_READ \
 276         (fpga_gpio_get(I2C_FPGA_IDX, I2C_SDA_GPIO) ? 1 : 0)
 277 #define I2C_SDA(bit) \
 278         do { \
 279                 if (bit) \
 280                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 281                 else \
 282                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SDA_GPIO); \
 283         } while (0)
 284 #define I2C_SCL(bit) \
 285         do { \
 286                 if (bit) \
 287                         fpga_gpio_set(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 288                 else \
 289                         fpga_gpio_clear(I2C_FPGA_IDX, I2C_SCL_GPIO); \
 290         } while (0)
 291 #define I2C_DELAY       udelay(25)      /* 1/4 I2C clock duration */
 292
 293 /*
 294  * Software (bit-bang) MII driver configuration
 295  */
 296 #define CONFIG_BITBANGMII_MULTI
 297
 298 /*
 299  * OSD Setup
 300  */
 301 #define CONFIG_SYS_OSD_SCREENS          1
 302 #define CONFIG_SYS_DP501_DIFFERENTIAL
 303 #define CONFIG_SYS_DP501_VCAPCTRL0      0x01 /* DDR mode 0, DE for H/VSYNC */
 304
 305 #ifdef CONFIG_HRCON_DH
 306 #define CONFIG_SYS_OSD_DH
 307 #endif
 308
 309 /*
 310  * General PCI
 311  * Addresses are mapped 1-1.
 312  */
 313 #define CONFIG_SYS_PCIE1_BASE           0xA0000000
 314 #define CONFIG_SYS_PCIE1_MEM_BASE       0xA0000000
 315 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xA0000000
 316 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x10000000
 317 #define CONFIG_SYS_PCIE1_CFG_BASE       0xB0000000
 318 #define CONFIG_SYS_PCIE1_CFG_SIZE       0x01000000
 319 #define CONFIG_SYS_PCIE1_IO_BASE        0x00000000
 320 #define CONFIG_SYS_PCIE1_IO_PHYS        0xB1000000
 321 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00800000
 322
 323 /* enable PCIE clock */
 324 #define CONFIG_SYS_SCCR_PCIEXP1CM       1
 325
 326 #define CONFIG_PCI_INDIRECT_BRIDGE
 327 #define CONFIG_PCIE
 328
 329 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957   /* Freescale */
 330 #define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES 1
 331
 332 /*
 333  * TSEC
 334  */
 335 #define CONFIG_SYS_TSEC1_OFFSET 0x24000
 336 #define CONFIG_SYS_TSEC1        (CONFIG_SYS_IMMR+CONFIG_SYS_TSEC1_OFFSET)
 337
 338 /*
 339  * TSEC ethernet configuration
 340  */
 341 #define CONFIG_TSEC1
 342 #define CONFIG_TSEC1_NAME       "eTSEC0"
 343 #define TSEC1_PHY_ADDR          1
 344 #define TSEC1_PHYIDX            0
 345 #define TSEC1_FLAGS             TSEC_GIGABIT
 346
 347 /* Options are: eTSEC[0-1] */
 348 #define CONFIG_ETHPRIME         "eTSEC0"
 349
 350 /*
 351  * Environment
 352  */
 353
 354 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 355 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 356
 357 /*
 358  * Command line configuration.
 359  */
 360
 361 /*
 362  * Miscellaneous configurable options
 363  */
 364 #define CONFIG_SYS_LOAD_ADDR            0x2000000 /* default load address */
 365 #define CONFIG_SYS_HZ           1000    /* decrementer freq: 1ms ticks */
 366
 367 #define CONFIG_SYS_CBSIZE       1024 /* Console I/O Buffer Size */
 368
 369 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 370
 371 /*
 372  * For booting Linux, the board info and command line data
 373  * have to be in the first 256 MB of memory, since this is
 374  * the maximum mapped by the Linux kernel during initialization.
 375  */
 376 #define CONFIG_SYS_BOOTMAPSZ    (256 << 20) /* Initial Memory map for Linux */
 377
 378 /*
 379  * Environment Configuration
 380  */
 381
 382 #define CONFIG_ENV_OVERWRITE
 383
 384 #if defined(CONFIG_TSEC_ENET)
 385 #define CONFIG_HAS_ETH0
 386 #endif
 387
 388 #define CONFIG_LOADADDR 800000  /* default location for tftp and bootm */
 389
 390
 391 #define CONFIG_HOSTNAME         "hrcon"
 392 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 393 #define CONFIG_BOOTFILE         "uImage"
 394
 395 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 396         "netdev=eth0\0"                                                 \
 397         "consoledev=ttyS1\0"                                            \
 398         "u-boot=u-boot.bin\0"                                           \
 399         "kernel_addr=1000000\0"                                 \
 400         "fdt_addr=C00000\0"                                             \
 401         "fdtfile=hrcon.dtb\0"                           \
 402         "load=tftp ${loadaddr} ${u-boot}\0"                             \
 403         "update=protect off " __stringify(CONFIG_SYS_MONITOR_BASE)      \
 404                 " +${filesize};era " __stringify(CONFIG_SYS_MONITOR_BASE)\
 405                 " +${filesize};cp.b ${fileaddr} "                       \
 406                 __stringify(CONFIG_SYS_MONITOR_BASE) " ${filesize}\0"   \
 407         "upd=run load update\0"                                         \
 408
 409 #define CONFIG_NFSBOOTCOMMAND                                           \
 410         "setenv bootargs root=/dev/nfs rw "                             \
 411         "nfsroot=$serverip:$rootpath "                                  \
 412         "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 413         "console=$consoledev,$baudrate $othbootargs;"                   \
 414         "tftp ${kernel_addr} $bootfile;"                                \
 415         "tftp ${fdt_addr} $fdtfile;"                                    \
 416         "bootm ${kernel_addr} - ${fdt_addr}"
 417
 418 #define CONFIG_MMCBOOTCOMMAND                                           \
 419         "setenv bootargs root=/dev/mmcblk0p3 rw rootwait "              \
 420         "console=$consoledev,$baudrate $othbootargs;"                   \
 421         "ext2load mmc 0:2 ${kernel_addr} $bootfile;"                    \
 422         "ext2load mmc 0:2 ${fdt_addr} $fdtfile;"                        \
 423         "bootm ${kernel_addr} - ${fdt_addr}"
 424
 425 #define CONFIG_BOOTCOMMAND              CONFIG_MMCBOOTCOMMAND
 426
 427 #endif  /* __CONFIG_H */