include/configs/hymod.h

   1 /*
   2  * (C) Copyright 2000
   3  * Murray Jensen <Murray.Jensen@cmst.csiro.au>
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * Config header file for Hymod board
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * High Level Configuration Options
  33  * (easy to change)
  34  */
  35
  36 #define CONFIG_MPC8260          1       /* This is an MPC8260 CPU       */
  37 #define CONFIG_HYMOD            1       /* ...on a Hymod board          */
  38
  39 #define CONFIG_BOARD_POSTCLK_INIT       /* have board_postclk_init() function */
  40
  41 /*
  42  * select serial console configuration
  43  *
  44  * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  45  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  46  * for SCC).
  47  *
  48  * if CONFIG_CONS_NONE is defined, then the serial console routines must
  49  * defined elsewhere (for example, on the cogent platform, there are serial
  50  * ports on the motherboard which are used for the serial console - see
  51  * cogent/cma101/serial.[ch]).
  52  */
  53 #undef  CONFIG_CONS_ON_SMC              /* define if console on SMC */
  54 #define CONFIG_CONS_ON_SCC              /* define if console on SCC */
  55 #undef  CONFIG_CONS_NONE                /* define if console on something else*/
  56 #define CONFIG_CONS_INDEX       1       /* which serial channel for console */
  57 #define CONFIG_CONS_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
  58 #define CONFIG_CONS_EXTC_RATE   3686400 /* SMC/SCC ext clk rate in Hz */
  59 #define CONFIG_CONS_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
  60
  61 /*
  62  * select ethernet configuration
  63  *
  64  * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
  65  * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
  66  * for FCC)
  67  *
  68  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
  69  * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
  70  * from CONFIG_COMMANDS to remove support for networking.
  71  */
  72 #undef  CONFIG_ETHER_ON_SCC             /* define if ether on SCC       */
  73 #define CONFIG_ETHER_ON_FCC             /* define if ether on FCC       */
  74 #undef  CONFIG_ETHER_NONE               /* define if ether on something else */
  75 #define CONFIG_ETHER_INDEX      1       /* which channel for ether      */
  76
  77 #if (CONFIG_ETHER_INDEX == 1)
  78
  79 /*
  80  * - Rx-CLK is CLK10
  81  * - Tx-CLK is CLK11
  82  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  83  * - Enable Full Duplex in FSMR
  84  */
  85 # define CFG_CMXFCR_MASK        (CMXFCR_FC1|CMXFCR_RF1CS_MSK|CMXFCR_TF1CS_MSK)
  86 # define CFG_CMXFCR_VALUE       (CMXFCR_RF1CS_CLK10|CMXFCR_TF1CS_CLK11)
  87 # define CFG_CPMFCR_RAMTYPE     0
  88 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
  89
  90 #elif (CONFIG_ETHER_INDEX == 2)
  91
  92 /*
  93  * - Rx-CLK is CLK13
  94  * - Tx-CLK is CLK14
  95  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
  96  * - Enable Full Duplex in FSMR
  97  */
  98 # define CFG_CMXFCR_MASK        (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
  99 # define CFG_CMXFCR_VALUE       (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
 100 # define CFG_CPMFCR_RAMTYPE     0
 101 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 102
 103 #elif (CONFIG_ETHER_INDEX == 3)
 104
 105 /*
 106  * - Rx-CLK is CLK15
 107  * - Tx-CLK is CLK16
 108  * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
 109  * - Enable Full Duplex in FSMR
 110  */
 111 # define CFG_CMXFCR_MASK        (CMXFCR_FC3|CMXFCR_RF3CS_MSK|CMXFCR_TF3CS_MSK)
 112 # define CFG_CMXFCR_VALUE       (CMXFCR_RF3CS_CLK15|CMXFCR_TF3CS_CLK16)
 113 # define CFG_CPMFCR_RAMTYPE     0
 114 # define CFG_FCC_PSMR           (FCC_PSMR_FDE|FCC_PSMR_LPB)
 115
 116 #endif  /* CONFIG_ETHER_INDEX */
 117
 118
 119 /* other options */
 120 #define CONFIG_HARD_I2C         1       /* To enable I2C hardware support       */
 121
 122 /* system clock rate (CLKIN) - equal to the 60x and local bus speed */
 123 #ifdef DEBUG
 124 #define CONFIG_8260_CLKIN       33333333        /* in Hz */
 125 #else
 126 #define CONFIG_8260_CLKIN       66666666        /* in Hz */
 127 #endif
 128
 129 #if defined(CONFIG_CONS_USE_EXTC)
 130 #define CONFIG_BAUDRATE         115200
 131 #else
 132 #define CONFIG_BAUDRATE         38400
 133 #endif
 134
 135 /* default ip addresses - these will be overridden */
 136 #define CONFIG_IPADDR           192.168.1.1     /* hymod "boot" address */
 137 #define CONFIG_SERVERIP         192.168.1.254   /* hymod "server" address */
 138
 139 #define CONFIG_COMMANDS         (CFG_CMD_ALL & ~( \
 140                                         CFG_CMD_BEDBUG  | \
 141                                         CFG_CMD_DOC     | \
 142                                         CFG_CMD_ELF     | \
 143                                         CFG_CMD_FDC     | \
 144                                         CFG_CMD_HWFLOW  | \
 145                                         CFG_CMD_IDE     | \
 146                                         CFG_CMD_JFFS2   | \
 147                                         CFG_CMD_MII     | \
 148                                         CFG_CMD_PCMCIA  | \
 149                                         CFG_CMD_PCI     | \
 150                                         CFG_CMD_USB     | \
 151                                         CFG_CMD_SCSI    | \
 152                                         CFG_CMD_SPI     | \
 153                                         CFG_CMD_VFD     | \
 154                                         CFG_CMD_DTT     ) )
 155
 156 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 157 #include <cmd_confdefs.h>
 158
 159 #ifdef DEBUG
 160 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 161 #endif
 162
 163 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 164 #undef  CONFIG_KGDB_ON_SMC              /* define if kgdb on SMC */
 165 #define CONFIG_KGDB_ON_SCC              /* define if kgdb on SCC */
 166 #undef  CONFIG_KGDB_NONE                /* define if kgdb on something else */
 167 #define CONFIG_KGDB_INDEX       2       /* which serial channel for kgdb */
 168 #define CONFIG_KGDB_USE_EXTC            /* SMC/SCC use ext clock not brg_clk */
 169 #define CONFIG_KGDB_EXTC_RATE   3686400 /* serial ext clk rate in Hz */
 170 #define CONFIG_KGDB_EXTC_PINSEL 0       /* pin select 0=CLK3/CLK9,1=CLK5/CLK15*/
 171 # if defined(CONFIG_KGDB_USE_EXTC)
 172 #define CONFIG_KGDB_BAUDRATE    115200  /* speed to run kgdb serial port at */
 173 # else
 174 #define CONFIG_KGDB_BAUDRATE    38400   /* speed to run kgdb serial port at */
 175 # endif
 176 #endif
 177
 178 #undef  CONFIG_WATCHDOG                 /* disable platform specific watchdog */
 179
 180 #define CONFIG_RTC_PCF8563              /* use Philips PCF8563 RTC      */
 181
 182 /*
 183  * Hymod specific configurable options
 184  */
 185 #undef  CFG_HYMOD_DBLEDS                        /* walk mezz board LEDs */
 186
 187 /*
 188  * Miscellaneous configurable options
 189  */
 190 #define CFG_LONGHELP                    /* undef to save memory         */
 191 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 192 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 193 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 194 #else
 195 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 196 #endif
 197 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 198 #define CFG_MAXARGS     16              /* max number of command args   */
 199 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 200
 201 #define CFG_MEMTEST_START       0x00400000      /* memtest works on     */
 202 #define CFG_MEMTEST_END         0x03c00000      /* 4 ... 60 MB in DRAM  */
 203
 204 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 205
 206 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 207
 208 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
 209
 210 #define CFG_I2C_SPEED           50000
 211 #define CFG_I2C_SLAVE           0x7e
 212
 213 /* these are for the ST M24C02 2kbit serial i2c eeprom */
 214 #define CFG_I2C_EEPROM_ADDR     0x50            /* base address */
 215 #define CFG_I2C_EEPROM_ADDR_LEN 1               /* bytes of address */
 216 #define CFG_I2C_RTC_ADDR        0x51    /* philips PCF8563 RTC address */
 217
 218 /*
 219  * Low Level Configuration Settings
 220  * (address mappings, register initial values, etc.)
 221  * You should know what you are doing if you make changes here.
 222  */
 223
 224 /*-----------------------------------------------------------------------
 225  * Hard Reset Configuration Words
 226  *
 227  * if you change bits in the HRCW, you must also change the CFG_*
 228  * defines for the various registers affected by the HRCW e.g. changing
 229  * HRCW_DPPCxx requires you to also change CFG_SIUMCR.
 230  */
 231 #ifdef DEBUG
 232 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
 233                          HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
 234                          HRCW_MODCK_H0010)
 235 #else
 236 #define CFG_HRCW_MASTER (HRCW_BPS11|HRCW_CIP|HRCW_L2CPC01|HRCW_DPPC10|\
 237                          HRCW_ISB100|HRCW_BMS|HRCW_MMR11|HRCW_APPC10|\
 238                          HRCW_MODCK_H0101)
 239 #endif
 240 /* no slaves so just duplicate the master hrcw */
 241 #define CFG_HRCW_SLAVE1 CFG_HRCW_MASTER
 242 #define CFG_HRCW_SLAVE2 CFG_HRCW_MASTER
 243 #define CFG_HRCW_SLAVE3 CFG_HRCW_MASTER
 244 #define CFG_HRCW_SLAVE4 CFG_HRCW_MASTER
 245 #define CFG_HRCW_SLAVE5 CFG_HRCW_MASTER
 246 #define CFG_HRCW_SLAVE6 CFG_HRCW_MASTER
 247 #define CFG_HRCW_SLAVE7 CFG_HRCW_MASTER
 248
 249 /*-----------------------------------------------------------------------
 250  * Internal Memory Mapped Register
 251  */
 252 #define CFG_IMMR                0xF0000000
 253
 254 /*-----------------------------------------------------------------------
 255  * Definitions for initial stack pointer and data area (in DPRAM)
 256  */
 257 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 258 #define CFG_INIT_RAM_END        0x4000  /* End of used area in DPRAM    */
 259 #define CFG_GBL_DATA_SIZE       128  /* size in bytes reserved for initial data */
 260 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 261 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 262
 263 /*-----------------------------------------------------------------------
 264  * Start addresses for the final memory configuration
 265  * (Set up by the startup code)
 266  * Please note that CFG_SDRAM_BASE _must_ start at 0
 267  */
 268 #define CFG_SDRAM_BASE          0x00000000
 269 #define CFG_FLASH_BASE          TEXT_BASE
 270 #define CFG_MONITOR_BASE        TEXT_BASE
 271 #define CFG_FPGA_BASE           0x80000000
 272 /*
 273  * unfortunately, CFG_MONITOR_LEN must include the
 274  * (very large i.e. 256kB) environment flash sector
 275  */
 276 #define CFG_MONITOR_LEN         (512 << 10)     /* Reserve 512 kB for Monitor*/
 277 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()*/
 278
 279 /*
 280  * For booting Linux, the board info and command line data
 281  * have to be in the first 8 MB of memory, since this is
 282  * the maximum mapped by the Linux kernel during initialization.
 283  */
 284 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Mem map for Linux*/
 285
 286 /*-----------------------------------------------------------------------
 287  * FLASH organization
 288  */
 289 #define CFG_MAX_FLASH_BANKS     2       /* max num of memory banks      */
 290 #define CFG_MAX_FLASH_SECT      67      /* max num of sects on one chip */
 291
 292 #define CFG_FLASH_ERASE_TOUT    120000  /* Flash Erase Timeout (in ms)  */
 293 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 294
 295 #define CFG_FLASH_TYPE          FLASH_28F640J3A
 296 #define CFG_FLASH_ID            (INTEL_ID_28F640J3A & 0xff)
 297 #define CFG_FLASH_NBLOCKS       64
 298
 299 #define CFG_ENV_IS_IN_FLASH     1
 300 #define CFG_ENV_SIZE            0x1000  /* Total Size of Environment Sector */
 301 #define CFG_ENV_SECT_SIZE       0x40000 /* see README - env sect real size */
 302 #define CFG_ENV_ADDR    (CFG_FLASH_BASE+CFG_MONITOR_LEN-CFG_ENV_SECT_SIZE)
 303
 304 /*-----------------------------------------------------------------------
 305  * Cache Configuration
 306  */
 307 #define CFG_CACHELINE_SIZE      32      /* For MPC8260 CPU              */
 308 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 309 #define CFG_CACHELINE_SHIFT     5       /* log base 2 of the above value*/
 310 #endif
 311
 312 /*-----------------------------------------------------------------------
 313  * HIDx - Hardware Implementation-dependent Registers                    2-11
 314  *-----------------------------------------------------------------------
 315  * HID0 also contains cache control - initially enable both caches and
 316  * invalidate contents, then the final state leaves only the instruction
 317  * cache enabled. Note that Power-On and Hard reset invalidate the caches,
 318  * but Soft reset does not.
 319  *
 320  * HID1 has only read-only information - nothing to set.
 321  */
 322 #define CFG_HID0_INIT   (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
 323                                 HID0_IFEM|HID0_ABE)
 324 #ifdef DEBUG
 325 #define CFG_HID0_FINAL  0
 326 #else
 327 #define CFG_HID0_FINAL  (HID0_ICE|HID0_IFEM|HID0_ABE)
 328 #endif
 329 #define CFG_HID2        0
 330
 331 /*-----------------------------------------------------------------------
 332  * RMR - Reset Mode Register                                     5-5
 333  *-----------------------------------------------------------------------
 334  * turn on Checkstop Reset Enable
 335  */
 336 #ifdef DEBUG
 337 #define CFG_RMR         0
 338 #else
 339 #define CFG_RMR         RMR_CSRE
 340 #endif
 341
 342 /*-----------------------------------------------------------------------
 343  * BCR - Bus Configuration                                       4-25
 344  *-----------------------------------------------------------------------
 345  */
 346 #define CFG_BCR         (BCR_ETM)
 347
 348 /*-----------------------------------------------------------------------
 349  * SIUMCR - SIU Module Configuration                             4-31
 350  *-----------------------------------------------------------------------
 351  */
 352 #define CFG_SIUMCR      (SIUMCR_DPPC10|SIUMCR_L2CPC01|\
 353                          SIUMCR_APPC10|SIUMCR_MMR11)
 354
 355 /*-----------------------------------------------------------------------
 356  * SYPCR - System Protection Control                             4-35
 357  * SYPCR can only be written once after reset!
 358  *-----------------------------------------------------------------------
 359  * Watchdog & Bus Monitor Timer max, 60x & Local Bus Monitor enable
 360  */
 361 #if defined(CONFIG_WATCHDOG)
 362 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 363                          SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
 364 #else
 365 #define CFG_SYPCR       (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
 366                          SYPCR_SWRI|SYPCR_SWP)
 367 #endif /* CONFIG_WATCHDOG */
 368
 369 /*-----------------------------------------------------------------------
 370  * TMCNTSC - Time Counter Status and Control                     4-40
 371  *-----------------------------------------------------------------------
 372  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 373  * and enable Time Counter
 374  */
 375 #define CFG_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 376
 377 /*-----------------------------------------------------------------------
 378  * PISCR - Periodic Interrupt Status and Control                 4-42
 379  *-----------------------------------------------------------------------
 380  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 381  * Periodic timer
 382  */
 383 #define CFG_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 384
 385 /*-----------------------------------------------------------------------
 386  * SCCR - System Clock Control                                   9-8
 387  *-----------------------------------------------------------------------
 388  * Ensure DFBRG is Divide by 16
 389  */
 390 #define CFG_SCCR        (SCCR_DFBRG01)
 391
 392 /*-----------------------------------------------------------------------
 393  * RCCR - RISC Controller Configuration                         13-7
 394  *-----------------------------------------------------------------------
 395  */
 396 #define CFG_RCCR        0
 397
 398 /*
 399  * Init Memory Controller:
 400  *
 401  * Bank Bus     Machine PortSz  Device
 402  * ---- ---     ------- ------  ------
 403  *  0   60x     GPCM    32 bit  FLASH
 404  *  1   60x     GPCM    32 bit  FLASH (same as 0 - unused for now)
 405  *  2   60x     SDRAM   64 bit  SDRAM
 406  *  3   Local   UPMC     8 bit  Main Xilinx configuration
 407  *  4   Local   GPCM    32 bit  Main Xilinx register mode
 408  *  5   Local   UPMB    32 bit  Main Xilinx port mode
 409  *  6   Local   UPMC     8 bit  Mezz Xilinx configuration
 410  */
 411
 412 /*
 413  * Bank 0 - FLASH
 414  *
 415  * Quotes from the HYMOD IO Board Reference manual:
 416  *
 417  * "The flash memory is two Intel StrataFlash chips, each configured for
 418  *  16 bit operation and connected to give a 32 bit wide port."
 419  *
 420  * "The chip select logic is configured to respond to both *CS0 and *CS1.
 421  *  Therefore the FLASH memory will be mapped to both bank 0 and bank 1.
 422  *  It is suggested that bank 0 be read-only and bank 1 be read/write. The
 423  *  FLASH will then appear as ROM during boot."
 424  *
 425  * Initially, we are only going to use bank 0 in read/write mode.
 426  */
 427
 428 /* 32 bit, read-write, GPCM on 60x bus */
 429 #define CFG_BR0_PRELIM  ((CFG_FLASH_BASE&BRx_BA_MSK)|\
 430                                 BRx_PS_32|BRx_MS_GPCM_P|BRx_V)
 431 /* up to 32 Mb */
 432 #define CFG_OR0_PRELIM  (MEG_TO_AM(32)|ORxG_CSNT|ORxG_ACS_DIV2|ORxG_SCY_10_CLK)
 433
 434 /*
 435  * Bank 2 - SDRAM
 436  *
 437  * Quotes from the HYMOD IO Board Reference manual:
 438  *
 439  * "The main memory is implemented using TC59SM716FTL-10 SDRAM and has a
 440  *  fixed size of 64 Mbytes. The Toshiba TC59SM716FTL-10 is a CMOS synchronous
 441  *  dynamic random access memory organised as 4 banks by 4096 rows by 512
 442  *  columns by 16 bits. Four chips provide a 64-bit port on the 60x bus."
 443  *
 444  * "The locations in SDRAM are accessed using multiplexed address pins to
 445  *  specify row and column. The pins also act to specify commands. The state
 446  *  of the inputs *RAS, *CAS and *WE defines the required action. The a10/AP
 447  *  pin may function as a row address or as the AUTO PRECHARGE control line,
 448  *  depending on the cycle type. The 60x bus SDRAM machine allows the MPC8260
 449  *  address lines to be configured to the required multiplexing scheme."
 450  */
 451
 452 #define CFG_SDRAM_SIZE  64
 453
 454 /* 64 bit, read-write, SDRAM on 60x bus */
 455 #define CFG_BR2_PRELIM  ((CFG_SDRAM_BASE&BRx_BA_MSK)|\
 456                                 BRx_PS_64|BRx_MS_SDRAM_P|BRx_V)
 457 /* 64 Mb, 4 int banks per dev, row start addr bit = A6, 12 row addr lines */
 458 #define CFG_OR2_PRELIM  (MEG_TO_AM(CFG_SDRAM_SIZE)|\
 459                                 ORxS_BPD_4|ORxS_ROWST_PBI1_A6|ORxS_NUMR_12)
 460
 461 /*
 462  * The 60x Bus SDRAM Mode Register (PDSMR) is set as follows:
 463  *
 464  * Page Based Interleaving, Refresh Enable, Address Multiplexing where A5
 465  * is output on A16 pin (A6 on A17, and so on), use address pins A14-A16
 466  * as bank select, A7 is output on SDA10 during an ACTIVATE command,
 467  * earliest timing for ACTIVATE command after REFRESH command is 6 clocks,
 468  * earliest timing for ACTIVATE or REFRESH command after PRECHARGE command
 469  * is 2 clocks, earliest timing for READ/WRITE command after ACTIVATE
 470  * command is 2 clocks, earliest timing for PRECHARGE after last data
 471  * was read is 1 clock, earliest timing for PRECHARGE after last data
 472  * was written is 1 clock, CAS Latency is 2.
 473  */
 474
 475 #define CFG_PSDMR       (PSDMR_PBI|PSDMR_SDAM_A16_IS_A5|\
 476                                 PSDMR_BSMA_A14_A16|PSDMR_SDA10_PBI1_A7|\
 477                                 PSDMR_RFRC_6_CLK|PSDMR_PRETOACT_2W|\
 478                                 PSDMR_ACTTORW_2W|PSDMR_LDOTOPRE_1C|\
 479                                 PSDMR_WRC_1C|PSDMR_CL_2)
 480
 481 /*
 482  * The 60x bus-assigned SDRAM Refresh Timer (PSRT) (10-31) and the Refresh
 483  * Timers Prescale (PTP) value in the Memory Refresh Timer Prescaler Register
 484  * (MPTPR) (10-32) must also be set up (it used to be called the Periodic Timer
 485  * Prescaler, hence the P instead of the R). The refresh timer period is given
 486  * by (note that there was a change in the 8260 UM Errata):
 487  *
 488  *      TimerPeriod = (PSRT + 1) / Fmptc
 489  *
 490  * where Fmptc is the BusClock divided by PTP. i.e.
 491  *
 492  *      TimerPeriod = (PSRT + 1) / (BusClock / PTP)
 493  *
 494  * or
 495  *
 496  *      TImerPeriod = (PTP * (PSRT + 1)) / BusClock
 497  *
 498  * The requirement for the Toshiba TC59SM716FTL-10 is that there must be
 499  * 4K refresh cycles every 64 ms. i.e. one refresh cycle every 64000/4096
 500  * = 15.625 usecs.
 501  *
 502  * So PTP * (PSRT + 1) <= 15.625 * BusClock. At 66.666MHz, PSRT=31 and PTP=32
 503  * appear to be reasonable.
 504  */
 505
 506 #ifdef DEBUG
 507 #define CFG_PSRT        39
 508 #define CFG_MPTPR       MPTPR_PTP_DIV8
 509 #else
 510 #define CFG_PSRT        31
 511 #define CFG_MPTPR       MPTPR_PTP_DIV32
 512 #endif
 513
 514 /*
 515  * Banks 3,4,5 and 6 - FPGA access
 516  *
 517  * Quotes from the HYMOD IO Board Reference manual:
 518  *
 519  * "The IO Board is fitted with a Xilinx XCV300E main FPGA. Provision is made
 520  *  for configuring an optional FPGA on the mezzanine interface.
 521  *
 522  *  Access to the FPGAs may be divided into several catagories:
 523  *
 524  *  1. Configuration
 525  *  2. Register mode access
 526  *  3. Port mode access
 527  *
 528  *  The main FPGA is supported for modes 1, 2 and 3. The mezzanine FPGA can be
 529  *  configured only (mode 1). Consequently there are four access types.
 530  *
 531  *  To improve interface performance and simplify software design, the four
 532  *  possible access types are separately mapped to different memory banks.
 533  *
 534  *  All are accessed using the local bus."
 535  *
 536  *       Device             Mode      Memory Bank Machine Port Size    Access
 537  *
 538  *        Main          Configuration      3       UPMC      8bit       R/W
 539  *        Main            Register         4       GPCM     32bit       R/W
 540  *        Main              Port           5       UPMB     32bit       R/W
 541  *      Mezzanine       Configuration      6       UPMC      8bit       W/O
 542  *
 543  * "Note that mezzanine mode 1 access is write-only."
 544  */
 545
 546 /* all the bank sizes must be a power of two, greater or equal to 32768 */
 547 #define FPGA_MAIN_CFG_BASE      (CFG_FPGA_BASE)
 548 #define FPGA_MAIN_CFG_SIZE      32768
 549 #define FPGA_MAIN_REG_BASE      (FPGA_MAIN_CFG_BASE + FPGA_MAIN_CFG_SIZE)
 550 #define FPGA_MAIN_REG_SIZE      32768
 551 #define FPGA_MAIN_PORT_BASE     (FPGA_MAIN_REG_BASE + FPGA_MAIN_REG_SIZE)
 552 #define FPGA_MAIN_PORT_SIZE     32768
 553 #define FPGA_MEZZ_CFG_BASE      (FPGA_MAIN_PORT_BASE + FPGA_MAIN_PORT_SIZE)
 554 #define FPGA_MEZZ_CFG_SIZE      32768
 555
 556 /* 8 bit, read-write, UPMC */
 557 #define CFG_BR3_PRELIM  (FPGA_MAIN_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
 558 /* up to 32Kbyte, burst inhibit */
 559 #define CFG_OR3_PRELIM  (P2SZ_TO_AM(FPGA_MAIN_CFG_SIZE)|ORxU_BI)
 560
 561 /* 32 bit, read-write, GPCM */
 562 #define CFG_BR4_PRELIM  (FPGA_MAIN_REG_BASE|BRx_PS_32|BRx_MS_GPCM_L|BRx_V)
 563 /* up to 32Kbyte */
 564 #define CFG_OR4_PRELIM  (P2SZ_TO_AM(FPGA_MAIN_REG_SIZE))
 565
 566 /* 32 bit, read-write, UPMB */
 567 #define CFG_BR5_PRELIM  (FPGA_MAIN_PORT_BASE|BRx_PS_32|BRx_MS_UPMB|BRx_V)
 568 /* up to 32Kbyte */
 569 #define CFG_OR5_PRELIM  (P2SZ_TO_AM(FPGA_MAIN_PORT_SIZE)|ORxU_BI)
 570
 571 /* 8 bit, write-only, UPMC */
 572 #define CFG_BR6_PRELIM  (FPGA_MEZZ_CFG_BASE|BRx_PS_8|BRx_MS_UPMC|BRx_V)
 573 /* up to 32Kbyte, burst inhibit */
 574 #define CFG_OR6_PRELIM  (P2SZ_TO_AM(FPGA_MEZZ_CFG_SIZE)|ORxU_BI)
 575
 576 /*-----------------------------------------------------------------------
 577  * MBMR - Machine B Mode                                        10-27
 578  *-----------------------------------------------------------------------
 579  */
 580 #define CFG_MBMR        (MxMR_BSEL|MxMR_OP_NORM)        /* XXX - needs more */
 581
 582 /*-----------------------------------------------------------------------
 583  * MCMR - Machine C Mode                                        10-27
 584  *-----------------------------------------------------------------------
 585  */
 586 #define CFG_MCMR        (MxMR_BSEL|MxMR_DSx_2_CYCL)     /* XXX - needs more */
 587
 588 /*
 589  * FPGA I/O Port/Bit information
 590  */
 591
 592 #define FPGA_MAIN_PROG_PORT     IOPIN_PORTA
 593 #define FPGA_MAIN_PROG_PIN      4       /* PA4 */
 594 #define FPGA_MAIN_INIT_PORT     IOPIN_PORTA
 595 #define FPGA_MAIN_INIT_PIN      5       /* PA5 */
 596 #define FPGA_MAIN_DONE_PORT     IOPIN_PORTA
 597 #define FPGA_MAIN_DONE_PIN      6       /* PA6 */
 598
 599 #define FPGA_MEZZ_PROG_PORT     IOPIN_PORTA
 600 #define FPGA_MEZZ_PROG_PIN      0       /* PA0 */
 601 #define FPGA_MEZZ_INIT_PORT     IOPIN_PORTA
 602 #define FPGA_MEZZ_INIT_PIN      1       /* PA1 */
 603 #define FPGA_MEZZ_DONE_PORT     IOPIN_PORTA
 604 #define FPGA_MEZZ_DONE_PIN      2       /* PA2 */
 605 #define FPGA_MEZZ_ENABLE_PORT   IOPIN_PORTA
 606 #define FPGA_MEZZ_ENABLE_PIN    3       /* PA3 */
 607
 608 /*
 609  * Internal Definitions
 610  *
 611  * Boot Flags
 612  */
 613 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH*/
 614 #define BOOTFLAG_WARM   0x02            /* Software reboot              */
 615
 616 #endif  /* __CONFIG_H */