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git.ipfire.org Git - thirdparty/u-boot.git/blob - include/configs/imx31_phycore.h
4 * Richard Woodruff <r-woodruff2@ti.com>
5 * Kshitij Gupta <kshitij@ti.com>
7 * Configuration settings for the phyCORE-i.MX31 board.
9 * SPDX-License-Identifier: GPL-2.0+
15 #include <asm/arch/imx-regs.h>
17 /* High Level Configuration Options */
18 #define CONFIG_MX31 /* This is a mx31 */
19 #define CONFIG_MX31_CLK32 32000
21 #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
22 #define CONFIG_SETUP_MEMORY_TAGS
23 #define CONFIG_INITRD_TAG
26 * Size of malloc() pool
28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 512 * 1024)
34 #define CONFIG_SYS_I2C
35 #define CONFIG_SYS_I2C_MXC
36 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
37 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
38 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
39 #define CONFIG_SYS_I2C_CLK_OFFSET I2C2_CLK_OFFSET
41 #define CONFIG_MXC_UART
42 #define CONFIG_MXC_UART_BASE UART1_BASE
44 /* allow to overwrite serial and ethaddr */
45 #define CONFIG_ENV_OVERWRITE
46 #define CONFIG_CONS_INDEX 1
48 /***********************************************************
50 ***********************************************************/
52 #define CONFIG_NETMASK 255.255.255.0
53 #define CONFIG_IPADDR 192.168.23.168
54 #define CONFIG_SERVERIP 192.168.23.2
56 #define CONFIG_EXTRA_ENV_SETTINGS \
57 "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \
58 "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs " \
59 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
60 "bootargs_flash=setenv bootargs $(bootargs) " \
61 "root=/dev/mtdblock2 rootfstype=jffs2\0" \
62 "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \
63 "bootcmd=run bootcmd_net\0" \
64 "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs;" \
65 "tftpboot 0x80000000 $(uimage);bootm\0" \
66 "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash;" \
67 "bootm 0x80000000\0" \
69 "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" \
70 "prg_uboot=tftpboot 0x80000000 $(uboot);" \
71 "protect off 0xa0000000 +0x20000;" \
72 "erase 0xa0000000 +0x20000;" \
73 "cp.b 0x80000000 0xa0000000 $(filesize)\0" \
74 "prg_kernel=tftpboot 0x80000000 $(uimage);" \
75 "erase 0xa0040000 +0x180000;" \
76 "cp.b 0x80000000 0xa0040000 $(filesize)\0" \
77 "prg_jffs2=tftpboot 0x80000000 $(jffs2);" \
78 "erase 0xa01c0000 0xa1ffffff;" \
79 "cp.b 0x80000000 0xa01c0000 $(filesize)\0" \
80 "videomode=video=ctfb:x:240,y:320,depth:16,mode:0," \
81 "pclk:185925,le:9,ri:17,up:7,lo:10,hs:1,vs:1," \
82 "sync:1241513985,vmode:0\0"
85 * Miscellaneous configurable options
87 #define CONFIG_SYS_LONGHELP /* undef to save memory */
89 #define CONFIG_SYS_MEMTEST_START 0 /* memtest works on */
90 #define CONFIG_SYS_MEMTEST_END 0x10000
92 #define CONFIG_SYS_LOAD_ADDR 0 /* default load address */
94 #define CONFIG_CMDLINE_EDITING
99 #define CONFIG_NR_DRAM_BANKS 1
100 #define PHYS_SDRAM_1 0x80000000
101 #define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024)
102 #define CONFIG_SYS_TEXT_BASE 0xA0000000
104 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
105 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
106 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
107 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
108 GENERATED_GBL_DATA_SIZE)
109 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
110 CONFIG_SYS_GBL_DATA_OFFSET)
113 * FLASH and environment organization
115 #define CONFIG_SYS_FLASH_BASE 0xa0000000
116 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max # of memory banks */
117 #define CONFIG_SYS_MAX_FLASH_SECT 259 /* max # of sectors/chip */
118 /* Monitor at beginning of flash */
119 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
121 #define CONFIG_ENV_OFFSET 0x00 /* env. starts here */
122 #define CONFIG_ENV_SIZE 4096
123 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x52
124 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* 5 bits = 32 octets */
125 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* 10 ms delay */
126 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* byte addr. lenght */
129 * CFI FLASH driver setup
131 #define CONFIG_SYS_FLASH_CFI /* Flash memory is CFI compliant */
132 #define CONFIG_FLASH_CFI_DRIVER /* Use drivers/mtd/cfi_flash.c */
133 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffered writes (~10x faster) */
134 #define CONFIG_SYS_FLASH_PROTECTION /* Use hardware sector protection */
137 * Timeout for Flash Erase and Flash Write
138 * timeout values are in ticks
140 #define CONFIG_SYS_FLASH_ERASE_TOUT (100*CONFIG_SYS_HZ)
141 #define CONFIG_SYS_FLASH_WRITE_TOUT (100*CONFIG_SYS_HZ)
146 #define CONFIG_JFFS2_DEV "nor0"
148 /* EET platform additions */
149 #ifdef CONFIG_TARGET_IMX31_PHYCORE_EET
150 #define CONFIG_MXC_GPIO
152 #define CONFIG_HARD_SPI
153 #define CONFIG_MXC_SPI
155 #define CONFIG_S6E63D6
157 #define CONFIG_VIDEO_MX3
158 #define CONFIG_VIDEO_LOGO
159 #define CONFIG_SPLASH_SCREEN
160 #define CONFIG_BMP_16BPP
163 #endif /* __CONFIG_H */