include/configs/inka4x0.h

   1 /*
   2  * (C) Copyright 2009
   3  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4  *
   5  * (C) Copyright 2003-2005
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  * (easy to change)
  17  */
  18
  19 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU       */
  20 #define CONFIG_INKA4X0          1       /* INKA4x0 board                */
  21 #define CONFIG_SYS_GENERIC_BOARD
  22 #define CONFIG_DISPLAY_BOARDINFO
  23
  24 /*
  25  * Valid values for CONFIG_SYS_TEXT_BASE are:
  26  * 0xFFE00000   boot low
  27  * 0x00100000   boot from RAM (for testing only)
  28  */
  29 #ifndef CONFIG_SYS_TEXT_BASE
  30 #define CONFIG_SYS_TEXT_BASE    0xFFE00000      /* Standard: boot low */
  31 #endif
  32 #define CONFIG_SYS_LDSCRIPT     "arch/powerpc/cpu/mpc5xxx/u-boot-customlayout.lds"
  33
  34 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  35
  36 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  37
  38 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  39
  40 /*
  41  * Serial console configuration
  42  */
  43 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  44 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  45 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  46
  47 /*
  48  * PCI Mapping:
  49  * 0x40000000 - 0x4fffffff - PCI Memory
  50  * 0x50000000 - 0x50ffffff - PCI IO Space
  51  */
  52 #define CONFIG_PCI              1
  53 #define CONFIG_PCI_PNP          1
  54 #define CONFIG_PCI_SCAN_SHOW    1
  55 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  56
  57 #define CONFIG_PCI_MEM_BUS      0x40000000
  58 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  59 #define CONFIG_PCI_MEM_SIZE     0x10000000
  60
  61 #define CONFIG_PCI_IO_BUS       0x50000000
  62 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  63 #define CONFIG_PCI_IO_SIZE      0x01000000
  64
  65 #define CONFIG_SYS_XLB_PIPELINING       1
  66
  67 /* Partitions */
  68 #define CONFIG_MAC_PARTITION
  69 #define CONFIG_DOS_PARTITION
  70 #define CONFIG_ISO_PARTITION
  71
  72
  73 /*
  74  * BOOTP options
  75  */
  76 #define CONFIG_BOOTP_BOOTFILESIZE
  77 #define CONFIG_BOOTP_BOOTPATH
  78 #define CONFIG_BOOTP_GATEWAY
  79 #define CONFIG_BOOTP_HOSTNAME
  80
  81
  82 /*
  83  * Command line configuration.
  84  */
  85 #define CONFIG_CMD_DATE
  86 #define CONFIG_CMD_DHCP
  87 #define CONFIG_CMD_EXT2
  88 #define CONFIG_CMD_FAT
  89 #define CONFIG_CMD_IDE
  90 #define CONFIG_CMD_PCI
  91 #define CONFIG_CMD_PING
  92 #define CONFIG_CMD_SNTP
  93 #define CONFIG_CMD_USB
  94
  95 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  96
  97 #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)                /* Boot low */
  98 #   define CONFIG_SYS_LOWBOOT           1
  99 #endif
 100
 101 /*
 102  * Autobooting
 103  */
 104 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 105
 106 #define CONFIG_PREBOOT  "echo;" \
 107         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 108         "echo"
 109
 110 #undef  CONFIG_BOOTARGS
 111
 112 #define CONFIG_IPADDR           192.168.100.2
 113 #define CONFIG_SERVERIP         192.168.100.1
 114 #define CONFIG_NETMASK          255.255.255.0
 115 #define HOSTNAME                inka4x0
 116 #define CONFIG_BOOTFILE         "/tftpboot/inka4x0/uImage"
 117 #define CONFIG_ROOTPATH         "/opt/eldk/ppc_6xx"
 118
 119 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 120         "netdev=eth0\0"                                                 \
 121         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 122                 "nfsroot=${serverip}:${rootpath}\0"                     \
 123         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 124         "addip=setenv bootargs ${bootargs} "                            \
 125                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 126                 ":${hostname}:${netdev}:off panic=1\0"                  \
 127         "addcons=setenv bootargs ${bootargs} "                          \
 128                 "console=ttyS0,${baudrate}\0"                           \
 129         "flash_nfs=run nfsargs addip addcons;"                          \
 130                 "bootm ${kernel_addr}\0"                                \
 131         "net_nfs=tftp 200000 ${bootfile};"                              \
 132                 "run nfsargs addip addcons;bootm\0"                     \
 133         "enable_disp=mw.l 100000 04000000 1;"                           \
 134                 "cp.l 100000 f0000b20 1;"                               \
 135                 "cp.l 100000 f0000b28 1\0"                              \
 136         "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 137         "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 138                 "run ideargs addip addcons enable_disp;bootm\0"         \
 139         "brightness=255\0"                                              \
 140         ""
 141
 142 #define CONFIG_BOOTCOMMAND      "run ide_boot"
 143
 144 /*
 145  * IPB Bus clocking configuration.
 146  */
 147 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 148
 149 /*
 150  * Flash configuration
 151  */
 152 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 153 #define CONFIG_FLASH_CFI_DRIVER 1
 154 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 155 #define CONFIG_SYS_FLASH_SIZE           0x00200000
 156 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 157 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 158 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 159 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 160
 161 /*
 162  * Environment settings
 163  */
 164 #define CONFIG_ENV_IS_IN_FLASH  1
 165 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 166 #define CONFIG_ENV_SIZE         0x2000
 167 #define CONFIG_ENV_SECT_SIZE    0x2000
 168 #define CONFIG_ENV_OVERWRITE    1
 169 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 170
 171 /*
 172  * Memory map
 173  */
 174 #define CONFIG_SYS_MBAR         0xF0000000
 175 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 176 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 177
 178 /*
 179  * SDRAM controller configuration
 180  */
 181 #undef CONFIG_SDR_MT48LC16M16A2
 182 #undef CONFIG_DDR_MT46V16M16
 183 #undef CONFIG_DDR_MT46V32M16
 184 #undef CONFIG_DDR_HYB25D512160BF
 185 #define CONFIG_DDR_K4H511638C
 186
 187 /* Use ON-Chip SRAM until RAM will be available */
 188 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 189
 190 /* preserve space for the post_word at end of on-chip SRAM */
 191 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 192
 193 #ifdef CONFIG_POST
 194 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 195 #else
 196 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 197 #endif
 198
 199 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 200 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 201
 202 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 203 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 204 #   define CONFIG_SYS_RAMBOOT           1
 205 #endif
 206
 207 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 208 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 209 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 210
 211 /*
 212  * Ethernet configuration
 213  */
 214 #define CONFIG_MPC5xxx_FEC      1
 215 #define CONFIG_MPC5xxx_FEC_MII100
 216 /*
 217  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 218  */
 219 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 220 #define CONFIG_PHY_ADDR         0x00
 221 #define CONFIG_MII
 222
 223 /*
 224  * GPIO configuration
 225  *
 226  * use CS1 as gpio_wkup_6 output
 227  *      Bit 0 (mask: 0x80000000): 0
 228  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 229  *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 230  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 231  *            EEPROM
 232  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 233  * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 234  * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 235  * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 236  */
 237 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 238
 239 /*
 240  * RTC configuration
 241  */
 242 #define CONFIG_RTC_RTC4543      1       /* use external RTC */
 243
 244 /*
 245  * Software (bit-bang) three wire serial configuration
 246  *
 247  * Note that we need the ifdefs because otherwise compilation of
 248  * mkimage.c fails.
 249  */
 250 #define CONFIG_SOFT_TWS         1
 251
 252 #ifdef TWS_IMPLEMENTATION
 253 #include <mpc5xxx.h>
 254 #include <asm/io.h>
 255
 256 #define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 257 #define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 258 #define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 259 #define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 260
 261 static inline void tws_ce(unsigned bit)
 262 {
 263         struct mpc5xxx_wu_gpio *wu_gpio =
 264                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 265         if (bit)
 266                 setbits_8(&wu_gpio->dvo, TWS_CE);
 267         else
 268                 clrbits_8(&wu_gpio->dvo, TWS_CE);
 269 }
 270
 271 static inline void tws_wr(unsigned bit)
 272 {
 273         struct mpc5xxx_wu_gpio *wu_gpio =
 274                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 275         if (bit)
 276                 setbits_8(&wu_gpio->dvo, TWS_WR);
 277         else
 278                 clrbits_8(&wu_gpio->dvo, TWS_WR);
 279 }
 280
 281 static inline void tws_clk(unsigned bit)
 282 {
 283         struct mpc5xxx_gpio *gpio =
 284                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 285         if (bit)
 286                 setbits_8(&gpio->sint_dvo, TWS_CLK);
 287         else
 288                 clrbits_8(&gpio->sint_dvo, TWS_CLK);
 289 }
 290
 291 static inline void tws_data(unsigned bit)
 292 {
 293         struct mpc5xxx_gpio *gpio =
 294                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 295         if (bit)
 296                 setbits_8(&gpio->sint_dvo, TWS_DATA);
 297         else
 298                 clrbits_8(&gpio->sint_dvo, TWS_DATA);
 299 }
 300
 301 static inline unsigned tws_data_read(void)
 302 {
 303         struct mpc5xxx_gpio *gpio =
 304                         (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 305         return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 306 }
 307
 308 static inline void tws_data_config_output(unsigned output)
 309 {
 310         struct mpc5xxx_gpio *gpio =
 311                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 312         if (output)
 313                 setbits_8(&gpio->sint_ddr, TWS_DATA);
 314         else
 315                 clrbits_8(&gpio->sint_ddr, TWS_DATA);
 316 }
 317 #endif /* TWS_IMPLEMENTATION */
 318
 319 /*
 320  * Miscellaneous configurable options
 321  */
 322 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 323 #if defined(CONFIG_CMD_KGDB)
 324 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 325 #else
 326 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 327 #endif
 328 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 329 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 330 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 331
 332 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 333 #if defined(CONFIG_CMD_KGDB)
 334 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 335 #endif
 336
 337 /* Enable an alternate, more extensive memory test */
 338 #define CONFIG_SYS_ALT_MEMTEST
 339
 340 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 341 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 342
 343 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 344
 345 /*
 346  * Enable loopw command.
 347  */
 348 #define CONFIG_LOOPW
 349
 350 /*
 351  * Various low-level settings
 352  */
 353 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 354 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 355
 356 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 357 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 358 #define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 359 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 360 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 361
 362 /* 32Mbit SRAM @0x30000000 */
 363 #define CONFIG_SYS_CS1_START            0x30000000
 364 #define CONFIG_SYS_CS1_SIZE             0x00400000
 365 #define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 366
 367 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 368 #define CONFIG_SYS_CS2_START            0x80000000
 369 #define CONFIG_SYS_CS2_SIZE             0x0001000
 370 #define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 371
 372 /* GPIO in @0x30400000 */
 373 #define CONFIG_SYS_CS3_START            0x30400000
 374 #define CONFIG_SYS_CS3_SIZE             0x00100000
 375 #define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 376
 377 #define CONFIG_SYS_CS_BURST             0x00000000
 378 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 379
 380 /*-----------------------------------------------------------------------
 381  * USB stuff
 382  *-----------------------------------------------------------------------
 383  */
 384 #define CONFIG_USB_OHCI
 385 #define CONFIG_USB_CLOCK        0x00015555
 386 #define CONFIG_USB_CONFIG       0x00001000
 387 #define CONFIG_USB_STORAGE
 388
 389 /*-----------------------------------------------------------------------
 390  * IDE/ATA stuff Supports IDE harddisk
 391  *-----------------------------------------------------------------------
 392  */
 393
 394 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 395
 396 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 397 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 398
 399 #define CONFIG_IDE_PREINIT
 400
 401 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 402 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 403
 404 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 405 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 406 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 407 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 408 #define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 409 #define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 410
 411 #define CONFIG_ATAPI            1
 412
 413 #define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 414
 415 #endif /* __CONFIG_H */