include/configs/inka4x0.h

   1 /*
   2  * (C) Copyright 2009
   3  * Detlev Zundel, DENX Software Engineering, dzu@denx.de.
   4  *
   5  * (C) Copyright 2003-2005
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 /*
  31  * High Level Configuration Options
  32  * (easy to change)
  33  */
  34
  35 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  36 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU)      */
  37 #define CONFIG_INKA4X0          1       /* INKA4x0 board                        */
  38
  39 /*
  40  * Valid values for CONFIG_SYS_TEXT_BASE are:
  41  * 0xFFE00000   boot low
  42  * 0x00100000   boot from RAM (for testing only)
  43  */
  44 #ifndef CONFIG_SYS_TEXT_BASE
  45 #define CONFIG_SYS_TEXT_BASE    0xFFE00000      /* Standard: boot low */
  46 #endif
  47
  48 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz         */
  49
  50 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
  51 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
  52
  53 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  54
  55 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  56
  57 /*
  58  * Serial console configuration
  59  */
  60 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  61 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  62 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  63
  64 /*
  65  * PCI Mapping:
  66  * 0x40000000 - 0x4fffffff - PCI Memory
  67  * 0x50000000 - 0x50ffffff - PCI IO Space
  68  */
  69 #define CONFIG_PCI              1
  70 #define CONFIG_PCI_PNP          1
  71 #define CONFIG_PCI_SCAN_SHOW    1
  72 #define CONFIG_PCIAUTO_SKIP_HOST_BRIDGE 1
  73
  74 #define CONFIG_PCI_MEM_BUS      0x40000000
  75 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  76 #define CONFIG_PCI_MEM_SIZE     0x10000000
  77
  78 #define CONFIG_PCI_IO_BUS       0x50000000
  79 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  80 #define CONFIG_PCI_IO_SIZE      0x01000000
  81
  82 #define CONFIG_SYS_XLB_PIPELINING       1
  83
  84 /* Partitions */
  85 #define CONFIG_MAC_PARTITION
  86 #define CONFIG_DOS_PARTITION
  87 #define CONFIG_ISO_PARTITION
  88
  89
  90 /*
  91  * BOOTP options
  92  */
  93 #define CONFIG_BOOTP_BOOTFILESIZE
  94 #define CONFIG_BOOTP_BOOTPATH
  95 #define CONFIG_BOOTP_GATEWAY
  96 #define CONFIG_BOOTP_HOSTNAME
  97
  98
  99 /*
 100  * Command line configuration.
 101  */
 102 #include <config_cmd_default.h>
 103
 104 #define CONFIG_CMD_DATE
 105 #define CONFIG_CMD_DHCP
 106 #define CONFIG_CMD_EXT2
 107 #define CONFIG_CMD_FAT
 108 #define CONFIG_CMD_IDE
 109 #define CONFIG_CMD_NFS
 110 #define CONFIG_CMD_PCI
 111 #define CONFIG_CMD_PING
 112 #define CONFIG_CMD_SNTP
 113 #define CONFIG_CMD_USB
 114
 115 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
 116
 117 #if (CONFIG_SYS_TEXT_BASE == 0xFFE00000)                /* Boot low */
 118 #   define CONFIG_SYS_LOWBOOT           1
 119 #endif
 120
 121 /*
 122  * Autobooting
 123  */
 124 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 125
 126 #define CONFIG_PREBOOT  "echo;" \
 127         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 128         "echo"
 129
 130 #undef  CONFIG_BOOTARGS
 131
 132 #define CONFIG_ETHADDR          00:a0:a4:03:00:00
 133 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 134
 135 #define CONFIG_IPADDR           192.168.100.2
 136 #define CONFIG_SERVERIP         192.168.100.1
 137 #define CONFIG_NETMASK          255.255.255.0
 138 #define HOSTNAME                inka4x0
 139 #define CONFIG_BOOTFILE         /tftpboot/inka4x0/uImage
 140 #define CONFIG_ROOTPATH         /opt/eldk/ppc_6xx
 141
 142 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 143         "netdev=eth0\0"                                                 \
 144         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 145                 "nfsroot=${serverip}:${rootpath}\0"                     \
 146         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 147         "addip=setenv bootargs ${bootargs} "                            \
 148                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 149                 ":${hostname}:${netdev}:off panic=1\0"                  \
 150         "addcons=setenv bootargs ${bootargs} "                          \
 151                 "console=ttyS0,${baudrate}\0"                           \
 152         "flash_nfs=run nfsargs addip addcons;"                          \
 153                 "bootm ${kernel_addr}\0"                                \
 154         "net_nfs=tftp 200000 ${bootfile};"                              \
 155                 "run nfsargs addip addcons;bootm\0"                     \
 156         "enable_disp=mw.l 100000 04000000 1;"                           \
 157                 "cp.l 100000 f0000b20 1;"                               \
 158                 "cp.l 100000 f0000b28 1\0"                              \
 159         "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 160         "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 161                 "run ideargs addip addcons enable_disp;bootm\0"         \
 162         "brightness=255\0"                                              \
 163         ""
 164
 165 #define CONFIG_BOOTCOMMAND      "run ide_boot"
 166
 167 /*
 168  * IPB Bus clocking configuration.
 169  */
 170 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 171
 172 /*
 173  * Flash configuration
 174  */
 175 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 176 #define CONFIG_FLASH_CFI_DRIVER 1
 177 #define CONFIG_SYS_FLASH_BASE           0xffe00000
 178 #define CONFIG_SYS_FLASH_SIZE           0x00200000
 179 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of memory banks */
 180 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 181 #define CONFIG_SYS_MAX_FLASH_SECT       128     /* max num of sects on one chip */
 182 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster) */
 183
 184 /*
 185  * Environment settings
 186  */
 187 #define CONFIG_ENV_IS_IN_FLASH  1
 188 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH_BASE + 0x4000)
 189 #define CONFIG_ENV_SIZE         0x2000
 190 #define CONFIG_ENV_SECT_SIZE    0x2000
 191 #define CONFIG_ENV_OVERWRITE    1
 192 #define CONFIG_SYS_USE_PPCENV                   /* Environment embedded in sect .ppcenv */
 193
 194 /*
 195  * Memory map
 196  */
 197 #define CONFIG_SYS_MBAR         0xF0000000
 198 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 199 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 200
 201 /*
 202  * SDRAM controller configuration
 203  */
 204 #undef CONFIG_SDR_MT48LC16M16A2
 205 #undef CONFIG_DDR_MT46V16M16
 206 #undef CONFIG_DDR_MT46V32M16
 207 #undef CONFIG_DDR_HYB25D512160BF
 208 #define CONFIG_DDR_K4H511638C
 209
 210 /* Use ON-Chip SRAM until RAM will be available */
 211 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 212
 213 /* preserve space for the post_word at end of on-chip SRAM */
 214 #define MPC5XXX_SRAM_POST_SIZE (MPC5XXX_SRAM_SIZE - 4)
 215
 216 #ifdef CONFIG_POST
 217 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE
 218 #else
 219 #define CONFIG_SYS_INIT_RAM_END MPC5XXX_SRAM_SIZE
 220 #endif
 221
 222 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 223 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 224 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 225
 226 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 227 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 228 #   define CONFIG_SYS_RAMBOOT           1
 229 #endif
 230
 231 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 232 #define CONFIG_SYS_MALLOC_LEN           (128 << 10)     /* Reserve 128 kB for malloc()  */
 233 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 234
 235 /*
 236  * Ethernet configuration
 237  */
 238 #define CONFIG_MPC5xxx_FEC      1
 239 #define CONFIG_MPC5xxx_FEC_MII100
 240 /*
 241  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 242  */
 243 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 244 #define CONFIG_PHY_ADDR         0x00
 245 #define CONFIG_MII
 246
 247 /*
 248  * GPIO configuration
 249  *
 250  * use CS1 as gpio_wkup_6 output
 251  *      Bit 0 (mask: 0x80000000): 0
 252  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 253  *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 254  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 255  *            EEPROM
 256  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 257  * use PSC2 as UART: Bits 24-27 (mask: 0x00000070): 0100
 258  * use PSC3 as UART: Bits 20-23 (mask: 0x00000700): 0100
 259  * use PSC6 as UART: Bits  9-11 (mask: 0x00700000): 0101
 260  */
 261 #define CONFIG_SYS_GPS_PORT_CONFIG      0x01501444
 262
 263 /*
 264  * RTC configuration
 265  */
 266 #define CONFIG_RTC_RTC4543      1       /* use external RTC */
 267
 268 /*
 269  * Software (bit-bang) three wire serial configuration
 270  *
 271  * Note that we need the ifdefs because otherwise compilation of
 272  * mkimage.c fails.
 273  */
 274 #define CONFIG_SOFT_TWS         1
 275
 276 #ifdef TWS_IMPLEMENTATION
 277 #include <mpc5xxx.h>
 278 #include <asm/io.h>
 279
 280 #define TWS_CE          MPC5XXX_GPIO_WKUP_PSC1_4 /* GPIO_WKUP_0 */
 281 #define TWS_WR          MPC5XXX_GPIO_WKUP_PSC2_4 /* GPIO_WKUP_1 */
 282 #define TWS_DATA        MPC5XXX_GPIO_SINT_PSC3_4 /* GPIO_SINT_0 */
 283 #define TWS_CLK         MPC5XXX_GPIO_SINT_PSC3_5 /* GPIO_SINT_1 */
 284
 285 static inline void tws_ce(unsigned bit)
 286 {
 287         struct mpc5xxx_wu_gpio *wu_gpio =
 288                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 289         if (bit)
 290                 setbits_8(&wu_gpio->dvo, TWS_CE);
 291         else
 292                 clrbits_8(&wu_gpio->dvo, TWS_CE);
 293 }
 294
 295 static inline void tws_wr(unsigned bit)
 296 {
 297         struct mpc5xxx_wu_gpio *wu_gpio =
 298                 (struct mpc5xxx_wu_gpio *)MPC5XXX_WU_GPIO;
 299         if (bit)
 300                 setbits_8(&wu_gpio->dvo, TWS_WR);
 301         else
 302                 clrbits_8(&wu_gpio->dvo, TWS_WR);
 303 }
 304
 305 static inline void tws_clk(unsigned bit)
 306 {
 307         struct mpc5xxx_gpio *gpio =
 308                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 309         if (bit)
 310                 setbits_8(&gpio->sint_dvo, TWS_CLK);
 311         else
 312                 clrbits_8(&gpio->sint_dvo, TWS_CLK);
 313 }
 314
 315 static inline void tws_data(unsigned bit)
 316 {
 317         struct mpc5xxx_gpio *gpio =
 318                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 319         if (bit)
 320                 setbits_8(&gpio->sint_dvo, TWS_DATA);
 321         else
 322                 clrbits_8(&gpio->sint_dvo, TWS_DATA);
 323 }
 324
 325 static inline unsigned tws_data_read(void)
 326 {
 327         struct mpc5xxx_gpio *gpio =
 328                         (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 329         return !!(in_8(&gpio->sint_ival) & TWS_DATA);
 330 }
 331
 332 static inline void tws_data_config_output(unsigned output)
 333 {
 334         struct mpc5xxx_gpio *gpio =
 335                 (struct mpc5xxx_gpio *)MPC5XXX_GPIO;
 336         if (output)
 337                 setbits_8(&gpio->sint_ddr, TWS_DATA);
 338         else
 339                 clrbits_8(&gpio->sint_ddr, TWS_DATA);
 340 }
 341 #endif /* TWS_IMPLEMENTATION */
 342
 343 /*
 344  * Miscellaneous configurable options
 345  */
 346 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 347 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 348 #if defined(CONFIG_CMD_KGDB)
 349 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 350 #else
 351 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 352 #endif
 353 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 354 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 355 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 356
 357 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 358 #if defined(CONFIG_CMD_KGDB)
 359 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 360 #endif
 361
 362 /* Enable an alternate, more extensive memory test */
 363 #define CONFIG_SYS_ALT_MEMTEST
 364
 365 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 366 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 367
 368 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 369
 370 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 371
 372 /*
 373  * Enable loopw command.
 374  */
 375 #define CONFIG_LOOPW
 376
 377 /*
 378  * Various low-level settings
 379  */
 380 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 381 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 382
 383 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 384 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 385 #define CONFIG_SYS_BOOTCS_CFG           0x00087800 /* for pci_clk  = 66 MHz */
 386 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 387 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 388
 389 /* 32Mbit SRAM @0x30000000 */
 390 #define CONFIG_SYS_CS1_START            0x30000000
 391 #define CONFIG_SYS_CS1_SIZE             0x00400000
 392 #define CONFIG_SYS_CS1_CFG              0x31800 /* for pci_clk = 33 MHz */
 393
 394 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 395 #define CONFIG_SYS_CS2_START            0x80000000
 396 #define CONFIG_SYS_CS2_SIZE             0x0001000
 397 #define CONFIG_SYS_CS2_CFG              0x21800  /* for pci_clk = 33 MHz */
 398
 399 /* GPIO in @0x30400000 */
 400 #define CONFIG_SYS_CS3_START            0x30400000
 401 #define CONFIG_SYS_CS3_SIZE             0x00100000
 402 #define CONFIG_SYS_CS3_CFG              0x31800 /* for pci_clk = 33 MHz */
 403
 404 #define CONFIG_SYS_CS_BURST             0x00000000
 405 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 406
 407 /*-----------------------------------------------------------------------
 408  * USB stuff
 409  *-----------------------------------------------------------------------
 410  */
 411 #define CONFIG_USB_OHCI
 412 #define CONFIG_USB_CLOCK        0x00015555
 413 #define CONFIG_USB_CONFIG       0x00001000
 414 #define CONFIG_USB_STORAGE
 415
 416 /*-----------------------------------------------------------------------
 417  * IDE/ATA stuff Supports IDE harddisk
 418  *-----------------------------------------------------------------------
 419  */
 420
 421 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 422
 423 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 424 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 425
 426 #define CONFIG_IDE_PREINIT
 427
 428 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 429 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 430
 431 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 432 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 433 #define CONFIG_SYS_ATA_DATA_OFFSET      0x0060  /* Offset for data I/O          */
 434 #define CONFIG_SYS_ATA_REG_OFFSET (CONFIG_SYS_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 435 #define CONFIG_SYS_ATA_ALT_OFFSET       0x005C  /* Offset for alternate registers */
 436 #define CONFIG_SYS_ATA_STRIDE          4        /* Interval between registers   */
 437
 438 #define CONFIG_ATAPI            1
 439
 440 #define CONFIG_SYS_BRIGHTNESS          0xFF     /* LCD Default Brightness (255 = off) */
 441
 442 #endif /* __CONFIG_H */