include/configs/inka4x0.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  33 #define CONFIG_MPC5200          1       /* (more precisely an MPC5200 CPU)      */
  34 #define CONFIG_INKA4X0          1       /* INKA4x0 board                        */
  35
  36 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33.000000MHz         */
  37
  38 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
  39 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
  40
  41 #define CONFIG_MISC_INIT_F      1       /* Use misc_init_f()                    */
  42
  43 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs                     */
  44 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  45 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
  46 #endif
  47
  48 /*
  49  * Serial console configuration
  50  */
  51 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  52 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps    */
  53 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  54
  55 /*
  56  * PCI Mapping:
  57  * 0x40000000 - 0x4fffffff - PCI Memory
  58  * 0x50000000 - 0x50ffffff - PCI IO Space
  59  */
  60 #define CONFIG_PCI              1
  61 #define CONFIG_PCI_PNP          1
  62 #define CONFIG_PCI_SCAN_SHOW    1
  63
  64 #define CONFIG_PCI_MEM_BUS      0x40000000
  65 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  66 #define CONFIG_PCI_MEM_SIZE     0x10000000
  67
  68 #define CONFIG_PCI_IO_BUS       0x50000000
  69 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  70 #define CONFIG_PCI_IO_SIZE      0x01000000
  71
  72 #define CFG_XLB_PIPELINING      1
  73
  74 /* Partitions */
  75 #define CONFIG_MAC_PARTITION
  76 #define CONFIG_DOS_PARTITION
  77 #define CONFIG_ISO_PARTITION
  78
  79 /*
  80  * Supported commands
  81  */
  82 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
  83                                 CFG_CMD_DHCP    | \
  84                                 CFG_CMD_EXT2    | \
  85                                 CFG_CMD_FAT     | \
  86                                 CFG_CMD_IDE     | \
  87                                 CFG_CMD_NFS     | \
  88                                 CFG_CMD_PCI     | \
  89                                 CFG_CMD_SNTP    | \
  90                                 CFG_CMD_USB     )
  91
  92 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  93 #include <cmd_confdefs.h>
  94
  95 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  96
  97 #if (TEXT_BASE == 0xFFE00000)           /* Boot low */
  98 #   define CFG_LOWBOOT          1
  99 #endif
 100
 101 /*
 102  * Autobooting
 103  */
 104 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 105
 106 #define CONFIG_PREBOOT  "echo;" \
 107         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 108         "echo"
 109
 110 #undef  CONFIG_BOOTARGS
 111
 112 #define CONFIG_ETHADDR          00:a0:a4:03:00:00
 113 #define CONFIG_OVERWRITE_ETHADDR_ONCE
 114
 115 #define CONFIG_IPADDR           192.168.100.2
 116 #define CONFIG_SERVERIP         192.168.100.1
 117 #define CONFIG_NETMASK          255.255.255.0
 118 #define HOSTNAME                inka4x0
 119 #define CONFIG_BOOTFILE         /tftpboot/inka4x0/uImage
 120 #define CONFIG_ROOTPATH         /opt/eldk/ppc_6xx
 121
 122 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 123         "netdev=eth0\0"                                                 \
 124         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 125                 "nfsroot=${serverip}:${rootpath}\0"                     \
 126         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 127         "addip=setenv bootargs ${bootargs} "                            \
 128                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 129                 ":${hostname}:${netdev}:off panic=1\0"                  \
 130         "addcons=setenv bootargs ${bootargs} "                          \
 131                 "console=ttyS0,${baudrate}\0"                           \
 132         "flash_nfs=run nfsargs addip addcons;"                          \
 133                 "bootm ${kernel_addr}\0"                                \
 134         "net_nfs=tftp 200000 ${bootfile};"                              \
 135                 "run nfsargs addip addcons;bootm\0"                     \
 136         "enable_disp=mw.l 100000 04000000 1;"                           \
 137                 "cp.l 100000 f0000b20 1;"                               \
 138                 "cp.l 100000 f0000b28 1\0"                              \
 139         "ideargs=setenv bootargs root=/dev/hda1 rw\0"                   \
 140         "ide_boot=ext2load ide 0:1 200000 uImage;"                      \
 141                 "run ideargs addip addcons enable_disp;bootm"           \
 142         "brightness=255\0"                                              \
 143         ""
 144
 145 #define CONFIG_BOOTCOMMAND      "run ide_boot"
 146
 147 /*
 148  * IPB Bus clocking configuration.
 149  */
 150 #define CFG_IPBCLK_EQUALS_XLBCLK                /* define for 133MHz speed */
 151
 152 /*
 153  * Flash configuration
 154  */
 155 #define CFG_FLASH_BASE          0xFFE00000
 156
 157 #define CFG_FLASH_SIZE          0x00200000 /* 2 MByte */
 158 #define CFG_MAX_FLASH_SECT      35      /* max num of sects on one chip */
 159
 160 #define CFG_ENV_ADDR            (CFG_FLASH_BASE + 0x4000) /* second sector */
 161 #define CFG_MAX_FLASH_BANKS     1       /* max num of flash banks
 162                                            (= chip selects) */
 163 #define CFG_FLASH_ERASE_TOUT    240000  /* Flash Erase Timeout (in ms)  */
 164 #define CFG_FLASH_WRITE_TOUT    500     /* Flash Write Timeout (in ms)  */
 165
 166 /*
 167  * Environment settings
 168  */
 169 #define CFG_ENV_IS_IN_FLASH     1
 170 #define CFG_ENV_SIZE            0x2000
 171 #define CFG_ENV_SECT_SIZE       0x2000
 172 #define CONFIG_ENV_OVERWRITE    1
 173
 174 /*
 175  * Memory map
 176  */
 177 #define CFG_MBAR                0xF0000000
 178 #define CFG_SDRAM_BASE          0x00000000
 179 #define CFG_DEFAULT_MBAR        0x80000000
 180
 181 #define CONFIG_MPC5200_DDR
 182
 183 /* Use ON-Chip SRAM until RAM will be available */
 184 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 185 #ifdef CONFIG_POST
 186 /* preserve space for the post_word at end of on-chip SRAM */
 187 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_POST_SIZE
 188 #else
 189 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE
 190 #endif
 191
 192
 193 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 194 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 195 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 196
 197 #define CFG_MONITOR_BASE    TEXT_BASE
 198 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 199 #   define CFG_RAMBOOT          1
 200 #endif
 201
 202 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 203 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 204 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 205
 206 /*
 207  * Ethernet configuration
 208  */
 209 #define CONFIG_MPC5xxx_FEC      1
 210 /*
 211  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 212  */
 213 /* #define CONFIG_FEC_10MBIT 1 */
 214 #define CONFIG_PHY_ADDR         0x00
 215 #define CONFIG_MII
 216
 217 /*
 218  * GPIO configuration
 219  *
 220  * use CS1 as gpio_wkup_6 output
 221  *      Bit 0 (mask: 0x80000000): 0
 222  * use ALT CAN position: Bits 2-3 (mask: 0x30000000):
 223  *      00 -> No Alternatives, I2C1 is used for onboard EEPROM
 224  *      01 -> CAN1 on I2C1, CAN2 on Tmr0/1 do not use on TQM5200 with onboard
 225  *            EEPROM
 226  * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100
 227  * use PSC6_1 and PSC6_3 as GPIO: Bits 9:11 (mask: 0x07000000):
 228  *      011 -> PSC6 could not be used as UART or CODEC. IrDA still possible.
 229  */
 230 #define CFG_GPS_PORT_CONFIG     0x01001004
 231
 232 /*
 233  * RTC configuration
 234  */
 235 #define CONFIG_RTC_MPC5200      1       /* use internal MPC5200 RTC */
 236
 237 /*
 238  * Miscellaneous configurable options
 239  */
 240 #define CFG_LONGHELP                    /* undef to save memory     */
 241 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 242 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 243 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 244 #else
 245 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 246 #endif
 247 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 248 #define CFG_MAXARGS             16      /* max number of command args   */
 249 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 250
 251 /* Enable an alternate, more extensive memory test */
 252 #define CFG_ALT_MEMTEST
 253
 254 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 255 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 256
 257 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 258
 259 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 260
 261 /*
 262  * Enable loopw commando. This has only affect, if CFG_CMD_MEM is defined,
 263  * which is normally part of the default commands (CFV_CMD_DFL)
 264  */
 265 #define CONFIG_LOOPW
 266
 267 /*
 268  * Various low-level settings
 269  */
 270 #if defined(CONFIG_MPC5200)
 271 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 272 #define CFG_HID0_FINAL          HID0_ICE
 273 #else
 274 #define CFG_HID0_INIT           0
 275 #define CFG_HID0_FINAL          0
 276 #endif
 277
 278 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 279 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 280 #define CFG_BOOTCS_CFG          0x00087800 /* for pci_clk  = 66 MHz */
 281 #define CFG_CS0_START           CFG_FLASH_BASE
 282 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 283
 284 /* 32Mbit SRAM @0x30000000 */
 285 #define CFG_CS1_START           0x30000000
 286 #define CFG_CS1_SIZE            0x00400000
 287 #define CFG_CS1_CFG             0x31800 /* for pci_clk = 33 MHz */
 288
 289 /* 2 quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 290 #define CFG_CS2_START           0x80000000
 291 #define CFG_CS2_SIZE            0x0001000
 292 #define CFG_CS2_CFG             0x21800  /* for pci_clk = 33 MHz */
 293
 294 /* GPIO in @0x30400000 */
 295 #define CFG_CS3_START           0x30400000
 296 #define CFG_CS3_SIZE            0x00100000
 297 #define CFG_CS3_CFG             0x31800 /* for pci_clk = 33 MHz */
 298
 299 #define CFG_CS_BURST            0x00000000
 300 #define CFG_CS_DEADCYCLE        0x33333333
 301
 302 /*-----------------------------------------------------------------------
 303  * USB stuff
 304  *-----------------------------------------------------------------------
 305  */
 306 #define CONFIG_USB_OHCI
 307 #define CONFIG_USB_CLOCK        0x00015555
 308 #define CONFIG_USB_CONFIG       0x00001000
 309 #define CONFIG_USB_STORAGE
 310
 311 /*-----------------------------------------------------------------------
 312  * IDE/ATA stuff Supports IDE harddisk
 313  *-----------------------------------------------------------------------
 314  */
 315
 316 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 317
 318 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 319 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 320
 321 #define CONFIG_IDE_RESET                /* reset for ide supported      */
 322 #define CONFIG_IDE_PREINIT
 323
 324 #define CFG_IDE_MAXBUS          1       /* max. 1 IDE bus               */
 325 #define CFG_IDE_MAXDEVICE       2       /* max. 1 drive per IDE bus     */
 326
 327 #define CFG_ATA_IDE0_OFFSET     0x0000
 328 #define CFG_ATA_BASE_ADDR       MPC5XXX_ATA
 329 #define CFG_ATA_DATA_OFFSET     0x0060  /* Offset for data I/O          */
 330 #define CFG_ATA_REG_OFFSET (CFG_ATA_DATA_OFFSET) /* Offset for normal register accesses */
 331 #define CFG_ATA_ALT_OFFSET      0x005C  /* Offset for alternate registers */
 332 #define CFG_ATA_STRIDE          4       /* Interval between registers   */
 333
 334 #define CONFIG_ATAPI            1
 335
 336 #define CFG_BRIGHTNESS          0xFF    /* LCD Default Brightness (255 = off) */
 337
 338 #endif /* __CONFIG_H */