include/configs/io64.h

   1 /*
   2  * (C) Copyright 2011
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * based on kilauea.h
   6  * by Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  * and Grant Erickson <gerickson@nuovations.com>
   8  *
   9  * See file CREDITS for list of people who contributed to this
  10  * project.
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 /************************************************************************
  29  * io64.h - configuration for Guntermann & Drunck Io64 (405EX)
  30  ***********************************************************************/
  31
  32 #ifndef __CONFIG_H
  33 #define __CONFIG_H
  34
  35 /*-----------------------------------------------------------------------
  36  * High Level Configuration Options
  37  *----------------------------------------------------------------------*/
  38 #define CONFIG_IO64             1               /* Board is Io64 */
  39 #define CONFIG_4xx              1               /* ... PPC4xx family */
  40 #define CONFIG_405EX            1               /* Specifc 405EX support*/
  41 #define CONFIG_SYS_CLK_FREQ     33333333        /* ext frequency to pll */
  42
  43 #ifndef CONFIG_SYS_TEXT_BASE
  44 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  45 #endif
  46
  47 /*
  48  * CHIP_21 errata
  49  */
  50 #define CONFIG_SYS_4xx_CHIP_21_405EX_SECURITY
  51
  52 /*
  53  * Include common defines/options for all AMCC eval boards
  54  */
  55 #define CONFIG_HOSTNAME         io64
  56 #define CONFIG_IDENT_STRING     " io64 0.01"
  57 #include "amcc-common.h"
  58
  59 #define CONFIG_BOARD_EARLY_INIT_F
  60 #define CONFIG_BOARD_EARLY_INIT_R
  61 #define CONFIG_MISC_INIT_R
  62 #define CONFIG_LAST_STAGE_INIT
  63
  64 #undef CONFIG_ZERO_BOOTDELAY_CHECK      /* ignore keypress on bootdelay==0 */
  65 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot */
  66 #define CONFIG_AUTOBOOT_STOP_STR " "
  67
  68 /* new uImage format support */
  69 #define CONFIG_FIT
  70 #define CONFIG_FIT_VERBOSE
  71
  72 /*-----------------------------------------------------------------------
  73  * Base addresses -- Note these are effective addresses where the
  74  * actual resources get mapped (not physical addresses)
  75  *----------------------------------------------------------------------*/
  76 #define CONFIG_SYS_FLASH_BASE           0xFC000000
  77 #define CONFIG_SYS_NVRAM_BASE           0xF0000000
  78 #define CONFIG_SYS_FPGA0_BASE           0xF0100000
  79 #define CONFIG_SYS_FPGA1_BASE           0xF0108000
  80 #define CONFIG_SYS_LATCH_BASE           0xF0200000
  81
  82 /*-----------------------------------------------------------------------
  83  * Initial RAM & Stack Pointer Configuration Options
  84  *
  85  *   There are traditionally three options for the primordial
  86  *   (i.e. initial) stack usage on the 405-series:
  87  *
  88  *      1) On-chip Memory (OCM) (i.e. SRAM)
  89  *      2) Data cache
  90  *      3) SDRAM
  91  *
  92  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  93  *   the latter of which is less than desireable since it requires
  94  *   setting up the SDRAM and ECC in assembly code.
  95  *
  96  *   To use (2), define 'CONFIG_SYS_INIT_DCACHE_CS' to be an unused chip
  97  *   select on the External Bus Controller (EBC) and then select a
  98  *   value for 'CONFIG_SYS_INIT_RAM_ADDR' outside of the range of valid,
  99  *   physical SDRAM. Otherwise, undefine 'CONFIG_SYS_INIT_DCACHE_CS' and
 100  *   select a value for 'CONFIG_SYS_INIT_RAM_ADDR' within the range of valid,
 101  *   physical SDRAM to use (3).
 102  *-----------------------------------------------------------------------*/
 103
 104 #define CONFIG_SYS_INIT_DCACHE_CS       4
 105
 106 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
 107 #define CONFIG_SYS_INIT_RAM_ADDR \
 108         (CONFIG_SYS_SDRAM_BASE + (1 << 30))     /*  1 GiB */
 109 #else
 110 #define CONFIG_SYS_INIT_RAM_ADDR \
 111         (CONFIG_SYS_SDRAM_BASE + (32 << 20))    /* 32 MiB */
 112 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 113
 114 #define CONFIG_SYS_INIT_RAM_SIZE \
 115         (4 << 10)                               /*  4 KiB */
 116 #define CONFIG_SYS_GBL_DATA_OFFSET \
 117         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 118
 119 /*
 120  * If the data cache is being used for the primordial stack and global
 121  * data area, the POST word must be placed somewhere else. The General
 122  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
 123  * its compare and mask register contents across reset, so it is used
 124  * for the POST word.
 125  */
 126
 127 #if defined(CONFIG_SYS_INIT_DCACHE_CS)
 128 # define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET
 129 # define CONFIG_SYS_POST_WORD_ADDR \
 130         (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
 131 #else
 132 # define CONFIG_SYS_INIT_EXTRA_SIZE     16
 133 # define CONFIG_SYS_INIT_SP_OFFSET \
 134         (CONFIG_SYS_GBL_DATA_OFFSET - CONFIG_SYS_INIT_EXTRA_SIZE)
 135 # define CONFIG_SYS_OCM_DATA_ADDR       CONFIG_SYS_INIT_RAM_ADDR
 136 #endif /* defined(CONFIG_SYS_INIT_DCACHE_CS) */
 137
 138 /*-----------------------------------------------------------------------
 139  * Serial Port
 140  *----------------------------------------------------------------------*/
 141 #define CONFIG_CONS_INDEX       1       /* Use UART0 */
 142 #define CONFIG_SYS_BASE_BAUD    691200
 143
 144 /*-----------------------------------------------------------------------
 145  * Environment
 146  *----------------------------------------------------------------------*/
 147 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars */
 148
 149 /*-----------------------------------------------------------------------
 150  * FLASH related
 151  *----------------------------------------------------------------------*/
 152 #define CONFIG_SYS_FLASH_CFI            /* The flash is CFI compatible */
 153 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver */
 154
 155 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 156 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 157 #define CONFIG_SYS_MAX_FLASH_SECT       512
 158
 159 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000
 160 #define CONFIG_SYS_FLASH_WRITE_TOUT     500
 161
 162 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 163 #define CONFIG_SYS_FLASH_EMPTY_INFO
 164
 165 #ifdef CONFIG_ENV_IS_IN_FLASH
 166 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector */
 167 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 168 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector */
 169
 170 /* Address and size of Redundant Environment Sector */
 171 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 172 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 173 #endif /* CONFIG_ENV_IS_IN_FLASH */
 174
 175 /* Gbit PHYs */
 176 #define CONFIG_BITBANGMII               /* bit-bang MII PHY management */
 177 #define CONFIG_BITBANGMII_MULTI
 178
 179 #define CONFIG_SYS_MDIO_PIN  (0x80000000 >> 12) /* MDIO is GPIO12 */
 180 #define CONFIG_SYS_MDC_PIN   (0x80000000 >> 13) /* MDC  is GPIO13 */
 181
 182 #define CONFIG_SYS_GBIT_MII_BUSNAME     "io_miiphy0"
 183
 184 #define CONFIG_SYS_MDIO1_PIN  (0x80000000 >> 2) /* MDIO is GPIO2 */
 185 #define CONFIG_SYS_MDC1_PIN   (0x80000000 >> 3) /* MDC  is GPIO3 */
 186
 187 #define CONFIG_SYS_GBIT_MII1_BUSNAME    "io_miiphy1"
 188
 189 /*-----------------------------------------------------------------------
 190  * DDR SDRAM
 191  *----------------------------------------------------------------------*/
 192 #define CONFIG_SYS_MBYTES_SDRAM        (128)    /* 128MB */
 193
 194 /*
 195  * CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 196  *
 197  * Note: DDR Autocalibration Method_A scans the full range of possible PPC4xx
 198  *       SDRAM Controller DDR autocalibration values and takes a lot longer
 199  *       to run than Method_B.
 200  * (See the Method_A and Method_B algorithm discription in the file:
 201  *      arch/powerpc/cpu/ppc4xx/4xx_ibm_ddr2_autocalib.c)
 202  * Define CONFIG_PPC4xx_DDR_METHOD_A to use DDR autocalibration Method_A
 203  *
 204  * DDR Autocalibration Method_B is the default.
 205  */
 206 #define CONFIG_PPC4xx_DDR_AUTOCALIBRATION
 207 #define DEBUG_PPC4xx_DDR_AUTOCALIBRATION
 208 #undef  CONFIG_PPC4xx_DDR_METHOD_A
 209
 210 #define CONFIG_SYS_SDRAM0_MB0CF_BASE    ((0 << 20) + CONFIG_SYS_SDRAM_BASE)
 211
 212 /* DDR1/2 SDRAM Device Control Register Data Values */
 213 #define CONFIG_SYS_SDRAM0_MB0CF ((CONFIG_SYS_SDRAM0_MB0CF_BASE >> 3) | \
 214                                  SDRAM_RXBAS_SDSZ_128MB | \
 215                                  SDRAM_RXBAS_SDAM_MODE2 | \
 216                                  SDRAM_RXBAS_SDBE_ENABLE)
 217 #define CONFIG_SYS_SDRAM0_MB1CF SDRAM_RXBAS_SDBE_DISABLE
 218 #define CONFIG_SYS_SDRAM0_MB2CF SDRAM_RXBAS_SDBE_DISABLE
 219 #define CONFIG_SYS_SDRAM0_MB3CF SDRAM_RXBAS_SDBE_DISABLE
 220 #define CONFIG_SYS_SDRAM0_MCOPT1        (SDRAM_MCOPT1_PMU_OPEN | \
 221                                  SDRAM_MCOPT1_4_BANKS | \
 222                                  SDRAM_MCOPT1_DDR2_TYPE | \
 223                                  SDRAM_MCOPT1_QDEP | \
 224                                  SDRAM_MCOPT1_DCOO_DISABLED)
 225 #define CONFIG_SYS_SDRAM0_MCOPT2        0x00000000
 226 #define CONFIG_SYS_SDRAM0_MODT0 (SDRAM_MODT_EB0W_ENABLE | \
 227                                  SDRAM_MODT_EB0R_ENABLE)
 228 #define CONFIG_SYS_SDRAM0_MODT1 0x00000000
 229 #define CONFIG_SYS_SDRAM0_CODT          (SDRAM_CODT_RK0R_ON | \
 230                                  SDRAM_CODT_CKLZ_36OHM | \
 231                                  SDRAM_CODT_DQS_1_8_V_DDR2 | \
 232                                  SDRAM_CODT_IO_NMODE)
 233 #define CONFIG_SYS_SDRAM0_RTR           SDRAM_RTR_RINT_ENCODE(1560)
 234 #define CONFIG_SYS_SDRAM0_INITPLR0      (SDRAM_INITPLR_ENABLE | \
 235                 SDRAM_INITPLR_IMWT_ENCODE(80) | \
 236                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_NOP))
 237 #define CONFIG_SYS_SDRAM0_INITPLR1      (SDRAM_INITPLR_ENABLE | \
 238                 SDRAM_INITPLR_IMWT_ENCODE(3) | \
 239                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
 240                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
 241                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 242 #define CONFIG_SYS_SDRAM0_INITPLR2      (SDRAM_INITPLR_ENABLE | \
 243                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 244                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 245                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR2) | \
 246                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR2_TEMP_COMMERCIAL))
 247 #define CONFIG_SYS_SDRAM0_INITPLR3      (SDRAM_INITPLR_ENABLE | \
 248                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 249                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 250                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR3) | \
 251                 SDRAM_INITPLR_IMA_ENCODE(0))
 252 #define CONFIG_SYS_SDRAM0_INITPLR4      (SDRAM_INITPLR_ENABLE | \
 253                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 254                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 255                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
 256                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_DQS_DISABLE | \
 257                                          JEDEC_MA_EMR_RTT_75OHM))
 258 #define CONFIG_SYS_SDRAM0_INITPLR5      (SDRAM_INITPLR_ENABLE | \
 259                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 260                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 261                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
 262                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 263                                          JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
 264                                          JEDEC_MA_MR_BLEN_4 | \
 265                                          JEDEC_MA_MR_DLL_RESET))
 266 #define CONFIG_SYS_SDRAM0_INITPLR6      (SDRAM_INITPLR_ENABLE | \
 267                 SDRAM_INITPLR_IMWT_ENCODE(3) | \
 268                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_PRECHARGE) | \
 269                 SDRAM_INITPLR_IBA_ENCODE(0x0) | \
 270                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_PRECHARGE_ALL))
 271 #define CONFIG_SYS_SDRAM0_INITPLR7      (SDRAM_INITPLR_ENABLE | \
 272                 SDRAM_INITPLR_IMWT_ENCODE(26) | \
 273                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 274 #define CONFIG_SYS_SDRAM0_INITPLR8      (SDRAM_INITPLR_ENABLE | \
 275                 SDRAM_INITPLR_IMWT_ENCODE(26) | \
 276                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 277 #define CONFIG_SYS_SDRAM0_INITPLR9      (SDRAM_INITPLR_ENABLE | \
 278                 SDRAM_INITPLR_IMWT_ENCODE(26) | \
 279                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 280 #define CONFIG_SYS_SDRAM0_INITPLR10     (SDRAM_INITPLR_ENABLE | \
 281                 SDRAM_INITPLR_IMWT_ENCODE(26) | \
 282                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_REFRESH))
 283 #define CONFIG_SYS_SDRAM0_INITPLR11     (SDRAM_INITPLR_ENABLE | \
 284                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 285                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 286                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_MR) | \
 287                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_MR_WR_DDR2_3_CYC | \
 288                                          JEDEC_MA_MR_CL_DDR2_5_0_CLK | \
 289                                          JEDEC_MA_MR_BLEN_4))
 290 #define CONFIG_SYS_SDRAM0_INITPLR12     (SDRAM_INITPLR_ENABLE | \
 291                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 292                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 293                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
 294                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_ENTER | \
 295                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 296                                          JEDEC_MA_EMR_DQS_DISABLE | \
 297                                          JEDEC_MA_EMR_RTT_DISABLED | \
 298                                          JEDEC_MA_EMR_ODS_NORMAL))
 299 #define CONFIG_SYS_SDRAM0_INITPLR13     (SDRAM_INITPLR_ENABLE | \
 300                 SDRAM_INITPLR_IMWT_ENCODE(2) | \
 301                 SDRAM_INITPLR_ICMD_ENCODE(JEDEC_CMD_EMR) | \
 302                 SDRAM_INITPLR_IBA_ENCODE(JEDEC_BA_EMR) | \
 303                 SDRAM_INITPLR_IMA_ENCODE(JEDEC_MA_EMR_OCD_EXIT | \
 304                                          JEDEC_MA_EMR_RDQS_DISABLE | \
 305                                          JEDEC_MA_EMR_DQS_DISABLE | \
 306                                          JEDEC_MA_EMR_RTT_DISABLED | \
 307                                          JEDEC_MA_EMR_ODS_NORMAL))
 308 #define CONFIG_SYS_SDRAM0_INITPLR14     (SDRAM_INITPLR_DISABLE)
 309 #define CONFIG_SYS_SDRAM0_INITPLR15     (SDRAM_INITPLR_DISABLE)
 310 #define CONFIG_SYS_SDRAM0_RQDC          (SDRAM_RQDC_RQDE_ENABLE | \
 311                                  SDRAM_RQDC_RQFD_ENCODE(56))
 312 #define CONFIG_SYS_SDRAM0_RFDC          SDRAM_RFDC_RFFD_ENCODE(521)
 313 #define CONFIG_SYS_SDRAM0_RDCC          (SDRAM_RDCC_RDSS_T2)
 314 #define CONFIG_SYS_SDRAM0_DLCR          (SDRAM_DLCR_DCLM_AUTO | \
 315                                  SDRAM_DLCR_DLCS_CONT_DONE | \
 316                                  SDRAM_DLCR_DLCV_ENCODE(165))
 317 #define CONFIG_SYS_SDRAM0_CLKTR (SDRAM_CLKTR_CLKP_180_DEG_ADV)
 318 #define CONFIG_SYS_SDRAM0_WRDTR 0x00000000
 319 #define CONFIG_SYS_SDRAM0_SDTR1 (SDRAM_SDTR1_LDOF_2_CLK | \
 320                                  SDRAM_SDTR1_RTW_2_CLK | \
 321                                  SDRAM_SDTR1_WTWO_1_CLK | \
 322                                  SDRAM_SDTR1_RTRO_1_CLK)
 323 #define CONFIG_SYS_SDRAM0_SDTR2 (SDRAM_SDTR2_RCD_3_CLK | \
 324                                  SDRAM_SDTR2_WTR_2_CLK | \
 325                                  SDRAM_SDTR2_XSNR_32_CLK | \
 326                                  SDRAM_SDTR2_WPC_4_CLK | \
 327                                  SDRAM_SDTR2_RPC_2_CLK | \
 328                                  SDRAM_SDTR2_RP_3_CLK | \
 329                                  SDRAM_SDTR2_RRD_2_CLK)
 330 #define CONFIG_SYS_SDRAM0_SDTR3 (SDRAM_SDTR3_RAS_ENCODE(9) | \
 331                                  SDRAM_SDTR3_RC_ENCODE(12) | \
 332                                  SDRAM_SDTR3_XCS | \
 333                                  SDRAM_SDTR3_RFC_ENCODE(21))
 334 #define CONFIG_SYS_SDRAM0_MMODE (SDRAM_MMODE_WR_DDR2_3_CYC | \
 335                                  SDRAM_MMODE_DCL_DDR2_5_0_CLK | \
 336                                  SDRAM_MMODE_BLEN_4)
 337 #define CONFIG_SYS_SDRAM0_MEMODE        (SDRAM_MEMODE_DQS_DISABLE | \
 338                                  SDRAM_MEMODE_RTT_75OHM)
 339
 340 /*-----------------------------------------------------------------------
 341  * I2C
 342  *----------------------------------------------------------------------*/
 343 #define CONFIG_SYS_I2C_SPEED    400000  /* I2C speed and slave address */
 344
 345 #define CONFIG_PCA9698          1       /* NXP PCA9698 */
 346
 347 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* I2C boot EEPROM (24C02BN) */
 348 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1       /* Bytes of address */
 349 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 350 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 351
 352 /* I2C bootstrap EEPROM */
 353 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x54
 354 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 355 #define CONFIG_4xx_CONFIG_BLOCKSIZE             16
 356
 357 /* Temp sensor/hwmon/dtt */
 358 #define CONFIG_DTT_LM63         1       /* National LM63 */
 359 #define CONFIG_DTT_SENSORS      { 0x18, 0x4c, 0x4e }    /* Sensor addresses */
 360 #define CONFIG_DTT_PWM_LOOKUPTABLE      \
 361                 { { 40, 10 }, { 43, 13 }, { 46, 16 },  \
 362                   { 50, 20 }, { 53, 27 }, { 56, 34 }, { 60, 40 } }
 363 #define CONFIG_DTT_TACH_LIMIT   0xa10
 364
 365 /*-----------------------------------------------------------------------
 366  * Ethernet
 367  *----------------------------------------------------------------------*/
 368 #define CONFIG_M88E1111_PHY     1
 369 #define CONFIG_IBM_EMAC4_V4     1
 370 #define CONFIG_EMAC_PHY_MODE    EMAC_PHY_MODE_RGMII_RGMII
 371 #define CONFIG_PHY_ADDR         0x12    /* PHY address, See schematics */
 372
 373 #define CONFIG_PHY_RESET        1       /* reset phy upon startup */
 374 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 375
 376 #define CONFIG_HAS_ETH0         1
 377
 378 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 379 #define CONFIG_PHY1_ADDR        0x13
 380
 381 /* Debug messages for the DDR autocalibration */
 382 #define CONFIG_AUTOCALIB                "silent\0"
 383
 384 /*
 385  * Default environment variables
 386  */
 387 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 388         CONFIG_AMCC_DEF_ENV                                             \
 389         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 390         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 391         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 392         "logversion=2\0"                                                \
 393         "kernel_addr=fc000000\0"                                        \
 394         "fdt_addr=fc1e0000\0"                                           \
 395         "ramdisk_addr=fc200000\0"                                       \
 396         "pciconfighost=1\0"                                             \
 397         "pcie_mode=RP:RP\0"                                             \
 398         ""
 399
 400 /*
 401  * Commands additional to the ones defined in amcc-common.h
 402  */
 403 #define CONFIG_CMD_CHIP_CONFIG
 404 #define CONFIG_CMD_DTT
 405
 406 #define CONFIG_SYS_POST_MEMORY_ON       CONFIG_SYS_POST_MEMORY
 407
 408 /* POST support */
 409 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE          | \
 410                                  CONFIG_SYS_POST_CPU            | \
 411                                  CONFIG_SYS_POST_ETHER          | \
 412                                  CONFIG_SYS_POST_I2C            | \
 413                                  CONFIG_SYS_POST_MEMORY_ON      | \
 414                                  CONFIG_SYS_POST_UART)
 415
 416 /* Define here the base-addresses of the UARTs to test in POST */
 417 #define CONFIG_SYS_POST_UART_TABLE      { CONFIG_SYS_NS16550_COM1, \
 418                         CONFIG_SYS_NS16550_COM2 }
 419
 420 #define CONFIG_LOGBUFFER
 421 #define CONFIG_SYS_POST_CACHE_ADDR      0x00800000 /* free virtual address */
 422
 423 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 424
 425 /*-----------------------------------------------------------------------
 426  * External Bus Controller (EBC) Setup
 427  *----------------------------------------------------------------------*/
 428
 429 /* Memory Bank 0 (NOR-flash) */
 430 #define CONFIG_SYS_EBC_PB0AP    (EBC_BXAP_BME_DISABLED          |       \
 431                                  EBC_BXAP_TWT_ENCODE(11)        |       \
 432                                  EBC_BXAP_BCE_DISABLE           |       \
 433                                  EBC_BXAP_BCT_2TRANS            |       \
 434                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 435                                  EBC_BXAP_OEN_ENCODE(0)         |       \
 436                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 437                                  EBC_BXAP_WBF_ENCODE(2)         |       \
 438                                  EBC_BXAP_TH_ENCODE(2)          |       \
 439                                  EBC_BXAP_RE_DISABLED           |       \
 440                                  EBC_BXAP_SOR_NONDELAYED        |       \
 441                                  EBC_BXAP_BEM_WRITEONLY         |       \
 442                                  EBC_BXAP_PEN_DISABLED)
 443 #define CONFIG_SYS_EBC_PB0CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) | \
 444                                  EBC_BXCR_BS_64MB               |       \
 445                                  EBC_BXCR_BU_RW                 |       \
 446                                  EBC_BXCR_BW_16BIT)
 447
 448 /* Memory Bank 1 (NVRAM/Uart) */
 449 #define CONFIG_SYS_EBC_PB1AP    (EBC_BXAP_BME_ENABLED           |       \
 450                                  EBC_BXAP_FWT_ENCODE(8)         |       \
 451                                  EBC_BXAP_BWT_ENCODE(4)         |       \
 452                                  EBC_BXAP_BCE_DISABLE           |       \
 453                                  EBC_BXAP_BCT_2TRANS            |       \
 454                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 455                                  EBC_BXAP_OEN_ENCODE(1)         |       \
 456                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 457                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 458                                  EBC_BXAP_TH_ENCODE(2)          |       \
 459                                  EBC_BXAP_RE_DISABLED           |       \
 460                                  EBC_BXAP_SOR_NONDELAYED        |       \
 461                                  EBC_BXAP_BEM_WRITEONLY         |       \
 462                                  EBC_BXAP_PEN_DISABLED)
 463 #define CONFIG_SYS_EBC_PB1CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_NVRAM_BASE) | \
 464                                  EBC_BXCR_BS_1MB                |       \
 465                                  EBC_BXCR_BU_RW                 |       \
 466                                  EBC_BXCR_BW_8BIT)
 467
 468 /* Memory Bank 2 (FPGA) */
 469 #define CONFIG_SYS_EBC_PB2AP    (EBC_BXAP_BME_DISABLED          |       \
 470                                  EBC_BXAP_TWT_ENCODE(5)         |       \
 471                                  EBC_BXAP_BCE_DISABLE           |       \
 472                                  EBC_BXAP_BCT_2TRANS            |       \
 473                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 474                                  EBC_BXAP_OEN_ENCODE(2)         |       \
 475                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 476                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 477                                  EBC_BXAP_TH_ENCODE(0)          |       \
 478                                  EBC_BXAP_RE_DISABLED           |       \
 479                                  EBC_BXAP_SOR_NONDELAYED        |       \
 480                                  EBC_BXAP_BEM_WRITEONLY         |       \
 481                                  EBC_BXAP_PEN_DISABLED)
 482 #define CONFIG_SYS_EBC_PB2CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FPGA0_BASE) | \
 483                                  EBC_BXCR_BS_1MB                |       \
 484                                  EBC_BXCR_BU_RW                 |       \
 485                                  EBC_BXCR_BW_16BIT)
 486
 487 /* Memory Bank 3 (Latches) */
 488 #define CONFIG_SYS_EBC_PB3AP    (EBC_BXAP_BME_ENABLED           |       \
 489                                  EBC_BXAP_FWT_ENCODE(8)         |       \
 490                                  EBC_BXAP_BWT_ENCODE(4)         |       \
 491                                  EBC_BXAP_BCE_DISABLE           |       \
 492                                  EBC_BXAP_BCT_2TRANS            |       \
 493                                  EBC_BXAP_CSN_ENCODE(0)         |       \
 494                                  EBC_BXAP_OEN_ENCODE(1)         |       \
 495                                  EBC_BXAP_WBN_ENCODE(1)         |       \
 496                                  EBC_BXAP_WBF_ENCODE(1)         |       \
 497                                  EBC_BXAP_TH_ENCODE(2)          |       \
 498                                  EBC_BXAP_RE_DISABLED           |       \
 499                                  EBC_BXAP_SOR_NONDELAYED        |       \
 500                                  EBC_BXAP_BEM_WRITEONLY         |       \
 501                                  EBC_BXAP_PEN_DISABLED)
 502 #define CONFIG_SYS_EBC_PB3CR    (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_LATCH_BASE) | \
 503                                  EBC_BXCR_BS_1MB                |       \
 504                                  EBC_BXCR_BU_RW                 |       \
 505                                  EBC_BXCR_BW_16BIT)
 506
 507 /* EBC peripherals */
 508
 509 #define CONFIG_SYS_FPGA_BASE(k) \
 510         (k ? CONFIG_SYS_FPGA1_BASE : CONFIG_SYS_FPGA0_BASE)
 511
 512 #define CONFIG_SYS_FPGA_DONE(k) \
 513         (k ? 0x0040 : 0x0080)
 514
 515 #define CONFIG_SYS_FPGA_COUNT           2
 516
 517 #define CONFIG_SYS_LATCH0_RESET         0xffff
 518 #define CONFIG_SYS_LATCH0_BOOT          0xffff
 519 #define CONFIG_SYS_LATCH1_RESET         0xffbf
 520 #define CONFIG_SYS_LATCH1_BOOT          0xffff
 521
 522 /*-----------------------------------------------------------------------
 523  * GPIO Setup
 524  *----------------------------------------------------------------------*/
 525 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out           GPIO */ \
 526 { \
 527 /* GPIO Core 0 */ \
 528 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO0 */ \
 529 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO1 */ \
 530 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO2 */ \
 531 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO3 */ \
 532 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO4 */ \
 533 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO5 */ \
 534 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO6 */ \
 535 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO7 */ \
 536 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO8 */ \
 537 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO9 */ \
 538 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO10 */ \
 539 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO11 */ \
 540 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO12 */ \
 541 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_1     }, /* GPIO13 */ \
 542 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO14 */ \
 543 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO15 */ \
 544 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO16 */ \
 545 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO17 */ \
 546 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0     }, /* GPIO18 */ \
 547 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO19 */ \
 548 {GPIO0_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0     }, /* GPIO20 */ \
 549 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO21 */ \
 550 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO22 */ \
 551 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG}, /* GPIO23 */ \
 552 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO24 */ \
 553 {GPIO0_BASE, GPIO_IN,  GPIO_ALT3, GPIO_OUT_0     }, /* GPIO25 */ \
 554 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0     }, /* GPIO26 */ \
 555 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO27 */ \
 556 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO28 */ \
 557 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0     }, /* GPIO29 */ \
 558 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO30 */ \
 559 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0     }, /* GPIO31 */ \
 560 } \
 561 }
 562
 563 #define CONFIG_SYS_GPIO_STARTUP_FINISHED        15
 564 #define CONFIG_SYS_GPIO_STARTUP_FINISHED_N      14
 565
 566 #endif  /* __CONFIG_H */