include/configs/ipek01.h

   1 /*
   2  * (C) Copyright 2006
   3  * MicroSys GmbH
   4  *
   5  * (C) Copyright 2009
   6  * Wolfgang Grandegger, DENX Software Engineering, wg@denx.de.
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Configuration Options
  16  */
  17
  18 #define CONFIG_MPC5200
  19 #define CONFIG_MPX5200          1       /* MPX5200 board */
  20 #define CONFIG_MPC5200_DDR      1       /* use DDR RAM */
  21 #define CONFIG_IPEK01                   /* Motherboard is ipek01 */
  22
  23 #define CONFIG_SYS_TEXT_BASE    0xfc000000
  24
  25 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz */
  26
  27 #define CONFIG_MISC_INIT_R
  28
  29 #define CONFIG_SYS_CACHELINE_SIZE       32 /* For MPC5xxx CPUs */
  30 #ifdef CONFIG_CMD_KGDB
  31 #define CONFIG_SYS_CACHELINE_SHIFT      5  /* log base 2 of the above value */
  32 #endif
  33
  34 /*
  35  * Serial console configuration
  36  */
  37 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1 */
  38 #define CONFIG_BAUDRATE         115200  /* ... at 9600 bps */
  39 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  40
  41 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
  42
  43 /*
  44  * Video configuration for LIME GDC
  45  */
  46 #ifdef CONFIG_VIDEO
  47 #define CONFIG_VIDEO_MB862xx
  48 #define CONFIG_VIDEO_MB862xx_ACCEL
  49 #define VIDEO_FB_16BPP_WORD_SWAP
  50 #define CONFIG_VIDEO_LOGO
  51 #define CONFIG_VIDEO_BMP_LOGO
  52 #define CONFIG_CONSOLE_EXTRA_INFO
  53 #define CONFIG_VGA_AS_SINGLE_DEVICE
  54 #define CONFIG_VIDEO_SW_CURSOR
  55 #define CONFIG_SPLASH_SCREEN
  56 #define CONFIG_VIDEO_BMP_GZIP
  57 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)       /* decompressed img */
  58 /* Lime clock frequency */
  59 #define CONFIG_SYS_MB862xx_CCF  0x90000 /* geo 166MHz other 133MHz */
  60 /* SDRAM parameter */
  61 #define CONFIG_SYS_MB862xx_MMR  0x41c767e3
  62 #endif
  63
  64 /*
  65  * PCI Mapping:
  66  * 0x40000000 - 0x4fffffff - PCI Memory
  67  * 0x50000000 - 0x50ffffff - PCI IO Space
  68  */
  69 #define CONFIG_PCI              1
  70 #define CONFIG_PCI_PNP          1
  71 #define CONFIG_PCI_SCAN_SHOW    1
  72
  73 #define CONFIG_PCI_MEM_BUS      0x40000000
  74 #define CONFIG_PCI_MEM_PHYS     CONFIG_PCI_MEM_BUS
  75 #define CONFIG_PCI_MEM_SIZE     0x10000000
  76
  77 #define CONFIG_PCI_IO_BUS       0x50000000
  78 #define CONFIG_PCI_IO_PHYS      CONFIG_PCI_IO_BUS
  79 #define CONFIG_PCI_IO_SIZE      0x01000000
  80
  81 #define CONFIG_MII              1
  82 #define CONFIG_EEPRO100         1
  83 #define CONFIG_SYS_RX_ETH_BUFFER        8  /* use 8 rx buffer on eepro100  */
  84
  85 /* Partitions */
  86 #define CONFIG_DOS_PARTITION
  87
  88 /* USB */
  89 #define CONFIG_USB_OHCI_NEW
  90 #define CONFIG_SYS_OHCI_BE_CONTROLLER
  91
  92 #define CONFIG_SYS_USB_OHCI_CPU_INIT
  93 #define CONFIG_SYS_USB_OHCI_REGS_BASE           MPC5XXX_USB
  94 #define CONFIG_SYS_USB_OHCI_SLOT_NAME           "mpc5200"
  95 #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS      15
  96
  97 /*
  98  * Command line configuration.
  99  */
 100 #ifdef CONFIG_VIDEO
 101 #define CONFIG_CMD_BMP          /* BMP support */
 102 #endif
 103 #define CONFIG_CMD_DATE         /* support for RTC, date/time...*/
 104 #define CONFIG_CMD_IDE          /* IDE harddisk support */
 105 #define CONFIG_CMD_IRQ          /* irqinfo */
 106 #define CONFIG_CMD_PCI          /* pciinfo */
 107
 108 #define CONFIG_SYS_LOWBOOT      1
 109
 110 /*
 111  * Autobooting
 112  */
 113
 114 #define CONFIG_PREBOOT  "echo;" \
 115         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 116         "echo"
 117
 118 #undef  CONFIG_BOOTARGS
 119
 120 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 121         "netdev=eth0\0"                                                 \
 122         "consoledev=ttyPSC0\0"                                          \
 123         "hostname=ipek01\0"                                             \
 124         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 125                 "nfsroot=${serverip}:${rootpath}\0"                     \
 126         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 127         "addip=setenv bootargs ${bootargs} "                            \
 128                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 129                 ":${hostname}:${netdev}:off panic=1\0"                  \
 130         "addtty=setenv bootargs ${bootargs} "                           \
 131                 "console=${consoledev},${baudrate}\0"                   \
 132         "flash_nfs=run nfsargs addip addtty;"                           \
 133                 "bootm ${kernel_addr} - ${fdtaddr}\0"                   \
 134         "flash_self=run ramargs addip addtty;"                          \
 135                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdtaddr}\0"     \
 136         "net_nfs=tftp 200000 ${bootfile}; tftp ${fdtaddr} ${fdtfile};"  \
 137                 "run nfsargs addip addtty;"                             \
 138                  "bootm ${loadaddr} - ${fdtaddr}\0"                     \
 139         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 140         "bootfile=ipek01/uImage\0"                                      \
 141         "load=tftp 100000 ipek01/u-boot.bin\0"                          \
 142         "update=protect off FC000000 +60000; era FC000000 +60000; "     \
 143                 "cp.b 100000 FC000000 ${filesize}\0"                    \
 144         "upd=run load;run update\0"                                     \
 145         "fdtaddr=800000\0"                                              \
 146         "loadaddr=400000\0"                                             \
 147         "fdtfile=ipek01/ipek01.dtb\0"                                   \
 148         ""
 149
 150 #define CONFIG_BOOTCOMMAND      "run flash_self"
 151
 152 /*
 153  * IPB Bus clocking configuration.
 154  */
 155 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* for 133MHz */
 156 /* PCI clock must be 33, because board will not boot */
 157 #undef CONFIG_SYS_PCICLK_EQUALS_IPBCLK_DIV2     /* for 66MHz */
 158
 159 /*
 160  * Open firmware flat tree support
 161  */
 162 #define OF_CPU                  "PowerPC,5200@0"
 163 #define OF_SOC                  "soc5200@f0000000"
 164 #define OF_TBCLK                (bd->bi_busfreq / 4)
 165
 166 /*
 167  * I2C configuration
 168  */
 169 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 170 #define CONFIG_SYS_I2C_MODULE   2       /* Select I2C module #1 or #2 */
 171
 172 #define CONFIG_SYS_I2C_SPEED    100000  /* 100 kHz */
 173 #define CONFIG_SYS_I2C_SLAVE    0x7F
 174
 175 /*
 176  * EEPROM configuration
 177  */
 178 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 179 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2
 180 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       6
 181 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
 182
 183 /*
 184  * RTC configuration
 185  */
 186 #define CONFIG_RTC_PCF8563
 187 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 188
 189 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 190 #define CONFIG_SYS_FLASH_SIZE           0x01000000
 191 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + \
 192                                          CONFIG_SYS_MONITOR_LEN)
 193
 194 #define CONFIG_SYS_MAX_FLASH_BANKS      1    /* max num of memory banks */
 195 #define CONFIG_SYS_MAX_FLASH_SECT       256  /* max num of sects on one chip */
 196 #define CONFIG_SYS_FLASH_PROTECTION  /* "Real" (hardware) sectors protection */
 197
 198 /* use CFI flash driver */
 199 #define CONFIG_FLASH_CFI_DRIVER
 200 #define CONFIG_SYS_FLASH_CFI
 201 #define CONFIG_SYS_FLASH_EMPTY_INFO
 202 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1
 203
 204 /*
 205  * Environment settings
 206  */
 207 #define CONFIG_ENV_IS_IN_FLASH          1
 208 #define CONFIG_ENV_SIZE                 0x10000
 209 #define CONFIG_ENV_SECT_SIZE            0x20000
 210 #define CONFIG_ENV_OVERWRITE            1
 211 #define CONFIG_ENV_ADDR_REDUND          (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 212 #define CONFIG_ENV_SIZE_REDUND          CONFIG_ENV_SIZE
 213
 214 /*
 215  * Memory map
 216  */
 217 #define CONFIG_SYS_MBAR                 0xf0000000
 218 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 219 #define CONFIG_SYS_DEFAULT_MBAR         0x80000000
 220 #define CONFIG_SYS_SRAM_BASE            0xF1000000
 221 #define CONFIG_SYS_SRAM_SIZE            0x00200000
 222 #define CONFIG_SYS_LIME_BASE            0xE4000000
 223 #define CONFIG_SYS_LIME_SIZE            0x04000000
 224 #define CONFIG_SYS_FPGA_BASE            0xC0000000
 225 #define CONFIG_SYS_FPGA_SIZE            0x10000000
 226 #define CONFIG_SYS_MPEG_BASE            0xe2000000
 227 #define CONFIG_SYS_MPEG_SIZE            0x01000000
 228 #define CONFIG_SYS_CF_BASE              0xe1000000
 229 #define CONFIG_SYS_CF_SIZE              0x01000000
 230
 231 /* Use SRAM until RAM will be available */
 232 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 233 /* End of used area in DPRAM */
 234 #define CONFIG_SYS_INIT_RAM_SIZE                MPC5XXX_SRAM_SIZE
 235
 236 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 237                                          GENERATED_GBL_DATA_SIZE)
 238 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 239
 240 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 241 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 242 #   define CONFIG_SYS_RAMBOOT           1
 243 #endif
 244
 245 #define CONFIG_SYS_MONITOR_LEN  (384 << 10)  /* Reserve 384 kB for Monitor */
 246 #define CONFIG_SYS_MALLOC_LEN   (4 << 20)    /* Reserve 128 kB for malloc() */
 247 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)    /* Initial Memory map for Linux */
 248
 249 /*
 250  * Ethernet configuration
 251  */
 252 #define CONFIG_MPC5xxx_FEC              1
 253 #define CONFIG_MPC5xxx_FEC_MII100
 254 #define CONFIG_PHY_ADDR                 0x00
 255
 256 /*
 257  * GPIO configuration
 258  */
 259 #define CONFIG_SYS_GPS_PORT_CONFIG      0x1d556624
 260
 261 /*
 262  * Miscellaneous configurable options
 263  */
 264 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 265 #ifdef CONFIG_CMD_KGDB
 266 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size */
 267 #else
 268 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 269 #endif
 270 /* Print Buffer Size */
 271 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 272                                          sizeof(CONFIG_SYS_PROMPT) + 16)
 273 /* max number of command args */
 274 #define CONFIG_SYS_MAXARGS              16
 275 /* Boot Argument Buffer Size */
 276 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 277
 278 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on */
 279 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1...15 MB in DRAM */
 280
 281 #define CONFIG_SYS_LOAD_ADDR            0x100000 /* default load address */
 282
 283 /*
 284  * Various low-level settings
 285  */
 286 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 287 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 288
 289 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 290 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 291 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 292 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 293 #define CONFIG_SYS_CS1_START            CONFIG_SYS_SRAM_BASE
 294 #define CONFIG_SYS_CS1_SIZE             CONFIG_SYS_SRAM_SIZE
 295 #define CONFIG_SYS_CS3_START            CONFIG_SYS_LIME_BASE
 296 #define CONFIG_SYS_CS3_SIZE             CONFIG_SYS_LIME_SIZE
 297 #define CONFIG_SYS_CS6_START            CONFIG_SYS_FPGA_BASE
 298 #define CONFIG_SYS_CS6_SIZE             CONFIG_SYS_FPGA_SIZE
 299 #define CONFIG_SYS_CS5_START            CONFIG_SYS_CF_BASE
 300 #define CONFIG_SYS_CS5_SIZE             CONFIG_SYS_CF_SIZE
 301 #define CONFIG_SYS_CS7_START            CONFIG_SYS_MPEG_BASE
 302 #define CONFIG_SYS_CS7_SIZE             CONFIG_SYS_MPEG_SIZE
 303
 304 #ifdef CONFIG_SYS_PCISPEED_66
 305 #define CONFIG_SYS_BOOTCS_CFG           0x0006F900
 306 #define CONFIG_SYS_CS1_CFG              0x0004FB00
 307 #define CONFIG_SYS_CS2_CFG              0x0006F900
 308 #else
 309 #define CONFIG_SYS_BOOTCS_CFG           0x0002F900
 310 #define CONFIG_SYS_CS1_CFG              0x0001FB00
 311 #define CONFIG_SYS_CS2_CFG              0x0002F90C
 312 #endif
 313
 314 /*
 315  * Ack active, Muxed mode, AS=24 bit address, DS=32 bit data, 0
 316  * waitstates, writeswap and readswap enabled
 317  */
 318 #define CONFIG_SYS_CS3_CFG              0x00FFFB0C
 319 #define CONFIG_SYS_CS6_CFG              0x00FFFB0C
 320 #define CONFIG_SYS_CS7_CFG              0x4040751C
 321
 322 #define CONFIG_SYS_CS_BURST             0x00000000
 323 #define CONFIG_SYS_CS_DEADCYCLE         0x33330000
 324
 325 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 326
 327 /*-----------------------------------------------------------------------
 328  * USB stuff
 329  *-----------------------------------------------------------------------
 330  */
 331 #define CONFIG_USB_CLOCK                0x0001BBBB
 332 #define CONFIG_USB_CONFIG               0x00005000
 333
 334 /*-----------------------------------------------------------------------
 335  * IDE/ATA stuff Supports IDE harddisk
 336  *-----------------------------------------------------------------------
 337  */
 338 #define CONFIG_IDE_PREINIT
 339
 340 #define CONFIG_SYS_IDE_MAXBUS           1 /* max. 1 IDE bus */
 341 #define CONFIG_SYS_IDE_MAXDEVICE        2 /* max. 2 drives per IDE bus */
 342
 343 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 344
 345 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 346
 347 /* Offset for data I/O */
 348 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 349
 350 /* Offset for normal register accesses */
 351 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 352
 353 /* Offset for alternate registers */
 354 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 355
 356 /* Interval between registers */
 357 #define CONFIG_SYS_ATA_STRIDE           4
 358
 359 #endif /* __CONFIG_H */