include/configs/katmai.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /************************************************************************
  27  * katmai.h - configuration for AMCC Katmai (440SPe)
  28  ***********************************************************************/
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*-----------------------------------------------------------------------
  34  * High Level Configuration Options
  35  *----------------------------------------------------------------------*/
  36 #define CONFIG_KATMAI                   1       /* Board is Katmai      */
  37 #define CONFIG_4xx                      1       /* ... PPC4xx family    */
  38 #define CONFIG_440                      1       /* ... PPC440 family    */
  39 #define CONFIG_440SPE                   1       /* Specifc SPe support  */
  40 #define CONFIG_440SPE_REVA              1       /* Support old Rev A.   */
  41 #define CONFIG_SYS_CLK_FREQ     33333333        /* external freq to pll */
  42 #define CONFIG_SYS_4xx_RESET_TYPE       0x2     /* use chip reset on this board */
  43
  44 /*
  45  * Enable this board for more than 2GB of SDRAM
  46  */
  47 #define CONFIG_PHYS_64BIT
  48 #define CONFIG_VERY_BIG_RAM
  49
  50 /*
  51  * Include common defines/options for all AMCC eval boards
  52  */
  53 #define CONFIG_HOSTNAME         katmai
  54 #include "amcc-common.h"
  55
  56 /*
  57  * For booting 256K-paged Linux we should have 16MB of memory
  58  * for Linux initial memory map
  59  */
  60 #undef CONFIG_SYS_BOOTMAPSZ
  61 #define CONFIG_SYS_BOOTMAPSZ    (16 << 20)
  62
  63 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_pre_init          */
  64 #undef  CONFIG_SHOW_BOOT_PROGRESS
  65
  66 /*-----------------------------------------------------------------------
  67  * Base addresses -- Note these are effective addresses where the
  68  * actual resources get mapped (not physical addresses)
  69  *----------------------------------------------------------------------*/
  70 #define CONFIG_SYS_FLASH_BASE           0xff000000      /* start of FLASH       */
  71 #define CONFIG_SYS_PERIPHERAL_BASE      0xa0000000      /* internal peripherals */
  72 #define CONFIG_SYS_ISRAM_BASE           0x90000000      /* internal SRAM        */
  73
  74 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped PCI memory    */
  75 #define CONFIG_SYS_PCI_BASE             0xd0000000      /* internal PCI regs    */
  76 #define CONFIG_SYS_PCI_TARGBASE CONFIG_SYS_PCI_MEMBASE
  77
  78 #define CONFIG_SYS_PCIE_MEMBASE 0xb0000000      /* mapped PCIe memory   */
  79 #define CONFIG_SYS_PCIE_MEMSIZE 0x08000000      /* smallest incr for PCIe port */
  80 #define CONFIG_SYS_PCIE_BASE            0xe0000000      /* PCIe UTL regs */
  81
  82 #define CONFIG_SYS_PCIE0_CFGBASE        0xc0000000
  83 #define CONFIG_SYS_PCIE1_CFGBASE        0xc1000000
  84 #define CONFIG_SYS_PCIE2_CFGBASE        0xc2000000
  85 #define CONFIG_SYS_PCIE0_XCFGBASE       0xc3000000
  86 #define CONFIG_SYS_PCIE1_XCFGBASE       0xc3001000
  87 #define CONFIG_SYS_PCIE2_XCFGBASE       0xc3002000
  88
  89 /* base address of inbound PCIe window */
  90 #define CONFIG_SYS_PCIE_INBOUND_BASE    0x0000000000000000ULL
  91
  92 /* System RAM mapped to PCI space */
  93 #define CONFIG_PCI_SYS_MEM_BUS  CONFIG_SYS_SDRAM_BASE
  94 #define CONFIG_PCI_SYS_MEM_PHYS CONFIG_SYS_SDRAM_BASE
  95 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
  96
  97 #define CONFIG_SYS_ACE_BASE             0xfe000000      /* Xilinx ACE controller - Compact Flash */
  98
  99 /*-----------------------------------------------------------------------
 100  * Initial RAM & stack pointer (placed in internal SRAM)
 101  *----------------------------------------------------------------------*/
 102 #define CONFIG_SYS_TEMP_STACK_OCM       1
 103 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_ISRAM_BASE
 104 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_ISRAM_BASE   /* Initial RAM address  */
 105 #define CONFIG_SYS_INIT_RAM_END 0x2000          /* End of used area in RAM */
 106 #define CONFIG_SYS_GBL_DATA_SIZE        128             /* num bytes initial data */
 107
 108 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 109 #define CONFIG_SYS_POST_WORD_ADDR       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
 110 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_POST_WORD_ADDR
 111
 112 /*-----------------------------------------------------------------------
 113  * Serial Port
 114  *----------------------------------------------------------------------*/
 115 #undef CONFIG_UART1_CONSOLE
 116 #undef CONFIG_SYS_EXT_SERIAL_CLOCK
 117
 118 /*-----------------------------------------------------------------------
 119  * DDR SDRAM
 120  *----------------------------------------------------------------------*/
 121 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 122 #define SPD_EEPROM_ADDRESS      {0x51, 0x52}    /* SPD i2c spd addresses*/
 123 #define CONFIG_DDR_ECC          1       /* with ECC support             */
 124 #define CONFIG_DDR_RQDC_FIXED   0x80000038 /* optimal value found by GDA*/
 125 #undef  CONFIG_STRESS
 126
 127 /*-----------------------------------------------------------------------
 128  * I2C
 129  *----------------------------------------------------------------------*/
 130 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 131
 132 #define CONFIG_I2C_MULTI_BUS
 133 #define CONFIG_SYS_SPD_BUS_NUM          0       /* The I2C bus for SPD          */
 134
 135 #define IIC0_BOOTPROM_ADDR      0x50
 136 #define IIC0_ALT_BOOTPROM_ADDR  0x54
 137
 138 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 139 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0x50)
 140 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 141 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 142 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 143
 144 /* I2C bootstrap EEPROM */
 145 #define CONFIG_4xx_CONFIG_I2C_EEPROM_ADDR       0x50
 146 #define CONFIG_4xx_CONFIG_I2C_EEPROM_OFFSET     0
 147 #define CONFIG_4xx_CONFIG_BLOCKSIZE             8
 148
 149 /* I2C RTC */
 150 #define CONFIG_RTC_M41T11       1
 151 #define CONFIG_SYS_RTC_BUS_NUM          1       /* The I2C bus for RTC          */
 152 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 153 #define CONFIG_SYS_M41T11_BASE_YEAR     1900    /* play along with linux        */
 154
 155 /* I2C DTT */
 156 #define CONFIG_DTT_ADM1021      1       /* ADM1021 temp sensor support  */
 157 #define CONFIG_SYS_DTT_BUS_NUM          1       /* The I2C bus for DTT          */
 158 /*
 159  * standard dtt sensor configuration - bottom bit will determine local or
 160  * remote sensor of the ADM1021, the rest determines index into
 161  * CONFIG_SYS_DTT_ADM1021 array below.
 162  */
 163 #define CONFIG_DTT_SENSORS      { 0, 1 }
 164
 165 /*
 166  * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
 167  * there will be one entry in this array for each two (dummy) sensors in
 168  * CONFIG_DTT_SENSORS.
 169  *
 170  * For Katmai board:
 171  * - only one ADM1021
 172  * - i2c addr 0x18
 173  * - conversion rate 0x02 = 0.25 conversions/second
 174  * - ALERT ouput disabled
 175  * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
 176  * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
 177  */
 178 #define CONFIG_SYS_DTT_ADM1021          { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
 179
 180 /*-----------------------------------------------------------------------
 181  * Environment
 182  *----------------------------------------------------------------------*/
 183 #define CONFIG_ENV_IS_IN_FLASH  1       /* Environment uses flash       */
 184
 185 /*
 186  * Default environment variables
 187  */
 188 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 189         CONFIG_AMCC_DEF_ENV                                             \
 190         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
 191         CONFIG_AMCC_DEF_ENV_PPC_OLD                                     \
 192         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 193         "kernel_addr=fff10000\0"                                        \
 194         "ramdisk_addr=fff20000\0"                                       \
 195         "kozio=bootm ffc60000\0"                                        \
 196         "pciconfighost=1\0"                                             \
 197         "pcie_mode=RP:RP:RP\0"                                          \
 198         ""
 199
 200 /*
 201  * Commands additional to the ones defined in amcc-common.h
 202  */
 203 #define CONFIG_CMD_CHIP_CONFIG
 204 #define CONFIG_CMD_DATE
 205 #define CONFIG_CMD_ECCTEST
 206 #define CONFIG_CMD_EXT2
 207 #define CONFIG_CMD_FAT
 208 #define CONFIG_CMD_PCI
 209 #define CONFIG_CMD_SDRAM
 210 #define CONFIG_CMD_SNTP
 211
 212 #define CONFIG_IBM_EMAC4_V4     1       /* 440SPe has this EMAC version */
 213 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 214 #define CONFIG_HAS_ETH0
 215 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 216 #define CONFIG_PHY_RESET_DELAY  1000
 217 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 218 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 219
 220 /*-----------------------------------------------------------------------
 221  * FLASH related
 222  *----------------------------------------------------------------------*/
 223 #define CONFIG_SYS_FLASH_CFI
 224 #define CONFIG_FLASH_CFI_DRIVER
 225 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 226 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 227
 228 #define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
 229 #define CONFIG_SYS_MAX_FLASH_BANKS     1                    /* number of banks      */
 230 #define CONFIG_SYS_MAX_FLASH_SECT       1024                /* sectors per device   */
 231
 232 #undef  CONFIG_SYS_FLASH_CHECKSUM
 233 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 234 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 235
 236 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector  */
 237 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 238 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 239
 240 /* Address and size of Redundant Environment Sector     */
 241 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 242 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 243
 244 /*-----------------------------------------------------------------------
 245  * PCI stuff
 246  *-----------------------------------------------------------------------
 247  */
 248 /* General PCI */
 249 #define CONFIG_PCI                      /* include pci support          */
 250 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 251 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 252 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 253
 254 /* Board-specific PCI */
 255 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 256 #undef  CONFIG_SYS_PCI_MASTER_INIT
 257
 258 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1014   /* IBM                          */
 259 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever                     */
 260 /* #define CONFIG_SYS_PCI_SUBSYS_ID     CONFIG_SYS_PCI_SUBSYS_DEVICEID */
 261
 262 /*
 263  *  NETWORK Support (PCI):
 264  */
 265 /* Support for Intel 82557/82559/82559ER chips. */
 266 #define CONFIG_EEPRO100
 267
 268 /*-----------------------------------------------------------------------
 269  * Xilinx System ACE support
 270  *----------------------------------------------------------------------*/
 271 #define CONFIG_SYSTEMACE        1       /* Enable SystemACE support     */
 272 #define CONFIG_SYS_SYSTEMACE_WIDTH      16      /* Data bus width is 16         */
 273 #define CONFIG_SYS_SYSTEMACE_BASE       CONFIG_SYS_ACE_BASE
 274 #define CONFIG_DOS_PARTITION    1
 275
 276 /*-----------------------------------------------------------------------
 277  * External Bus Controller (EBC) Setup
 278  *----------------------------------------------------------------------*/
 279
 280 /* Memory Bank 0 (Flash) initialization                                 */
 281 #define CONFIG_SYS_EBC_PB0AP            (EBC_BXAP_BME_DISABLED      |           \
 282                                  EBC_BXAP_TWT_ENCODE(7)     |           \
 283                                  EBC_BXAP_BCE_DISABLE       |           \
 284                                  EBC_BXAP_BCT_2TRANS        |           \
 285                                  EBC_BXAP_CSN_ENCODE(0)     |           \
 286                                  EBC_BXAP_OEN_ENCODE(0)     |           \
 287                                  EBC_BXAP_WBN_ENCODE(0)     |           \
 288                                  EBC_BXAP_WBF_ENCODE(0)     |           \
 289                                  EBC_BXAP_TH_ENCODE(0)      |           \
 290                                  EBC_BXAP_RE_DISABLED       |           \
 291                                  EBC_BXAP_SOR_DELAYED       |           \
 292                                  EBC_BXAP_BEM_WRITEONLY     |           \
 293                                  EBC_BXAP_PEN_DISABLED)
 294 #define CONFIG_SYS_EBC_PB0CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_FLASH_BASE) |   \
 295                                  EBC_BXCR_BS_16MB                    |  \
 296                                  EBC_BXCR_BU_RW                      |  \
 297                                  EBC_BXCR_BW_16BIT)
 298
 299 /* Memory Bank 1 (Xilinx System ACE controller) initialization          */
 300 #define CONFIG_SYS_EBC_PB1AP            (EBC_BXAP_BME_DISABLED      |           \
 301                                  EBC_BXAP_TWT_ENCODE(4)     |           \
 302                                  EBC_BXAP_BCE_DISABLE       |           \
 303                                  EBC_BXAP_BCT_2TRANS        |           \
 304                                  EBC_BXAP_CSN_ENCODE(0)     |           \
 305                                  EBC_BXAP_OEN_ENCODE(0)     |           \
 306                                  EBC_BXAP_WBN_ENCODE(0)     |           \
 307                                  EBC_BXAP_WBF_ENCODE(0)     |           \
 308                                  EBC_BXAP_TH_ENCODE(0)      |           \
 309                                  EBC_BXAP_RE_DISABLED       |           \
 310                                  EBC_BXAP_SOR_NONDELAYED    |           \
 311                                  EBC_BXAP_BEM_WRITEONLY     |           \
 312                                  EBC_BXAP_PEN_DISABLED)
 313 #define CONFIG_SYS_EBC_PB1CR            (EBC_BXCR_BAS_ENCODE(CONFIG_SYS_ACE_BASE)  |    \
 314                                  EBC_BXCR_BS_1MB                    |   \
 315                                  EBC_BXCR_BU_RW                     |   \
 316                                  EBC_BXCR_BW_16BIT)
 317
 318 /*-------------------------------------------------------------------------
 319  * Initialize EBC CONFIG -
 320  * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
 321  * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
 322  *-------------------------------------------------------------------------*/
 323 #define CONFIG_SYS_EBC_CFG              (EBC_CFG_LE_UNLOCK    | \
 324                                  EBC_CFG_PTD_ENABLE   | \
 325                                  EBC_CFG_RTC_16PERCLK | \
 326                                  EBC_CFG_ATC_PREVIOUS | \
 327                                  EBC_CFG_DTC_PREVIOUS | \
 328                                  EBC_CFG_CTC_PREVIOUS | \
 329                                  EBC_CFG_OEO_PREVIOUS | \
 330                                  EBC_CFG_EMC_DEFAULT  | \
 331                                  EBC_CFG_PME_DISABLE  | \
 332                                  EBC_CFG_PR_16)
 333
 334 /*-----------------------------------------------------------------------
 335  * GPIO Setup
 336  *----------------------------------------------------------------------*/
 337 #define CONFIG_SYS_GPIO_PCIE_PRESENT0   17
 338 #define CONFIG_SYS_GPIO_PCIE_PRESENT1   21
 339 #define CONFIG_SYS_GPIO_PCIE_PRESENT2   23
 340 #define CONFIG_SYS_GPIO_RS232_FORCEOFF  30
 341
 342 #define CONFIG_SYS_PFC0         (GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT0) | \
 343                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT1) | \
 344                                  GPIO_VAL(CONFIG_SYS_GPIO_PCIE_PRESENT2) | \
 345                                  GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF))
 346 #define CONFIG_SYS_GPIO_OR              GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 347 #define CONFIG_SYS_GPIO_TCR             GPIO_VAL(CONFIG_SYS_GPIO_RS232_FORCEOFF)
 348 #define CONFIG_SYS_GPIO_ODR             0
 349
 350 #endif  /* __CONFIG_H */