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[PATCH] Add support for the AMCC Katmai (440SPe) eval board
[people/ms/u-boot.git] / include / configs / katmai.h
1 /*
2 * (C) Copyright 2007
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26 /************************************************************************
27 * katmai.h - configuration for AMCC Katmai (440SPe)
28 ***********************************************************************/
29
30 #ifndef __CONFIG_H
31 #define __CONFIG_H
32
33 /*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 *----------------------------------------------------------------------*/
36 #define CONFIG_KATMAI 1 /* Board is Katmai */
37 #define CONFIG_4xx 1 /* ... PPC4xx family */
38 #define CONFIG_440 1 /* ... PPC440 family */
39 #define CONFIG_440SPE 1 /* Specifc SPe support */
40 #undef CFG_DRAM_TEST /* Disable-takes long time */
41 #define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
42
43 #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
44 #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */
45 #define CONFIG_ADD_RAM_INFO 1 /* Print additional info */
46 #undef CONFIG_SHOW_BOOT_PROGRESS
47
48 /*-----------------------------------------------------------------------
49 * Base addresses -- Note these are effective addresses where the
50 * actual resources get mapped (not physical addresses)
51 *----------------------------------------------------------------------*/
52 #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
53 #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */
54
55 #define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */
56 #define CFG_FLASH_BASE 0xff000000 /* start of FLASH */
57 #define CFG_MONITOR_BASE TEXT_BASE
58 #define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */
59 #define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */
60
61 #define CFG_PCI_MEMBASE 0x80000000 /* mapped PCI memory */
62 #define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */
63 #define CFG_PCI_TARGBASE CFG_PCI_MEMBASE
64
65 #define CFG_PCIE_MEMBASE 0xb0000000 /* mapped PCIe memory */
66 #define CFG_PCIE_MEMSIZE 0x01000000
67 #define CFG_PCIE_BASE 0xe0000000 /* PCIe UTL regs */
68
69 #define CFG_PCIE0_CFGBASE 0xc0000000
70 #define CFG_PCIE0_XCFGBASE 0xc0000400
71 #define CFG_PCIE1_CFGBASE 0xc0001000
72 #define CFG_PCIE1_XCFGBASE 0xc0001400
73 #define CFG_PCIE2_CFGBASE 0xc0002000
74 #define CFG_PCIE2_XCFGBASE 0xc0002400
75
76 /* System RAM mapped to PCI space */
77 #define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE
78 #define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE
79 #define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024)
80
81 #define CFG_ACE_BASE 0xe0000000 /* Xilinx ACE controller - Compact Flash */
82
83 /*-----------------------------------------------------------------------
84 * Initial RAM & stack pointer (placed in internal SRAM)
85 *----------------------------------------------------------------------*/
86 #define CFG_TEMP_STACK_OCM 1
87 #define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE
88 #define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */
89 #define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */
90 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
91
92 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
93 #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4)
94 #define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR
95
96 /*-----------------------------------------------------------------------
97 * Serial Port
98 *----------------------------------------------------------------------*/
99 #define CONFIG_SERIAL_MULTI 1
100 #undef CONFIG_UART1_CONSOLE
101 #undef CFG_EXT_SERIAL_CLOCK
102 #define CONFIG_BAUDRATE 115200
103 #define CFG_BAUDRATE_TABLE \
104 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
105
106 /*-----------------------------------------------------------------------
107 * DDR SDRAM
108 *----------------------------------------------------------------------*/
109 #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */
110 #define SPD_EEPROM_ADDRESS {0x51, 0x52} /* SPD i2c spd addresses */
111 #define IIC0_DIMM0_ADDR 0x51
112 #define IIC0_DIMM1_ADDR 0x52
113 #undef CONFIG_STRESS
114 #undef ENABLE_ECC
115
116 /*-----------------------------------------------------------------------
117 * I2C
118 *----------------------------------------------------------------------*/
119 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
120 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
121 #define CFG_I2C_SPEED 100000 /* I2C speed and slave address */
122 #define CFG_I2C_SLAVE 0x7F
123
124 #define CONFIG_I2C_MULTI_BUS
125 #define CONFIG_I2C_CMD_TREE
126 #define CFG_SPD_BUS_NUM 0 /* The I2C bus for SPD */
127
128 #define IIC0_BOOTPROM_ADDR 0x50
129 #define IIC0_ALT_BOOTPROM_ADDR 0x54
130
131 #define CFG_I2C_MULTI_EEPROMS
132 #define CFG_I2C_EEPROM_ADDR (0x50)
133 #define CFG_I2C_EEPROM_ADDR_LEN 1
134 #define CFG_EEPROM_PAGE_WRITE_ENABLE
135 #define CFG_EEPROM_PAGE_WRITE_BITS 3
136 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
137
138 /* I2C RTC */
139 #define CONFIG_RTC_M41T11 1
140 #define CFG_RTC_BUS_NUM 1 /* The I2C bus for RTC */
141 #define CFG_I2C_RTC_ADDR 0x68
142 #define CFG_M41T11_BASE_YEAR 1900 /* play along with linux */
143
144 /* I2C DTT */
145 #define CONFIG_DTT_ADM1021 1 /* ADM1021 temp sensor support */
146 #define CFG_DTT_BUS_NUM 1 /* The I2C bus for DTT */
147 /*
148 * standard dtt sensor configuration - bottom bit will determine local or
149 * remote sensor of the ADM1021, the rest determines index into
150 * CFG_DTT_ADM1021 array below.
151 */
152 #define CONFIG_DTT_SENSORS { 0, 1 }
153
154 /*
155 * ADM1021 temp sensor configuration (see dtt/adm1021.c for details).
156 * there will be one entry in this array for each two (dummy) sensors in
157 * CONFIG_DTT_SENSORS.
158 *
159 * For Katmai board:
160 * - only one ADM1021
161 * - i2c addr 0x18
162 * - conversion rate 0x02 = 0.25 conversions/second
163 * - ALERT ouput disabled
164 * - local temp sensor enabled, min set to 0 deg, max set to 85 deg
165 * - remote temp sensor enabled, min set to 0 deg, max set to 85 deg
166 */
167 #define CFG_DTT_ADM1021 { { 0x18, 0x02, 0, 1, 0, 85, 1, 0, 58} }
168
169 /*-----------------------------------------------------------------------
170 * Environment
171 *----------------------------------------------------------------------*/
172 #define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */
173
174 #define CONFIG_PREBOOT "echo;" \
175 "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
176 "echo"
177
178 #undef CONFIG_BOOTARGS
179
180 #define CONFIG_EXTRA_ENV_SETTINGS \
181 "netdev=eth0\0" \
182 "hostname=katmai\0" \
183 "nfsargs=setenv bootargs root=/dev/nfs rw " \
184 "nfsroot=${serverip}:${rootpath}\0" \
185 "ramargs=setenv bootargs root=/dev/ram rw\0" \
186 "addip=setenv bootargs ${bootargs} " \
187 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
188 ":${hostname}:${netdev}:off panic=1\0" \
189 "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
190 "flash_nfs=run nfsargs addip addtty;" \
191 "bootm ${kernel_addr}\0" \
192 "flash_self=run ramargs addip addtty;" \
193 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
194 "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \
195 "bootm\0" \
196 "rootpath=/opt/eldk/ppc_4xx\0" \
197 "bootfile=katmai/uImage\0" \
198 "kernel_addr=fff10000\0" \
199 "ramdisk_addr=fff20000\0" \
200 "initrd_high=30000000\0" \
201 "load=tftp 200000 katmai/u-boot.bin\0" \
202 "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \
203 "cp.b ${fileaddr} fffc0000 ${filesize};" \
204 "setenv filesize;saveenv\0" \
205 "upd=run load;run update\0" \
206 "kozio=bootm ffc60000\0" \
207 ""
208 #define CONFIG_BOOTCOMMAND "run flash_self"
209
210 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
211
212 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
213 #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
214
215 #define CONFIG_COMMANDS (CONFIG_CMD_DFL | \
216 CFG_CMD_ASKENV | \
217 CFG_CMD_EEPROM | \
218 CFG_CMD_DATE | \
219 CFG_CMD_DHCP | \
220 CFG_CMD_DIAG | \
221 CFG_CMD_DTT | \
222 CFG_CMD_ELF | \
223 CFG_CMD_EXT2 | \
224 CFG_CMD_FAT | \
225 CFG_CMD_I2C | \
226 CFG_CMD_IRQ | \
227 CFG_CMD_MII | \
228 CFG_CMD_NET | \
229 CFG_CMD_NFS | \
230 CFG_CMD_PCI | \
231 CFG_CMD_PING | \
232 CFG_CMD_REGINFO | \
233 CFG_CMD_SDRAM)
234
235 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
236 #include <cmd_confdefs.h>
237
238 #define CONFIG_IBM_EMAC4_V4 1 /* 440SPe has this EMAC version */
239 #define CONFIG_MII 1 /* MII PHY management */
240 #define CONFIG_PHY_ADDR 1 /* PHY address, See schematics */
241 #define CONFIG_HAS_ETH0
242 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
243 #define CONFIG_PHY_RESET_DELAY 1000
244 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */
245 #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
246 #define CFG_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
247
248 #define CONFIG_NETCONSOLE /* include NetConsole support */
249 #define CONFIG_NET_MULTI /* needed for NetConsole */
250
251 #undef CONFIG_WATCHDOG /* watchdog disabled */
252
253 /*
254 * Miscellaneous configurable options
255 */
256 #define CFG_LONGHELP /* undef to save memory */
257 #define CFG_PROMPT "=> " /* Monitor Command Prompt */
258
259 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
260 #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
261 #else
262 #define CFG_CBSIZE 256 /* Console I/O Buffer Size */
263 #endif
264 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
265 #define CFG_MAXARGS 16 /* max number of command args */
266 #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
267
268 #define CFG_MEMTEST_START 0x0400000 /* memtest works on */
269 #define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
270
271 #define CFG_LOAD_ADDR 0x100000 /* default load address */
272 #define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */
273
274 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
275
276 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
277 #define CONFIG_LOOPW 1 /* enable loopw command */
278 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
279 #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */
280 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
281
282 #define CFG_4xx_RESET_TYPE 0x2 /* use chip reset on this board */
283
284 /*-----------------------------------------------------------------------
285 * FLASH related
286 *----------------------------------------------------------------------*/
287 #define CFG_FLASH_CFI
288 #define CFG_FLASH_CFI_DRIVER
289 #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
290 #define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
291
292 #define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE}
293 #define CFG_MAX_FLASH_BANKS 1 /* number of banks */
294 #define CFG_MAX_FLASH_SECT 1024 /* sectors per device */
295
296 #undef CFG_FLASH_CHECKSUM
297 #define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
298 #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
299
300 #define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */
301 #define CFG_ENV_ADDR (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
302 #define CFG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
303
304 /* Address and size of Redundant Environment Sector */
305 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
306 #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
307
308 /*-----------------------------------------------------------------------
309 * PCI stuff
310 *-----------------------------------------------------------------------
311 */
312 /* General PCI */
313 #define CONFIG_PCI /* include pci support */
314 #define CONFIG_PCI_PNP 1 /* do pci plug-and-play */
315 #define CONFIG_PCI_SCAN_SHOW 1 /* show pci devices on startup */
316 #undef CONFIG_PCI_CONFIG_HOST_BRIDGE
317
318 /* Board-specific PCI */
319 #define CFG_PCI_PRE_INIT 1 /* enable board pci_pre_init() */
320 #define CFG_PCI_TARGET_INIT /* let board init pci target */
321 #undef CFG_PCI_MASTER_INIT
322
323 #define CFG_PCI_SUBSYS_VENDORID 0x1014 /* IBM */
324 #define CFG_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
325 /* #define CFG_PCI_SUBSYS_ID CFG_PCI_SUBSYS_DEVICEID */
326
327 /*
328 * NETWORK Support (PCI):
329 */
330 /* Support for Intel 82557/82559/82559ER chips. */
331 #define CONFIG_EEPRO100
332
333 /*-----------------------------------------------------------------------
334 * Xilinx System ACE support
335 *----------------------------------------------------------------------*/
336 #define CONFIG_SYSTEMACE 1 /* Enable SystemACE support */
337 #define CFG_SYSTEMACE_WIDTH 16 /* Data bus width is 16 */
338 #define CFG_SYSTEMACE_BASE CFG_ACE_BASE
339 #define CONFIG_DOS_PARTITION 1
340
341 /*-----------------------------------------------------------------------
342 * External Bus Controller (EBC) Setup
343 *----------------------------------------------------------------------*/
344
345 /* Memory Bank 0 (Flash) initialization */
346 #define CFG_EBC_PB0AP (EBC_BXAP_BME_DISABLED | \
347 EBC_BXAP_TWT_ENCODE(7) | \
348 EBC_BXAP_BCE_DISABLE | \
349 EBC_BXAP_BCT_2TRANS | \
350 EBC_BXAP_CSN_ENCODE(0) | \
351 EBC_BXAP_OEN_ENCODE(0) | \
352 EBC_BXAP_WBN_ENCODE(0) | \
353 EBC_BXAP_WBF_ENCODE(0) | \
354 EBC_BXAP_TH_ENCODE(0) | \
355 EBC_BXAP_RE_DISABLED | \
356 EBC_BXAP_SOR_DELAYED | \
357 EBC_BXAP_BEM_WRITEONLY | \
358 EBC_BXAP_PEN_DISABLED)
359 #define CFG_EBC_PB0CR (EBC_BXCR_BAS_ENCODE(CFG_FLASH_BASE) | \
360 EBC_BXCR_BS_16MB | \
361 EBC_BXCR_BU_RW | \
362 EBC_BXCR_BW_16BIT)
363
364 /* Memory Bank 1 (Xilinx System ACE controller) initialization */
365 #define CFG_EBC_PB1AP 0x7F8FFE80
366 #define CFG_EBC_PB1CR (EBC_BXCR_BAS_ENCODE(CFG_ACE_BASE) | \
367 EBC_BXCR_BS_1MB | \
368 EBC_BXCR_BU_RW | \
369 EBC_BXCR_BW_16BIT)
370
371 /*-------------------------------------------------------------------------
372 * Initialize EBC CONFIG -
373 * Keep the Default value, but the bit PDT which has to be set to 1 ?TBC
374 * default value : 0x07C00000 - 0 0 000 1 1 1 1 1 0000 0 00000 000000000000
375 *-------------------------------------------------------------------------*/
376 #define CFG_EBC_CFG (EBC_CFG_LE_UNLOCK | \
377 EBC_CFG_PTD_ENABLE | \
378 EBC_CFG_RTC_16PERCLK | \
379 EBC_CFG_ATC_PREVIOUS | \
380 EBC_CFG_DTC_PREVIOUS | \
381 EBC_CFG_CTC_PREVIOUS | \
382 EBC_CFG_OEO_PREVIOUS | \
383 EBC_CFG_EMC_DEFAULT | \
384 EBC_CFG_PME_DISABLE | \
385 EBC_CFG_PR_16)
386
387 /*
388 * For booting Linux, the board info and command line data
389 * have to be in the first 8 MB of memory, since this is
390 * the maximum mapped by the Linux kernel during initialization.
391 */
392 #define CFG_BOOTMAPSZ (8 << 20) /*Initial Memory map for Linux*/
393 /*-----------------------------------------------------------------------
394 * Cache Configuration
395 */
396 #define CFG_DCACHE_SIZE 8192 /* For AMCC 405 CPUs */
397 #define CFG_CACHELINE_SIZE 32 /* ... */
398 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
399 #define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
400 #endif
401
402 /*
403 * Internal Definitions
404 *
405 * Boot Flags
406 */
407 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
408 #define BOOTFLAG_WARM 0x02 /* Software reboot */
409
410 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
411 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
412 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
413 #endif
414
415 #endif /* __CONFIG_H */
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