include/configs/km/km83xx-common.h

   1 /*
   2  * (C) Copyright 2010
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  */
  10
  11 #ifndef __CONFIG_KM83XX_H
  12 #define __CONFIG_KM83XX_H
  13
  14 /* include common defines/options for all Keymile boards */
  15 #include "keymile-common.h"
  16 #include "km-powerpc.h"
  17
  18 #ifndef MTDIDS_DEFAULT
  19 # define MTDIDS_DEFAULT "nor0=boot"
  20 #endif /* MTDIDS_DEFAULT */
  21
  22 #ifndef MTDPARTS_DEFAULT
  23 # define MTDPARTS_DEFAULT       "mtdparts="                     \
  24         "boot:"                                                 \
  25                 "768k(u-boot),"                                 \
  26                 "128k(env),"                                    \
  27                 "128k(envred),"                                 \
  28                 "-(" CONFIG_KM_UBI_PARTITION_NAME_BOOT ");"
  29 #endif /* MTDPARTS_DEFAULT */
  30
  31 #define CONFIG_MISC_INIT_R
  32 /*
  33  * System Clock Setup
  34  */
  35 #define CONFIG_83XX_CLKIN               66000000
  36 #define CONFIG_SYS_CLK_FREQ             66000000
  37 #define CONFIG_83XX_PCICLK              66000000
  38
  39 /*
  40  * IMMR new address
  41  */
  42 #define CONFIG_SYS_IMMR         0xE0000000
  43
  44 /*
  45  * Bus Arbitration Configuration Register (ACR)
  46  */
  47 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  48 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  49 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  50 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  51
  52 /*
  53  * DDR Setup
  54  */
  55 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  56 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  57 #define CONFIG_SYS_SDRAM_BASE2  (CONFIG_SYS_SDRAM_BASE + 0x10000000) /* +256M */
  58
  59 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  60 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  61                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  62
  63 #define CFG_83XX_DDR_USES_CS0
  64
  65 /*
  66  * Manually set up DDR parameters
  67  */
  68 #define CONFIG_DDR_II
  69 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  70
  71 /*
  72  * The reserved memory
  73  */
  74 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
  75 #define CONFIG_SYS_FLASH_BASE           0xF0000000
  76
  77 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
  78 #define CONFIG_SYS_RAMBOOT
  79 #endif
  80
  81 /* Reserve 768 kB for Mon */
  82 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
  83
  84 /*
  85  * Initial RAM Base Address Setup
  86  */
  87 #define CONFIG_SYS_INIT_RAM_LOCK
  88 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
  89 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* End of used area in RAM */
  90 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
  91 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
  92                                                 GENERATED_GBL_DATA_SIZE)
  93
  94 /*
  95  * Init Local Bus Memory Controller:
  96  *
  97  * Bank Bus     Machine PortSz  Size  Device
  98  * ---- ---     ------- ------  -----  ------
  99  *  0   Local   GPCM    16 bit  256MB FLASH
 100  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 101  *
 102  */
 103 /*
 104  * FLASH on the Local Bus
 105  */
 106 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 107 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 108 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 109 #define CONFIG_SYS_FLASH_PROTECTION
 110 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 111
 112 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 113 #define CONFIG_SYS_LBLAWAR0_PRELIM      (LBLAWAR_EN | LBLAWAR_256MB)
 114
 115 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 116                                 BR_PS_16 | /* 16 bit port size */ \
 117                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 118                                 BR_V)
 119
 120 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 121                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 122                                 OR_GPCM_SCY_5 | \
 123                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 124
 125 #define CONFIG_SYS_MAX_FLASH_BANKS      1   /* max num of flash banks   */
 126 #define CONFIG_SYS_MAX_FLASH_SECT       512 /* max num of sects on one chip */
 127 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 128
 129 /*
 130  * PRIO1/PIGGY on the local bus CS1
 131  */
 132 /* Window base at flash base */
 133 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_KMBEC_FPGA_BASE
 134 #define CONFIG_SYS_LBLAWAR1_PRELIM      (LBLAWAR_EN | LBLAWAR_128MB)
 135
 136 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_KMBEC_FPGA_BASE | \
 137                                 BR_PS_8 | /* 8 bit port size */ \
 138                                 BR_MS_GPCM | /* MSEL = GPCM */ \
 139                                 BR_V)
 140 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_KMBEC_FPGA_SIZE) | \
 141                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 142                                 OR_GPCM_SCY_2 | \
 143                                 OR_GPCM_TRLX_SET | OR_GPCM_EAD)
 144
 145 /*
 146  * Serial Port
 147  */
 148 #define CONFIG_CONS_INDEX       1
 149 #define CONFIG_SYS_NS16550
 150 #define CONFIG_SYS_NS16550_SERIAL
 151 #define CONFIG_SYS_NS16550_REG_SIZE     1
 152 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 153
 154 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 155 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 156
 157 /* Pass open firmware flat tree */
 158 #define CONFIG_OF_LIBFDT
 159 #define CONFIG_OF_BOARD_SETUP
 160 #define CONFIG_OF_STDOUT_VIA_ALIAS
 161
 162 /*
 163  * QE UEC ethernet configuration
 164  */
 165 #define CONFIG_UEC_ETH
 166 #define CONFIG_ETHPRIME         "UEC0"
 167
 168 #if !defined(CONFIG_MPC8309)
 169 #define CONFIG_UEC_ETH1         /* GETH1 */
 170 #define UEC_VERBOSE_DEBUG       1
 171 #endif
 172
 173 #ifdef CONFIG_UEC_ETH1
 174 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 175 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII Mode */
 176 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 177 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 178 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 179 #define CONFIG_SYS_UEC1_INTERFACE_TYPE  PHY_INTERFACE_MODE_RMII
 180 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 181 #endif
 182
 183 /*
 184  * Environment
 185  */
 186
 187 #ifndef CONFIG_SYS_RAMBOOT
 188 #define CONFIG_ENV_IS_IN_FLASH
 189 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 190                                         CONFIG_SYS_MONITOR_LEN)
 191 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 192 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 193
 194 /* Address and size of Redundant Environment Sector     */
 195 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 196                                                 CONFIG_ENV_SECT_SIZE)
 197 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 198
 199 #else /* CFG_SYS_RAMBOOT */
 200 #define CONFIG_SYS_NO_FLASH             /* Flash is not usable now */
 201 #define CONFIG_ENV_IS_NOWHERE           /* Store ENV in memory only */
 202 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 203 #define CONFIG_ENV_SIZE         0x2000
 204 #endif /* CFG_SYS_RAMBOOT */
 205
 206 /* I2C */
 207 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 208 #define CONFIG_FSL_I2C
 209 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 210 #define CONFIG_SYS_I2C_SLAVE    0x7F
 211 #define CONFIG_SYS_I2C_OFFSET   0x3000
 212
 213 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
 214 #define CONFIG_DTT_LM75         /* ON Semi's LM75 */
 215 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses */
 216 #define CONFIG_SYS_DTT_MAX_TEMP 70
 217 #define CONFIG_SYS_DTT_LOW_TEMP -30
 218 #define CONFIG_SYS_DTT_HYSTERESIS       3
 219 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 220
 221 #if defined(CONFIG_CMD_NAND)
 222 #define CONFIG_NAND_KMETER1
 223 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 224 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_KMBEC_FPGA_BASE
 225 #endif
 226
 227 #if defined(CONFIG_PCI)
 228 #define CONFIG_CMD_PCI
 229 #endif
 230
 231 /*
 232  * For booting Linux, the board info and command line data
 233  * have to be in the first 8 MB of memory, since this is
 234  * the maximum mapped by the Linux kernel during initialization.
 235  */
 236 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 237
 238 /*
 239  * Core HID Setup
 240  */
 241 #define CONFIG_SYS_HID0_INIT            0x000000000
 242 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 243                                          HID0_ENABLE_INSTRUCTION_CACHE)
 244 #define CONFIG_SYS_HID2                 HID2_HBE
 245
 246 /*
 247  * MMU Setup
 248  */
 249
 250 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 251
 252 /* DDR: cache cacheable */
 253 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_RW | \
 254                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 255 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 256                                         BATU_VS | BATU_VP)
 257 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 258 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 259
 260 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 261 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_RW | \
 262                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 263 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS \
 264                                         | BATU_VP)
 265 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 266 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 267
 268 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 269 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 270                                 BATL_MEMCOHERENCE)
 271 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_KMBEC_FPGA_BASE | BATU_BL_128M | \
 272                                 BATU_VS | BATU_VP)
 273 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_KMBEC_FPGA_BASE | BATL_PP_RW | \
 274                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 275 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 276
 277 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 278 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 279                                         BATL_MEMCOHERENCE)
 280 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 281                                         BATU_VS | BATU_VP)
 282 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \
 283                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 284 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 285
 286 /* Stack in dcache: cacheable, no memory coherence */
 287 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW)
 288 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 289                                         BATU_VS | BATU_VP)
 290 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 291 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 292
 293 /*
 294  * Internal Definitions
 295  */
 296 #define BOOTFLASH_START 0xF0000000
 297
 298 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 299
 300 /*
 301  * Environment Configuration
 302  */
 303 #define CONFIG_ENV_OVERWRITE
 304 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 305 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 306 #endif
 307
 308 #ifndef CONFIG_KM_DEF_ARCH
 309 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 310 #endif
 311
 312 #define CONFIG_EXTRA_ENV_SETTINGS \
 313         CONFIG_KM_DEF_ENV                                               \
 314         CONFIG_KM_DEF_ARCH                                              \
 315         "EEprom_ivm=pca9547:70:9\0"                                     \
 316         "newenv="                                                       \
 317                 "prot off 0xF00C0000 +0x40000 && "                      \
 318                 "era 0xF00C0000 +0x40000\0"                             \
 319         "unlock=yes\0"                                                  \
 320         ""
 321
 322 #if defined(CONFIG_UEC_ETH)
 323 #define CONFIG_HAS_ETH0
 324 #endif
 325
 326 #endif /* __CONFIG_KM83XX_H */