include/configs/kmeter1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_QE               /* Has QE */
  27 #define CONFIG_MPC8360          /* MPC8360 CPU specific */
  28 #define CONFIG_KMETER1          /* KMETER1 board specific */
  29 #define CONFIG_HOSTNAME         kmeter1
  30
  31 #define CONFIG_SYS_TEXT_BASE    0xF0000000
  32
  33 /* include common defines/options for all Keymile boards */
  34 #include "keymile-common.h"
  35
  36 #define CONFIG_KM_UBI_PARTITION_NAME    "ubi0"
  37
  38 #define MTDIDS_DEFAULT          "nor0=boot"
  39 #define MTDPARTS_DEFAULT        \
  40         "mtdparts=boot:768k(u-boot),128k(env),128k(envred),"    \
  41         "-(" CONFIG_KM_UBI_PARTITION_NAME ")"
  42
  43 #define CONFIG_MISC_INIT_R
  44 /*
  45  * System Clock Setup
  46  */
  47 #define CONFIG_83XX_CLKIN               66000000
  48 #define CONFIG_SYS_CLK_FREQ             66000000
  49 #define CONFIG_83XX_PCICLK              66000000
  50
  51 /*
  52  * Hardware Reset Configuration Word
  53  */
  54 #define CONFIG_SYS_HRCW_LOW (\
  55         HRCWL_CSB_TO_CLKIN_4X1 | \
  56         HRCWL_CORE_TO_CSB_2X1 | \
  57         HRCWL_CE_PLL_VCO_DIV_2 | \
  58         HRCWL_CE_TO_PLL_1X6 )
  59
  60 #define CONFIG_SYS_HRCW_HIGH (\
  61         HRCWH_CORE_ENABLE | \
  62         HRCWH_FROM_0X00000100 | \
  63         HRCWH_BOOTSEQ_DISABLE | \
  64         HRCWH_SW_WATCHDOG_DISABLE | \
  65         HRCWH_ROM_LOC_LOCAL_16BIT | \
  66         HRCWH_BIG_ENDIAN | \
  67         HRCWH_LALE_EARLY | \
  68         HRCWH_LDP_CLEAR )
  69
  70 /*
  71  * System IO Config
  72  */
  73 #define CONFIG_SYS_SICRH                0x00000006
  74 #define CONFIG_SYS_SICRL                0x00000000
  75
  76 /*
  77  * IMMR new address
  78  */
  79 #define CONFIG_SYS_IMMR         0xE0000000
  80
  81 /*
  82  * Bus Arbitration Configuration Register (ACR)
  83  */
  84 #define CONFIG_SYS_ACR_PIPE_DEP 3       /* pipeline depth 4 transactions */
  85 #define CONFIG_SYS_ACR_RPTCNT   3       /* 4 consecutive transactions */
  86 #define CONFIG_SYS_ACR_APARK    0       /* park bus to master (below) */
  87 #define CONFIG_SYS_ACR_PARKM    3       /* parking master = QuiccEngine */
  88
  89 /*
  90  * DDR Setup
  91  */
  92 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  93 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  95 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  96                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  97
  98 #define CFG_83XX_DDR_USES_CS0
  99
 100 #undef CONFIG_DDR_ECC
 101
 102 /*
 103  * DDRCDR - DDR Control Driver Register
 104  */
 105
 106 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
 107
 108 /*
 109  * Manually set up DDR parameters
 110  */
 111 #define CONFIG_DDR_II
 112 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
 113 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 114 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 115                                         CSCONFIG_ROW_BIT_13 | \
 116                                         CSCONFIG_COL_BIT_10 | \
 117                                         CSCONFIG_ODT_WR_ACS)
 118
 119 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 120                                          SDRAM_CFG_SREN)
 121 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 122 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 123 #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 124                                  (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 125
 126 #define CONFIG_SYS_DDRCDR               0x40000001
 127 #define CONFIG_SYS_DDR_MODE             0x47860452
 128 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 129
 130 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 131                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 132                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 133                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 134                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 135                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 136                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 137                                  (0 << TIMING_CFG0_RWT_SHIFT))
 138
 139 #define CONFIG_SYS_DDR_TIMING_1 ((TIMING_CFG1_CASLAT_50) | \
 140                                  (2 << TIMING_CFG1_WRTORD_SHIFT) | \
 141                                  (2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 142                                  (3 << TIMING_CFG1_WRREC_SHIFT) | \
 143                                  (7 << TIMING_CFG1_REFREC_SHIFT) | \
 144                                  (3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 145                                  (8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 146                                  (3 << TIMING_CFG1_PRETOACT_SHIFT))
 147
 148 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 149                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 150                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 151                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 152                                  (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 153                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 154                                  (5 << TIMING_CFG2_CPO_SHIFT))
 155
 156 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 157
 158 /*
 159  * The reserved memory
 160  */
 161 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
 162 #define CONFIG_SYS_FLASH_BASE           0xF0000000
 163 #define CONFIG_SYS_PIGGY_BASE           0xE8000000
 164 #define CONFIG_SYS_PIGGY_SIZE           128
 165 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 166 #define CONFIG_SYS_PAXE_SIZE            512
 167
 168 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 169 #define CONFIG_SYS_RAMBOOT
 170 #else
 171 #undef  CONFIG_SYS_RAMBOOT
 172 #endif
 173
 174 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve for Mon */
 175
 176 /*
 177  * Initial RAM Base Address Setup
 178  */
 179 #define CONFIG_SYS_INIT_RAM_LOCK        1
 180 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 181 #define CONFIG_SYS_INIT_RAM_SIZE        0x1000 /* Size of used area in RAM */
 182 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 183                                         GENERATED_GBL_DATA_SIZE)
 184
 185 /*
 186  * Local Bus Configuration & Clock Setup
 187  */
 188 #define CONFIG_SYS_LCRR_DBYP    LCRR_DBYP
 189 #define CONFIG_SYS_LCRR_EADC    LCRR_EADC_2
 190 #define CONFIG_SYS_LCRR_CLKDIV  LCRR_CLKDIV_4
 191
 192 /*
 193  * Init Local Bus Memory Controller:
 194  *
 195  * Bank Bus     Machine PortSz  Size  Device
 196  * ---- ---     ------- ------  -----  ------
 197  *  0   Local   GPCM    16 bit  256MB FLASH
 198  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 199  *  3   Local   GPCM     8 bit  512MB PAXE
 200  *
 201  */
 202 /*
 203  * FLASH on the Local Bus
 204  */
 205 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 206 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 207 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 208 #define CONFIG_SYS_FLASH_PROTECTION     1
 209 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 210
 211 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE
 212 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
 213
 214 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 215                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 216                                 BR_V)
 217
 218 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 219                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 220                                 OR_GPCM_SCY_5 | \
 221                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 222
 223 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks */
 224 /* max num of sects on one chip */
 225 #define CONFIG_SYS_MAX_FLASH_SECT       512
 226 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
 227
 228 #undef  CONFIG_SYS_FLASH_CHECKSUM
 229
 230 /*
 231  * PRIO1/PIGGY on the local bus CS1
 232  */
 233 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE
 234 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001A /* 128MB window size */
 235
 236 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
 237                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 238                                 BR_V)
 239 #define CONFIG_SYS_OR1_PRELIM   (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | \
 240                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 241                                 OR_GPCM_SCY_2 | \
 242                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 243
 244 /*
 245  * PAXE on the local bus CS3
 246  */
 247 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE
 248 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 249
 250 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 251                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 252                                 BR_V)
 253 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 254                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 255                                 OR_GPCM_SCY_2 | \
 256                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 257
 258 /*
 259  * Serial Port
 260  */
 261 #define CONFIG_CONS_INDEX       1
 262 #define CONFIG_SYS_NS16550
 263 #define CONFIG_SYS_NS16550_SERIAL
 264 #define CONFIG_SYS_NS16550_REG_SIZE     1
 265 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 266
 267 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 268 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 269
 270 /* Pass open firmware flat tree */
 271 #define CONFIG_OF_LIBFDT
 272 #define CONFIG_OF_BOARD_SETUP
 273 #define CONFIG_OF_STDOUT_VIA_ALIAS
 274
 275 /*
 276  * General PCI
 277  * Addresses are mapped 1-1.
 278  */
 279 #undef CONFIG_PCI               /* No PCI */
 280
 281 #ifndef CONFIG_NET_MULTI
 282 #define CONFIG_NET_MULTI
 283 #endif
 284 /*
 285  * QE UEC ethernet configuration
 286  */
 287 #define CONFIG_UEC_ETH
 288 #define CONFIG_ETHPRIME         "UEC0"
 289
 290 #define CONFIG_UEC_ETH1         /* GETH1 */
 291 #define UEC_VERBOSE_DEBUG       1
 292
 293 #ifdef CONFIG_UEC_ETH1
 294 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 295 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE /* not used in RMII */
 296 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 297 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 298 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 299 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 300 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 301 #endif
 302
 303 /*
 304  * Environment
 305  */
 306
 307 #ifndef CONFIG_SYS_RAMBOOT
 308 #define CONFIG_ENV_IS_IN_FLASH  1
 309 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + \
 310                                 CONFIG_SYS_MONITOR_LEN)
 311 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 312 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 313
 314 /* Address and size of Redundant Environment Sector     */
 315 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + \
 316                                         CONFIG_ENV_SECT_SIZE)
 317 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 318
 319 #else /* CFG_RAMBOOT */
 320 #define CONFIG_SYS_NO_FLASH     /* Flash is not usable now */
 321 #define CONFIG_ENV_IS_NOWHERE   /* Store ENV in memory only */
 322 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 323 #define CONFIG_ENV_SIZE         0x2000
 324 #endif /* CFG_RAMBOOT */
 325
 326 /* I2C */
 327 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 328 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 329 #define CONFIG_FSL_I2C
 330 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 331 #define CONFIG_SYS_I2C_SLAVE    0x7F
 332 #define CONFIG_SYS_I2C_OFFSET   0x3000
 333 #define CONFIG_I2C_MULTI_BUS    1
 334 #define CONFIG_I2C_MUX          1
 335
 336 /* EEprom support */
 337 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 338
 339 /* I2C SYSMON (LM75, AD7414 is almost compatible) */
 340 #define CONFIG_DTT_LM75         /* ON Semi's LM75 */
 341 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses */
 342 #define CONFIG_SYS_DTT_MAX_TEMP 70
 343 #define CONFIG_SYS_DTT_LOW_TEMP -30
 344 #define CONFIG_SYS_DTT_HYSTERESIS       3
 345 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 346
 347 #if defined(CONFIG_CMD_NAND)
 348 #define CONFIG_NAND_KMETER1
 349 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 350 #define CONFIG_SYS_NAND_BASE            CONFIG_SYS_PIGGY_BASE
 351 #endif
 352
 353 #if defined(CONFIG_PCI)
 354 #define CONFIG_CMD_PCI
 355 #endif
 356
 357 #if defined(CFG_RAMBOOT)
 358 #undef CONFIG_CMD_SAVEENV
 359 #undef CONFIG_CMD_LOADS
 360 #endif
 361
 362 /*
 363  * For booting Linux, the board info and command line data
 364  * have to be in the first 256 MB of memory, since this is
 365  * the maximum mapped by the Linux kernel during initialization.
 366  */
 367 #define CONFIG_SYS_BOOTMAPSZ            (256 << 20)
 368
 369 /*
 370  * Core HID Setup
 371  */
 372 #define CONFIG_SYS_HID0_INIT            0x000000000
 373 #define CONFIG_SYS_HID0_FINAL           (HID0_ENABLE_MACHINE_CHECK | \
 374                                          HID0_ENABLE_INSTRUCTION_CACHE)
 375 #define CONFIG_SYS_HID2                 HID2_HBE
 376
 377 /*
 378  * MMU Setup
 379  */
 380
 381 #define CONFIG_HIGH_BATS        /* High BATs supported */
 382
 383 /* DDR: cache cacheable */
 384 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 385                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 386 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | \
 387                                 BATU_VS | BATU_VP)
 388 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 389 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 390
 391 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 392 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 393                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 394 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | \
 395                                 BATU_VP)
 396 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 397 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 398
 399 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 400 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 401                                 BATL_MEMCOHERENCE)
 402 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | \
 403                                 BATU_VS | BATU_VP)
 404 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 405                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 406 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 407
 408 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 409 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 410                                 BATL_MEMCOHERENCE)
 411 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | \
 412                                 BATU_VS | BATU_VP)
 413 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 414                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 415 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 416
 417 /* Stack in dcache: cacheable, no memory coherence */
 418 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 419 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | \
 420                                 BATU_VS | BATU_VP)
 421 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 422 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 423
 424 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 425 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 426                                 BATL_MEMCOHERENCE)
 427 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | \
 428                                 BATU_VS | BATU_VP)
 429 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 430                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 431 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 432
 433 #ifdef CONFIG_PCI
 434 /* PCI MEM space: cacheable */
 435 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 436 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 437 #define CFG_DBAT6L      CFG_IBAT6L
 438 #define CFG_DBAT6U      CFG_IBAT6U
 439 /* PCI MMIO space: cache-inhibit and guarded */
 440 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 441                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 442 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 443 #define CFG_DBAT7L      CFG_IBAT7L
 444 #define CFG_DBAT7U      CFG_IBAT7U
 445 #else /* CONFIG_PCI */
 446 #define CONFIG_SYS_IBAT6L       (0)
 447 #define CONFIG_SYS_IBAT6U       (0)
 448 #define CONFIG_SYS_IBAT7L       (0)
 449 #define CONFIG_SYS_IBAT7U       (0)
 450 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 451 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 452 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 453 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 454 #endif /* CONFIG_PCI */
 455
 456 #define BOOTFLASH_START F0000000
 457
 458 #define CONFIG_PRAM     512     /* protected RAM [KBytes] */
 459
 460 /*
 461  * Environment Configuration
 462  */
 463 #define CONFIG_ENV_OVERWRITE
 464 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 465 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 466 #endif
 467
 468 #define CONFIG_EXTRA_ENV_SETTINGS \
 469        CONFIG_KM_DEF_ENV                                                \
 470         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 471         "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 472         "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"                     \
 473         "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"              \
 474         "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"                      \
 475         "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"                \
 476         "unlock=yes\0"                                                  \
 477         "fdt_addr=F0080000\0"                                           \
 478         "kernel_addr=F00a0000\0"                                        \
 479         "ramdisk_addr=F03a0000\0"                                       \
 480         "ramdisk_addr_r=F10000\0"                                       \
 481         "EEprom_ivm=pca9547:70:9\0"                                     \
 482         "dtt_bus=pca9547:70:a\0"                                        \
 483         "mtdids=nor0=app \0"                                            \
 484         "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
 485    ""
 486
 487 #if defined(CONFIG_UEC_ETH)
 488 #define CONFIG_HAS_ETH0
 489 #endif
 490
 491 #endif /* __CONFIG_H */