include/configs/kmeter1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_E300             1 /* E300 family */
  27 #define CONFIG_QE               1 /* Has QE */
  28 #define CONFIG_MPC83XX          1 /* MPC83XX family */
  29 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  30 #define CONFIG_KMETER1          1 /* KMETER1 board specific */
  31
  32 /*
  33  * System Clock Setup
  34  */
  35 #define CONFIG_83XX_CLKIN               66000000
  36 #define CONFIG_SYS_CLK_FREQ             66000000
  37 #define CONFIG_83XX_PCICLK              66000000
  38
  39 /*
  40  * Hardware Reset Configuration Word
  41  */
  42 #define CONFIG_SYS_HRCW_LOW (\
  43         HRCWL_CSB_TO_CLKIN_4X1 | \
  44         HRCWL_CORE_TO_CSB_2X1 | \
  45         HRCWL_CE_PLL_VCO_DIV_2 | \
  46         HRCWL_CE_TO_PLL_1X6 )
  47
  48 #define CONFIG_SYS_HRCW_HIGH (\
  49         HRCWH_CORE_ENABLE | \
  50         HRCWH_FROM_0X00000100 | \
  51         HRCWH_BOOTSEQ_NORMAL | \
  52         HRCWH_SW_WATCHDOG_DISABLE | \
  53         HRCWH_ROM_LOC_LOCAL_16BIT | \
  54         HRCWH_BIG_ENDIAN | \
  55         HRCWH_LDP_CLEAR )
  56
  57 /*
  58  * System IO Config
  59  */
  60 #define CONFIG_SYS_SICRH                0x00000006
  61 #define CONFIG_SYS_SICRL                0x00000000
  62
  63 #define CONFIG_BOARD_EARLY_INIT_R
  64
  65 /*
  66  * IMMR new address
  67  */
  68 #define CONFIG_SYS_IMMR         0xE0000000
  69
  70 /*
  71  * DDR Setup
  72  */
  73 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  74 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  75 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  76 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  77                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  78
  79 #define CFG_83XX_DDR_USES_CS0
  80
  81 #undef CONFIG_DDR_ECC
  82
  83 /*
  84  * DDRCDR - DDR Control Driver Register
  85  */
  86
  87 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
  88
  89 /*
  90  * Manually set up DDR parameters
  91  */
  92 #define CONFIG_DDR_II
  93 #define CONFIG_SYS_DDR_SIZE             256 /* MB */
  94 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000000f
  95 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
  96                                          CSCONFIG_ROW_BIT_13 | \
  97                                          CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
  98
  99 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 100                                          SDRAM_CFG_SREN)
 101 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 102 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 103 #define CONFIG_SYS_DDR_INTERVAL ((0x100 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 104                                  (0x406 << SDRAM_INTERVAL_REFINT_SHIFT))
 105
 106 #define CONFIG_SYS_DDR_MODE             0x04440242
 107 #define CONFIG_SYS_DDR_MODE2            0x00800000
 108
 109 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 110                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 111                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 112                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 113                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 114                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 115                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 116                                  (0 << TIMING_CFG0_RWT_SHIFT))
 117
 118 #define CONFIG_SYS_DDR_TIMING_1 ((      TIMING_CFG1_CASLAT_40) | \
 119                                  ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 120                                  ( 1 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 121                                  ( 2 << TIMING_CFG1_WRREC_SHIFT) | \
 122                                  ( 2 << TIMING_CFG1_REFREC_SHIFT) | \
 123                                  ( 2 << TIMING_CFG1_ACTTORW_SHIFT) | \
 124                                  ( 6 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 125                                  ( 2 << TIMING_CFG1_PRETOACT_SHIFT))
 126
 127 #define CONFIG_SYS_DDR_TIMING_2 ((5 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 128                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 129                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 130                                  (1 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 131                                  (3 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 132                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 133                                  (4 << TIMING_CFG2_CPO_SHIFT))
 134
 135 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 136
 137 /*
 138  * Memory test
 139  */
 140 #define CONFIG_SYS_ALT_MEMTEST          /* memory test, takes time */
 141 #define CONFIG_SYS_MEMTEST_START        0x00100000 /* memtest region */
 142 #define CONFIG_SYS_MEMTEST_END          0x00F00000
 143
 144 /*
 145  * The reserved memory
 146  */
 147 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 148 #define CONFIG_SYS_FLASH_BASE           0xF0000000
 149 #define CONFIG_SYS_FLASH_BASE_1         0xF2000000
 150 #define CONFIG_SYS_PIGGY_BASE           0x80000000
 151 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 152 #define CONFIG_SYS_PAXE_SIZE            256
 153
 154 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 155 #define CONFIG_SYS_RAMBOOT
 156 #else
 157 #undef  CONFIG_SYS_RAMBOOT
 158 #endif
 159
 160 #define CONFIG_SYS_MONITOR_LEN          (256 * 1024) /* Reserve 256 kB for Mon */
 161 #define CONFIG_SYS_MALLOC_LEN           (128 * 1024) /* Reserved for malloc */
 162
 163 /*
 164  * Initial RAM Base Address Setup
 165  */
 166 #define CONFIG_SYS_INIT_RAM_LOCK        1
 167 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 168 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 169 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 170 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 171
 172 /*
 173  * Local Bus Configuration & Clock Setup
 174  */
 175 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
 176
 177 /*
 178  * Init Local Bus Memory Controller:
 179  *
 180  * Bank Bus     Machine PortSz  Size  Device
 181  * ---- ---     ------- ------  -----  ------
 182  *  0   Local   GPCM    16 bit  256MB FLASH
 183  *  1   Local   GPCM     8 bit  256KB GPIO/PIGGY
 184  *  3   Local   GPCM     8 bit  256MB PAXE
 185  *
 186  */
 187 /*
 188  * FLASH on the Local Bus
 189  */
 190 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 191 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 192 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 193 #define CONFIG_SYS_FLASH_PROTECTION     1
 194 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 195
 196 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 197 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
 198
 199 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 200                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 201                                 BR_V)
 202
 203 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 204                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 205                                 OR_GPCM_SCY_5 | \
 206                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 207
 208 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks       */
 209 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 210 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
 211
 212 #undef  CONFIG_SYS_FLASH_CHECKSUM
 213
 214 /*
 215  * PRIO1/PIGGY on the local bus CS1
 216  */
 217 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
 218 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x80000011 /* 256KB window size */
 219
 220 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
 221                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 222                                 BR_V)
 223 #define CONFIG_SYS_OR1_PRELIM           (0xfffc0000 | /* 256KB */ \
 224                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 225                                 OR_GPCM_SCY_2 | \
 226                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 227
 228 /*
 229  * PAXE on the local bus CS3
 230  */
 231 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE /* Window base at flash base */
 232 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001b /* 256MB window size */
 233
 234 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 235                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 236                                 BR_V)
 237 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 238                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 239                                 OR_GPCM_SCY_2 | \
 240                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 241
 242 /*
 243  * Serial Port
 244  */
 245 #define CONFIG_CONS_INDEX       1
 246 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 247 #define CONFIG_SYS_NS16550
 248 #define CONFIG_SYS_NS16550_SERIAL
 249 #define CONFIG_SYS_NS16550_REG_SIZE     1
 250 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 251
 252 #define CONFIG_SYS_BAUDRATE_TABLE       \
 253         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200,}
 254
 255 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 256 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 257
 258 /* Pass open firmware flat tree */
 259 #define CONFIG_OF_LIBFDT        1
 260 #define CONFIG_OF_BOARD_SETUP   1
 261 #define CONFIG_OF_STDOUT_VIA_ALIAS
 262
 263 /*
 264  * General PCI
 265  * Addresses are mapped 1-1.
 266  */
 267 #undef CONFIG_PCI               /* No PCI */
 268
 269 #ifndef CONFIG_NET_MULTI
 270 #define CONFIG_NET_MULTI        1
 271 #endif
 272
 273 /*
 274  * QE UEC ethernet configuration
 275  */
 276 #define CONFIG_UEC_ETH
 277 #define CONFIG_ETHPRIME         "FSL UEC0"
 278
 279 #define CONFIG_UEC_ETH1         /* GETH1 */
 280 #define UEC_VERBOSE_DEBUG       1
 281
 282 #ifdef CONFIG_UEC_ETH1
 283 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 284 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE     /* not used in RMII Mode */
 285 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 286 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 287 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 288 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
 289 #endif
 290
 291 /*
 292  * Environment
 293  */
 294
 295 #ifndef CONFIG_SYS_RAMBOOT
 296 #define CONFIG_ENV_IS_IN_FLASH  1
 297 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 298 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 299 #define CONFIG_ENV_SIZE         0x20000
 300 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 301
 302 /* Address and size of Redundant Environment Sector     */
 303 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 304 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 305
 306 #else /* CFG_RAMBOOT */
 307 #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 308 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 309 #define CONFIG_ENV_ADDR         (CFG_MONITOR_BASE - 0x1000)
 310 #define CONFIG_ENV_SIZE         0x2000
 311 #endif /* CFG_RAMBOOT */
 312
 313 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 314 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 315
 316 /*
 317  * How to get access to the slot ID.  Put this here to make it easy
 318  * to modify in a centralized location.  This is used in the HDLC
 319  * driver to set the MAC.
 320 */
 321 #define CONFIG_SYS_SLOT_ID_BASE         CONFIG_SYS_PIGGY_BASE
 322 #define CONFIG_SYS_SLOT_ID_OFF          (0x07)  /* register offset */
 323 #define CONFIG_SYS_SLOT_ID_MASK         (0x3f)  /* mask for slot ID bits */
 324
 325 /*
 326  * BOOTP options
 327  */
 328 #define CONFIG_BOOTP_BOOTFILESIZE
 329 #define CONFIG_BOOTP_BOOTPATH
 330 #define CONFIG_BOOTP_GATEWAY
 331 #define CONFIG_BOOTP_HOSTNAME
 332
 333 /*
 334  * Command line configuration.
 335  */
 336 #include <config_cmd_default.h>
 337
 338 #define CONFIG_CMD_ASKENV
 339 #define CONFIG_CMD_DHCP
 340 #define CONFIG_CMD_NFS
 341 #define CONFIG_CMD_MII
 342 #define CONFIG_CMD_PING
 343
 344 #if defined(CONFIG_PCI)
 345 #define CONFIG_CMD_PCI
 346 #endif
 347
 348 #if defined(CFG_RAMBOOT)
 349 #undef CONFIG_CMD_ENV
 350 #undef CONFIG_CMD_LOADS
 351 #endif
 352
 353 #undef CONFIG_WATCHDOG          /* watchdog disabled */
 354
 355 /*
 356  * Miscellaneous configurable options
 357  */
 358 #define CONFIG_SYS_HUSH_PARSER
 359 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 360 #define CONFIG_SYS_LONGHELP                     /* undef to save memory     */
 361 #define CONFIG_SYS_LOAD_ADDR            0x200000 /* default load address */
 362 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt   */
 363 #if defined(CONFIG_CMD_KGDB)
 364 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size  */
 365 #else
 366 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size  */
 367 #endif
 368 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 369 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 370 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 371 #define CONFIG_CMDLINE_EDITING  1       /* add command line history */
 372
 373 #define CONFIG_SYS_HZ                   1000
 374
 375 /*
 376  * For booting Linux, the board info and command line data
 377  * have to be in the first 8 MB of memory, since this is
 378  * the maximum mapped by the Linux kernel during initialization.
 379  */
 380 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 381
 382 /*
 383  * Core HID Setup
 384  */
 385 #define CONFIG_SYS_HID0_INIT            0x000000000
 386 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 387 #define CONFIG_SYS_HID2                 HID2_HBE
 388
 389 /*
 390  * MMU Setup
 391  */
 392
 393 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 394
 395 /* DDR: cache cacheable */
 396 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 397                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 398 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 399 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 400 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 401
 402 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 403 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 404                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 405 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 406 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 407 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 408
 409 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 410 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 411 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
 412 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 413                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 414 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 415
 416 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 417 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 418 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 419 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 420                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 421 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 422
 423 /* Stack in dcache: cacheable, no memory coherence */
 424 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 425 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 426 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 427 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 428
 429 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 430 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 431 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256K | BATU_VS | BATU_VP)
 432 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 433                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 434 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 435
 436 #ifdef CONFIG_PCI
 437 /* PCI MEM space: cacheable */
 438 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 439 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 440 #define CFG_DBAT6L      CFG_IBAT6L
 441 #define CFG_DBAT6U      CFG_IBAT6U
 442 /* PCI MMIO space: cache-inhibit and guarded */
 443 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 444                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 445 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 446 #define CFG_DBAT7L      CFG_IBAT7L
 447 #define CFG_DBAT7U      CFG_IBAT7U
 448 #else /* CONFIG_PCI */
 449 #define CONFIG_SYS_IBAT6L       (0)
 450 #define CONFIG_SYS_IBAT6U       (0)
 451 #define CONFIG_SYS_IBAT7L       (0)
 452 #define CONFIG_SYS_IBAT7U       (0)
 453 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 454 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 455 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 456 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 457 #endif /* CONFIG_PCI */
 458
 459 /*
 460  * Internal Definitions
 461  *
 462  * Boot Flags
 463  */
 464 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 465 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 466
 467 #if defined(CONFIG_CMD_KGDB)
 468 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 469 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 470 #endif
 471
 472 /*
 473  * Environment Configuration
 474  */
 475 #define CONFIG_ENV_OVERWRITE
 476
 477 #if defined(CONFIG_UEC_ETH)
 478 #define CONFIG_HAS_ETH0
 479 #endif
 480
 481 #define CONFIG_BAUDRATE 115200
 482
 483 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 484 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 485
 486 #define CONFIG_EXTRA_ENV_SETTINGS \
 487         "netdev=eth0\0"                                                 \
 488         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 489         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 490                 "nfsroot=${serverip}:${rootpath}\0"                     \
 491         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 492         "addip=setenv bootargs ${bootargs} "                            \
 493                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 494                 ":${hostname}:${netdev}:off panic=1\0"                  \
 495         "addtty=setenv bootargs ${bootargs}"                            \
 496                 " console=ttyS0,${baudrate}\0"                          \
 497         "fdt_addr=f0080000\0"                                           \
 498         "kernel_addr=f00a0000\0"                                        \
 499         "ramdisk_addr=f03a0000\0"                                       \
 500         "kernel_addr_r=400000\0"                                        \
 501         "fdt_addr_r=800000\0"                                           \
 502         "ramdisk_addr_r=810000\0"                                       \
 503         "flash_self=run ramargs addip addtty;"                          \
 504                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 505         "flash_nfs=run nfsargs addip addtty;"                           \
 506                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 507         "net_nfs=tftp ${kernel_addr_r} ${boot_file}; "                  \
 508                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 509                 "run nfsargs addip addtty;"                             \
 510                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 511         "fdt_file=/tftpboot/kmeter1/kmeter1.dtb\0"                      \
 512         "boot_file=/tftpboot/kmeter1/uImage\0"                          \
 513         "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"                     \
 514         "u-boot=/tftpboot/kmeter1/u-boot.bin\0"                         \
 515         "loadaddr=" MK_STR(CONFIG_SYS_LOAD_ADDR) "\0"                   \
 516         "load=tftp $loadaddr ${u-boot}\0"                               \
 517         "update=protect off " MK_STR(TEXT_BASE) " +$filesize;"          \
 518                 "erase " MK_STR(TEXT_BASE) " +$filesize;"               \
 519                 "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;"       \
 520                 "protect on " MK_STR(TEXT_BASE) " +$filesize;"          \
 521                 "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize;"      \
 522                 "setenv filesize;saveenv\0"                             \
 523         "upd=run load update\0"                                         \
 524         "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"              \
 525         "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"                      \
 526         "loadkernel=tftp ${kernel_addr_r} ${boot_file}\0"               \
 527         "unlock=yes\0"                                                  \
 528    ""
 529
 530 #define CONFIG_BOOTCOMMAND "run net_nfs"
 531
 532 #endif /* __CONFIG_H */