include/configs/kmeter1.h

   1 /*
   2  * Copyright (C) 2006 Freescale Semiconductor, Inc.
   3  *                    Dave Liu <daveliu@freescale.com>
   4  *
   5  * Copyright (C) 2007 Logic Product Development, Inc.
   6  *                    Peter Barada <peterb@logicpd.com>
   7  *
   8  * Copyright (C) 2007 MontaVista Software, Inc.
   9  *                    Anton Vorontsov <avorontsov@ru.mvista.com>
  10  *
  11  * (C) Copyright 2008
  12  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  */
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*
  24  * High Level Configuration Options
  25  */
  26 #define CONFIG_E300             1 /* E300 family */
  27 #define CONFIG_QE               1 /* Has QE */
  28 #define CONFIG_MPC83xx          1 /* MPC83xx family */
  29 #define CONFIG_MPC8360          1 /* MPC8360 CPU specific */
  30 #define CONFIG_KMETER1          1 /* KMETER1 board specific */
  31 #define CONFIG_HOSTNAME         kmeter1
  32
  33 /* include common defines/options for all Keymile boards */
  34 #include "keymile-common.h"
  35
  36 #undef CONFIG_SYS_I2C_INIT_BOARD
  37 #define CONFIG_MISC_INIT_R      1
  38 /*
  39  * System Clock Setup
  40  */
  41 #define CONFIG_83XX_CLKIN               66000000
  42 #define CONFIG_SYS_CLK_FREQ             66000000
  43 #define CONFIG_83XX_PCICLK              66000000
  44
  45 /*
  46  * Hardware Reset Configuration Word
  47  */
  48 #define CONFIG_SYS_HRCW_LOW (\
  49         HRCWL_CSB_TO_CLKIN_4X1 | \
  50         HRCWL_CORE_TO_CSB_2X1 | \
  51         HRCWL_CE_PLL_VCO_DIV_2 | \
  52         HRCWL_CE_TO_PLL_1X6 )
  53
  54 #define CONFIG_SYS_HRCW_HIGH (\
  55         HRCWH_CORE_ENABLE | \
  56         HRCWH_FROM_0X00000100 | \
  57         HRCWH_BOOTSEQ_DISABLE | \
  58         HRCWH_SW_WATCHDOG_DISABLE | \
  59         HRCWH_ROM_LOC_LOCAL_16BIT | \
  60         HRCWH_BIG_ENDIAN | \
  61         HRCWH_LALE_EARLY | \
  62         HRCWH_LDP_CLEAR )
  63
  64 /*
  65  * System IO Config
  66  */
  67 #define CONFIG_SYS_SICRH                0x00000006
  68 #define CONFIG_SYS_SICRL                0x00000000
  69
  70 /*
  71  * IMMR new address
  72  */
  73 #define CONFIG_SYS_IMMR         0xE0000000
  74
  75 /*
  76  * DDR Setup
  77  */
  78 #define CONFIG_SYS_DDR_BASE             0x00000000 /* DDR is system memory */
  79 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  80 #define CONFIG_SYS_DDR_SDRAM_BASE       CONFIG_SYS_DDR_BASE
  81 #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL   (DDR_SDRAM_CLK_CNTL_SS_EN | \
  82                                         DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
  83
  84 #define CFG_83XX_DDR_USES_CS0
  85
  86 #undef CONFIG_DDR_ECC
  87
  88 /*
  89  * DDRCDR - DDR Control Driver Register
  90  */
  91
  92 #undef CONFIG_SPD_EEPROM        /* Do not use SPD EEPROM for DDR setup */
  93
  94 /*
  95  * Manually set up DDR parameters
  96  */
  97 #define CONFIG_DDR_II
  98 #define CONFIG_SYS_DDR_SIZE             2048 /* MB */
  99 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000007f
 100 #define CONFIG_SYS_DDR_CS0_CONFIG       (CSCONFIG_EN | CSCONFIG_AP | \
 101                                          CSCONFIG_ROW_BIT_13 | \
 102                                          CSCONFIG_COL_BIT_10 | CSCONFIG_ODT_WR_ACS)
 103
 104 #define CONFIG_SYS_DDR_SDRAM_CFG        (SDRAM_CFG_SDRAM_TYPE_DDR2 | \
 105                                          SDRAM_CFG_SREN)
 106 #define CONFIG_SYS_DDR_SDRAM_CFG2       0x00401000
 107 #define CONFIG_SYS_DDR_CLK_CNTL (DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05)
 108 #define CONFIG_SYS_DDR_INTERVAL ((0x080 << SDRAM_INTERVAL_BSTOPRE_SHIFT) | \
 109                                  (0x3cf << SDRAM_INTERVAL_REFINT_SHIFT))
 110
 111 #define CONFIG_SYS_DDRCDR               0x40000001
 112 #define CONFIG_SYS_DDR_MODE             0x47860452
 113 #define CONFIG_SYS_DDR_MODE2            0x8080c000
 114
 115 #define CONFIG_SYS_DDR_TIMING_0 ((2 << TIMING_CFG0_MRS_CYC_SHIFT) | \
 116                                  (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) | \
 117                                  (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) | \
 118                                  (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) | \
 119                                  (0 << TIMING_CFG0_WWT_SHIFT) | \
 120                                  (0 << TIMING_CFG0_RRT_SHIFT) | \
 121                                  (0 << TIMING_CFG0_WRT_SHIFT) | \
 122                                  (0 << TIMING_CFG0_RWT_SHIFT))
 123
 124 #define CONFIG_SYS_DDR_TIMING_1 ((      TIMING_CFG1_CASLAT_50) | \
 125                                  ( 2 << TIMING_CFG1_WRTORD_SHIFT) | \
 126                                  ( 2 << TIMING_CFG1_ACTTOACT_SHIFT) | \
 127                                  ( 3 << TIMING_CFG1_WRREC_SHIFT) | \
 128                                  ( 7 << TIMING_CFG1_REFREC_SHIFT) | \
 129                                  ( 3 << TIMING_CFG1_ACTTORW_SHIFT) | \
 130                                  ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT) | \
 131                                  ( 3 << TIMING_CFG1_PRETOACT_SHIFT))
 132
 133 #define CONFIG_SYS_DDR_TIMING_2 ((8 << TIMING_CFG2_FOUR_ACT_SHIFT) | \
 134                                  (3 << TIMING_CFG2_CKE_PLS_SHIFT) | \
 135                                  (2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT) | \
 136                                  (2 << TIMING_CFG2_RD_TO_PRE_SHIFT) | \
 137                                  (4 << TIMING_CFG2_WR_LAT_DELAY_SHIFT) | \
 138                                  (0 << TIMING_CFG2_ADD_LAT_SHIFT) | \
 139                                  (5 << TIMING_CFG2_CPO_SHIFT))
 140
 141 #define CONFIG_SYS_DDR_TIMING_3 0x00000000
 142
 143 /*
 144  * The reserved memory
 145  */
 146 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
 147 #define CONFIG_SYS_FLASH_BASE           0xF0000000
 148 #define CONFIG_SYS_FLASH_BASE_1         0xF2000000
 149 #define CONFIG_SYS_PIGGY_BASE           0xE8000000
 150 #define CONFIG_SYS_PIGGY_SIZE           128
 151 #define CONFIG_SYS_PAXE_BASE            0xA0000000
 152 #define CONFIG_SYS_PAXE_SIZE            512
 153
 154 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 155 #define CONFIG_SYS_RAMBOOT
 156 #else
 157 #undef  CONFIG_SYS_RAMBOOT
 158 #endif
 159
 160 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kB for Mon */
 161
 162 /*
 163  * Initial RAM Base Address Setup
 164  */
 165 #define CONFIG_SYS_INIT_RAM_LOCK        1
 166 #define CONFIG_SYS_INIT_RAM_ADDR        0xE6000000 /* Initial RAM address */
 167 #define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM */
 168 #define CONFIG_SYS_GBL_DATA_SIZE        0x100 /* num bytes initial data */
 169 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 170
 171 /*
 172  * Local Bus Configuration & Clock Setup
 173  */
 174 #define CONFIG_SYS_LCRR         (LCRR_DBYP | LCRR_EADC_2 | LCRR_CLKDIV_4)
 175
 176 /*
 177  * Init Local Bus Memory Controller:
 178  *
 179  * Bank Bus     Machine PortSz  Size  Device
 180  * ---- ---     ------- ------  -----  ------
 181  *  0   Local   GPCM    16 bit  256MB FLASH
 182  *  1   Local   GPCM     8 bit  128MB GPIO/PIGGY
 183  *  3   Local   GPCM     8 bit  512MB PAXE
 184  *
 185  */
 186 /*
 187  * FLASH on the Local Bus
 188  */
 189 #define CONFIG_SYS_FLASH_CFI            /* use the Common Flash Interface */
 190 #define CONFIG_FLASH_CFI_DRIVER         /* use the CFI driver */
 191 #define CONFIG_SYS_FLASH_SIZE           256 /* max FLASH size is 256M */
 192 #define CONFIG_SYS_FLASH_PROTECTION     1
 193 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE       1
 194
 195 #define CONFIG_SYS_LBLAWBAR0_PRELIM     CONFIG_SYS_FLASH_BASE /* Window base at flash base */
 196 #define CONFIG_SYS_LBLAWAR0_PRELIM      0x8000001b /* 256MB window size */
 197
 198 #define CONFIG_SYS_BR0_PRELIM   (CONFIG_SYS_FLASH_BASE | \
 199                                 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
 200                                 BR_V)
 201
 202 #define CONFIG_SYS_OR0_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) | \
 203                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 204                                 OR_GPCM_SCY_5 | \
 205                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 206
 207 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks       */
 208 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 209 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
 210
 211 #undef  CONFIG_SYS_FLASH_CHECKSUM
 212
 213 /*
 214  * PRIO1/PIGGY on the local bus CS1
 215  */
 216 #define CONFIG_SYS_LBLAWBAR1_PRELIM     CONFIG_SYS_PIGGY_BASE /* Window base at flash base */
 217 #define CONFIG_SYS_LBLAWAR1_PRELIM      0x8000001A /* 128MB window size */
 218
 219 #define CONFIG_SYS_BR1_PRELIM   (CONFIG_SYS_PIGGY_BASE | \
 220                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 221                                 BR_V)
 222 #define CONFIG_SYS_OR1_PRELIM           (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) | /* 128MB */ \
 223                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 224                                 OR_GPCM_SCY_2 | \
 225                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 226
 227 /*
 228  * PAXE on the local bus CS3
 229  */
 230 #define CONFIG_SYS_LBLAWBAR3_PRELIM     CONFIG_SYS_PAXE_BASE /* Window base at flash base */
 231 #define CONFIG_SYS_LBLAWAR3_PRELIM      0x8000001C /* 512MB window size */
 232
 233 #define CONFIG_SYS_BR3_PRELIM   (CONFIG_SYS_PAXE_BASE | \
 234                                 (1 << BR_PS_SHIFT) | /* 8 bit port size */ \
 235                                 BR_V)
 236 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PAXE_SIZE) | \
 237                                 OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 | \
 238                                 OR_GPCM_SCY_2 | \
 239                                 OR_GPCM_TRLX | OR_GPCM_EAD)
 240
 241 /*
 242  * Serial Port
 243  */
 244 #define CONFIG_CONS_INDEX       1
 245 #undef  CONFIG_SERIAL_SOFTWARE_FIFO
 246 #define CONFIG_SYS_NS16550
 247 #define CONFIG_SYS_NS16550_SERIAL
 248 #define CONFIG_SYS_NS16550_REG_SIZE     1
 249 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 250
 251 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
 252 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
 253
 254 /* Pass open firmware flat tree */
 255 #define CONFIG_OF_LIBFDT        1
 256 #define CONFIG_OF_BOARD_SETUP   1
 257 #define CONFIG_OF_STDOUT_VIA_ALIAS
 258
 259 /*
 260  * General PCI
 261  * Addresses are mapped 1-1.
 262  */
 263 #undef CONFIG_PCI               /* No PCI */
 264
 265 #ifndef CONFIG_NET_MULTI
 266 #define CONFIG_NET_MULTI        1
 267 #endif
 268 /*
 269  * QE UEC ethernet configuration
 270  */
 271 #define CONFIG_UEC_ETH
 272 #define CONFIG_ETHPRIME         "FSL UEC0"
 273
 274 #define CONFIG_UEC_ETH1         /* GETH1 */
 275 #define UEC_VERBOSE_DEBUG       1
 276
 277 #ifdef CONFIG_UEC_ETH1
 278 #define CONFIG_SYS_UEC1_UCC_NUM 3       /* UCC4 */
 279 #define CONFIG_SYS_UEC1_RX_CLK          QE_CLK_NONE     /* not used in RMII Mode */
 280 #define CONFIG_SYS_UEC1_TX_CLK          QE_CLK17
 281 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 282 #define CONFIG_SYS_UEC1_PHY_ADDR        0
 283 #define CONFIG_SYS_UEC1_INTERFACE_MODE ENET_100_RMII
 284 #endif
 285
 286 /*
 287  * Environment
 288  */
 289
 290 #ifndef CONFIG_SYS_RAMBOOT
 291 #define CONFIG_ENV_IS_IN_FLASH  1
 292 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 293 #define CONFIG_ENV_SECT_SIZE    0x20000 /* 128K(one sector) for env */
 294 #define CONFIG_ENV_OFFSET       (CONFIG_SYS_MONITOR_LEN)
 295
 296 /* Address and size of Redundant Environment Sector     */
 297 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
 298 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 299
 300 #else /* CFG_RAMBOOT */
 301 #define CONFIG_SYS_NO_FLASH             1       /* Flash is not usable now */
 302 #define CONFIG_ENV_IS_NOWHERE   1       /* Store ENV in memory only */
 303 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - 0x1000)
 304 #define CONFIG_ENV_SIZE         0x2000
 305 #endif /* CFG_RAMBOOT */
 306
 307 /* I2C */
 308 #define CONFIG_HARD_I2C         /* I2C with hardware support */
 309 #undef  CONFIG_SOFT_I2C         /* I2C bit-banged */
 310 #define CONFIG_FSL_I2C
 311 #define CONFIG_SYS_I2C_SPEED    200000  /* I2C speed and slave address */
 312 #define CONFIG_SYS_I2C_SLAVE    0x7F
 313 #define CONFIG_SYS_I2C_OFFSET   0x3000
 314 #define CONFIG_I2C_MULTI_BUS    1
 315 #define CONFIG_I2C_MUX          1
 316
 317 /* EEprom support */
 318 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 319
 320 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 321 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 322 #define CONFIG_DTT_SENSORS      {0, 1, 2, 3}    /* Sensor addresses             */
 323 #define CONFIG_SYS_DTT_MAX_TEMP 70
 324 #define CONFIG_SYS_DTT_LOW_TEMP -30
 325 #define CONFIG_SYS_DTT_HYSTERESIS       3
 326 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 327
 328 #if defined(CONFIG_PCI)
 329 #define CONFIG_CMD_PCI
 330 #endif
 331
 332 #if defined(CFG_RAMBOOT)
 333 #undef CONFIG_CMD_SAVEENV
 334 #undef CONFIG_CMD_LOADS
 335 #endif
 336
 337 /*
 338  * For booting Linux, the board info and command line data
 339  * have to be in the first 8 MB of memory, since this is
 340  * the maximum mapped by the Linux kernel during initialization.
 341  */
 342 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 343
 344 /*
 345  * Core HID Setup
 346  */
 347 #define CONFIG_SYS_HID0_INIT            0x000000000
 348 #define CONFIG_SYS_HID0_FINAL           HID0_ENABLE_MACHINE_CHECK
 349 #define CONFIG_SYS_HID2                 HID2_HBE
 350
 351 /*
 352  * MMU Setup
 353  */
 354
 355 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 356
 357 /* DDR: cache cacheable */
 358 #define CONFIG_SYS_IBAT0L       (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | \
 359                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 360 #define CONFIG_SYS_IBAT0U       (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 361 #define CONFIG_SYS_DBAT0L       CONFIG_SYS_IBAT0L
 362 #define CONFIG_SYS_DBAT0U       CONFIG_SYS_IBAT0U
 363
 364 /* IMMRBAR & PCI IO: cache-inhibit and guarded */
 365 #define CONFIG_SYS_IBAT1L       (CONFIG_SYS_IMMR | BATL_PP_10 | \
 366                                 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 367 #define CONFIG_SYS_IBAT1U       (CONFIG_SYS_IMMR | BATU_BL_4M | BATU_VS | BATU_VP)
 368 #define CONFIG_SYS_DBAT1L       CONFIG_SYS_IBAT1L
 369 #define CONFIG_SYS_DBAT1U       CONFIG_SYS_IBAT1U
 370
 371 /* PRIO1, PIGGY:  icache cacheable, but dcache-inhibit and guarded */
 372 #define CONFIG_SYS_IBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 373 #define CONFIG_SYS_IBAT2U       (CONFIG_SYS_PIGGY_BASE | BATU_BL_128M | BATU_VS | BATU_VP)
 374 #define CONFIG_SYS_DBAT2L       (CONFIG_SYS_PIGGY_BASE | BATL_PP_10 | \
 375                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 376 #define CONFIG_SYS_DBAT2U       CONFIG_SYS_IBAT2U
 377
 378 /* FLASH: icache cacheable, but dcache-inhibit and guarded */
 379 #define CONFIG_SYS_IBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 380 #define CONFIG_SYS_IBAT3U       (CONFIG_SYS_FLASH_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 381 #define CONFIG_SYS_DBAT3L       (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
 382                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 383 #define CONFIG_SYS_DBAT3U       CONFIG_SYS_IBAT3U
 384
 385 /* Stack in dcache: cacheable, no memory coherence */
 386 #define CONFIG_SYS_IBAT4L       (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
 387 #define CONFIG_SYS_IBAT4U       (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 388 #define CONFIG_SYS_DBAT4L       CONFIG_SYS_IBAT4L
 389 #define CONFIG_SYS_DBAT4U       CONFIG_SYS_IBAT4U
 390
 391 /* PAXE:  icache cacheable, but dcache-inhibit and guarded */
 392 #define CONFIG_SYS_IBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 393 #define CONFIG_SYS_IBAT5U       (CONFIG_SYS_PAXE_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 394 #define CONFIG_SYS_DBAT5L       (CONFIG_SYS_PAXE_BASE | BATL_PP_10 | \
 395                                  BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 396 #define CONFIG_SYS_DBAT5U       CONFIG_SYS_IBAT5U
 397
 398 #ifdef CONFIG_PCI
 399 /* PCI MEM space: cacheable */
 400 #define CFG_IBAT6L      (CFG_PCI1_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
 401 #define CFG_IBAT6U      (CFG_PCI1_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 402 #define CFG_DBAT6L      CFG_IBAT6L
 403 #define CFG_DBAT6U      CFG_IBAT6U
 404 /* PCI MMIO space: cache-inhibit and guarded */
 405 #define CFG_IBAT7L      (CFG_PCI1_MMIO_PHYS | BATL_PP_10 | \
 406                          BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
 407 #define CFG_IBAT7U      (CFG_PCI1_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
 408 #define CFG_DBAT7L      CFG_IBAT7L
 409 #define CFG_DBAT7U      CFG_IBAT7U
 410 #else /* CONFIG_PCI */
 411 #define CONFIG_SYS_IBAT6L       (0)
 412 #define CONFIG_SYS_IBAT6U       (0)
 413 #define CONFIG_SYS_IBAT7L       (0)
 414 #define CONFIG_SYS_IBAT7U       (0)
 415 #define CONFIG_SYS_DBAT6L       CONFIG_SYS_IBAT6L
 416 #define CONFIG_SYS_DBAT6U       CONFIG_SYS_IBAT6U
 417 #define CONFIG_SYS_DBAT7L       CONFIG_SYS_IBAT7L
 418 #define CONFIG_SYS_DBAT7U       CONFIG_SYS_IBAT7U
 419 #endif /* CONFIG_PCI */
 420
 421 /*
 422  * Internal Definitions
 423  *
 424  * Boot Flags
 425  */
 426 #define BOOTFLAG_COLD   0x01 /* Normal Power-On: Boot from FLASH */
 427 #define BOOTFLAG_WARM   0x02 /* Software reboot */
 428
 429 #define BOOTFLASH_START F0000000
 430
 431 #define CONFIG_PRAM     512     /* protected RAM [KBytes] */
 432
 433 #define MTDIDS_DEFAULT          "nor2=app"
 434 #define MTDPARTS_DEFAULT \
 435         "mtdparts=app:256k(u-boot),128k(env),128k(envred),"     \
 436         "1536k(esw0),8704k(rootfs0),1536k(esw1),2432k(rootfs1),640k(var),768k(cfg)"
 437
 438 /*
 439  * Environment Configuration
 440  */
 441 #define CONFIG_ENV_OVERWRITE
 442 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 443 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 444 #endif
 445
 446 #define CONFIG_EXTRA_ENV_SETTINGS \
 447        CONFIG_KM_DEF_ENV                                                \
 448         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
 449         "addcon=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 450         "ramdisk_file=/tftpboot/kmeter1/uRamdisk\0"                     \
 451         "loadram=tftp ${ramdisk_addr_r} ${ramdisk_file}\0"              \
 452         "loadfdt=tftp ${fdt_addr_r} ${fdt_file}\0"                      \
 453         "loadkernel=tftp ${kernel_addr_r} ${bootfile}\0"                \
 454         "unlock=yes\0"                                                  \
 455         "fdt_addr=F0080000\0"                                           \
 456         "kernel_addr=F00a0000\0"                                        \
 457         "ramdisk_addr=F03a0000\0"                                       \
 458         "ramdisk_addr_r=F10000\0"                                       \
 459         "EEprom_ivm=pca9547:70:9\0"                                     \
 460         "dtt_bus=pca9547:70:a\0"                                        \
 461         "mtdids=nor0=app \0"                                            \
 462         "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                       \
 463    ""
 464
 465 #if defined(CONFIG_UEC_ETH)
 466 #define CONFIG_HAS_ETH0
 467 #endif
 468
 469 #endif /* __CONFIG_H */