include/configs/kmp204x.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2013 Keymile AG
   4  * Valentin Longchamp <valentin.longchamp@keymile.com>
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #if defined(CONFIG_KMCOGE4)
  11 #define CONFIG_HOSTNAME         "kmcoge4"
  12
  13 #else
  14 #error ("Board not supported")
  15 #endif
  16
  17 #define CONFIG_KMP204X
  18
  19 /* an additionnal option is required for UBI as subpage access is
  20  * supported in u-boot
  21  */
  22 #define CONFIG_KM_UBI_PART_BOOT_OPTS            ",2048"
  23
  24 #define CONFIG_NAND_ECC_BCH
  25
  26 /* common KM defines */
  27 #include "km/keymile-common.h"
  28
  29 #define CONFIG_SYS_RAMBOOT
  30 #define CONFIG_RAMBOOT_PBL
  31 #define CONFIG_RAMBOOT_TEXT_BASE        CONFIG_SYS_TEXT_BASE
  32 #define CONFIG_RESET_VECTOR_ADDRESS     0xfffffffc
  33 #define CONFIG_SYS_FSL_PBL_PBI board/keymile/kmp204x/pbi.cfg
  34 #define CONFIG_SYS_FSL_PBL_RCW board/keymile/kmp204x/rcw_kmp204x.cfg
  35
  36 /* High Level Configuration Options */
  37 #define CONFIG_SYS_BOOK3E_HV            /* Category E.HV supported */
  38 #define CONFIG_FSL_CORENET              /* Freescale CoreNet platform */
  39
  40 #define CONFIG_SYS_FSL_CPC              /* Corenet Platform Cache */
  41 #define CONFIG_SYS_NUM_CPC              CONFIG_SYS_NUM_DDR_CTLRS
  42 #define CONFIG_PCIE1                    /* PCIE controller 1 */
  43 #define CONFIG_PCIE3                    /* PCIE controller 3 */
  44 #define CONFIG_FSL_PCI_INIT             /* Use common FSL init code */
  45 #define CONFIG_SYS_PCI_64BIT            /* enable 64-bit PCI resources */
  46
  47 #define CONFIG_SYS_DPAA_RMAN            /* RMan */
  48
  49 /* Environment in SPI Flash */
  50 #define CONFIG_ENV_TOTAL_SIZE           0x020000
  51
  52 #ifndef __ASSEMBLY__
  53 unsigned long get_board_sys_clk(unsigned long dummy);
  54 #endif
  55 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0)
  56
  57 /*
  58  * These can be toggled for performance analysis, otherwise use default.
  59  */
  60 #define CONFIG_SYS_CACHE_STASHING
  61 #define CONFIG_BACKSIDE_L2_CACHE
  62 #define CONFIG_SYS_INIT_L2CSR0          L2CSR0_L2E
  63 #define CONFIG_BTB                      /* toggle branch predition */
  64
  65 #define CONFIG_ENABLE_36BIT_PHYS
  66
  67 #define CONFIG_ADDR_MAP
  68 #define CONFIG_SYS_NUM_ADDR_MAP         64      /* number of TLB1 entries */
  69
  70 #define CONFIG_POST CONFIG_SYS_POST_MEM_REGIONS /* POST memory regions test */
  71
  72 /*
  73  *  Config the L3 Cache as L3 SRAM
  74  */
  75 #define CONFIG_SYS_INIT_L3_ADDR         CONFIG_RAMBOOT_TEXT_BASE
  76 #define CONFIG_SYS_INIT_L3_ADDR_PHYS    (0xf00000000ull | \
  77                 CONFIG_RAMBOOT_TEXT_BASE)
  78 #define CONFIG_SYS_L3_SIZE              (1024 << 10)
  79 #define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
  80
  81 #define CONFIG_SYS_DCSRBAR              0xf0000000
  82 #define CONFIG_SYS_DCSRBAR_PHYS         0xf00000000ull
  83
  84 /*
  85  * DDR Setup
  86  */
  87 #define CONFIG_VERY_BIG_RAM
  88 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  89 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  90
  91 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  92 #define CONFIG_CHIP_SELECTS_PER_CTRL    (4 * CONFIG_DIMM_SLOTS_PER_CTLR)
  93
  94 #define CONFIG_DDR_SPD
  95
  96 #define CONFIG_SYS_SPD_BUS_NUM  0
  97 #define SPD_EEPROM_ADDRESS      0x54
  98 #define CONFIG_SYS_SDRAM_SIZE   4096    /* for fixed parameter use */
  99
 100 #define CONFIG_SYS_LOAD_ADDR    0x100000        /* default load address */
 101 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2
 102
 103 /******************************************************************************
 104  * (PRAM usage)
 105  * ... -------------------------------------------------------
 106  * ... |ROOTFSSIZE | PNVRAM |PHRAM |RESERVED_PRAM | END_OF_RAM
 107  * ... |<------------------- pram -------------------------->|
 108  * ... -------------------------------------------------------
 109  * @END_OF_RAM:
 110  * @CONFIG_KM_RESERVED_PRAM: reserved pram for special purpose
 111  * @CONFIG_KM_PHRAM: address for /var
 112  * @CONFIG_KM_PNVRAM: address for PNVRAM (for the application)
 113  * @CONFIG_KM_ROOTFSSIZE: address for rootfilesystem in RAM
 114  */
 115
 116 /* size of rootfs in RAM */
 117 #define CONFIG_KM_ROOTFSSIZE    0x0
 118 /* pseudo-non volatile RAM [hex] */
 119 #define CONFIG_KM_PNVRAM        0x80000
 120 /* physical RAM MTD size [hex] */
 121 #define CONFIG_KM_PHRAM         0x100000
 122 /* reserved pram area at the end of memory [hex]
 123  * u-boot reserves some memory for the MP boot page
 124  */
 125 #define CONFIG_KM_RESERVED_PRAM 0x1000
 126 /* set the default PRAM value to at least PNVRAM + PHRAM when pram env variable
 127  * is not valid yet, which is the case for when u-boot copies itself to RAM
 128  */
 129 #define CONFIG_PRAM             ((CONFIG_KM_PNVRAM + CONFIG_KM_PHRAM) >> 10)
 130
 131 #define CONFIG_KM_CRAMFS_ADDR   0x2000000
 132 #define CONFIG_KM_KERNEL_ADDR   0x1000000       /* max kernel size 15.5Mbytes */
 133 #define CONFIG_KM_FDT_ADDR      0x1F80000       /* max dtb    size  0.5Mbytes */
 134
 135 /*
 136  * Local Bus Definitions
 137  */
 138
 139 /* Set the local bus clock 1/8 of plat clk, 2 clk delay LALE */
 140 #define CONFIG_SYS_LBC_LCRR             (LCRR_CLKDIV_8 | LCRR_EADC_2)
 141
 142 /* Nand Flash */
 143 #define CONFIG_NAND_FSL_ELBC
 144 #define CONFIG_SYS_NAND_BASE            0xffa00000
 145 #define CONFIG_SYS_NAND_BASE_PHYS       0xfffa00000ull
 146
 147 #define CONFIG_SYS_NAND_BASE_LIST     {CONFIG_SYS_NAND_BASE}
 148 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 149 #define CONFIG_SYS_NAND_BLOCK_SIZE    (128 * 1024)
 150
 151 /* NAND flash config */
 152 #define CONFIG_SYS_NAND_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 153                                | BR_PS_8               /* Port Size = 8 bit */ \
 154                                | BR_MS_FCM             /* MSEL = FCM */ \
 155                                | BR_V)                 /* valid */
 156
 157 #define CONFIG_SYS_NAND_OR_PRELIM  (OR_AM_256KB       /* length 256K */ \
 158                                | OR_FCM_BCTLD   /* LBCTL not ass */     \
 159                                | OR_FCM_SCY_1   /* 1 clk wait cycle */  \
 160                                | OR_FCM_RST     /* 1 clk read setup */  \
 161                                | OR_FCM_PGS     /* Large page size */   \
 162                                | OR_FCM_CST)    /* 0.25 command setup */
 163
 164 #define CONFIG_SYS_BR0_PRELIM  CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
 165 #define CONFIG_SYS_OR0_PRELIM  CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
 166
 167 /* QRIO FPGA */
 168 #define CONFIG_SYS_QRIO_BASE            0xfb000000
 169 #define CONFIG_SYS_QRIO_BASE_PHYS       0xffb000000ull
 170
 171 #define CONFIG_SYS_QRIO_BR_PRELIM  (BR_PHYS_ADDR(CONFIG_SYS_QRIO_BASE_PHYS) \
 172                                 | BR_PS_8       /* Port Size 8 bits */ \
 173                                 | BR_DECC_OFF   /* no error corr */ \
 174                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 175                                 | BR_V)         /* valid */
 176
 177 #define CONFIG_SYS_QRIO_OR_PRELIM  (OR_AM_64KB  /* length 64K */ \
 178                                 | OR_GPCM_BCTLD /* no LCTL assert */ \
 179                                 | OR_GPCM_ACS_DIV4 /* LCS 1/4 clk after */ \
 180                                 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
 181                                 | OR_GPCM_TRLX /* relaxed tmgs */ \
 182                                 | OR_GPCM_EAD) /* extra bus clk cycles */
 183
 184 #define CONFIG_SYS_BR1_PRELIM  CONFIG_SYS_QRIO_BR_PRELIM /* QRIO Base Address */
 185 #define CONFIG_SYS_OR1_PRELIM  CONFIG_SYS_QRIO_OR_PRELIM /* QRIO Options */
 186
 187 #define CONFIG_MISC_INIT_F
 188
 189 #define CONFIG_HWCONFIG
 190
 191 /* define to use L1 as initial stack */
 192 #define CONFIG_L1_INIT_RAM
 193 #define CONFIG_SYS_INIT_RAM_LOCK
 194 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000      /* Initial L1 address */
 195 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
 196 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR
 197 /* The assembler doesn't like typecast */
 198 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
 199         ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
 200           CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
 201 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 202
 203 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 204                                         GENERATED_GBL_DATA_SIZE)
 205 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 206
 207 #define CONFIG_SYS_MONITOR_BASE         CONFIG_SYS_TEXT_BASE
 208 #define CONFIG_SYS_MONITOR_LEN          (768 * 1024)
 209 #define CONFIG_SYS_MALLOC_LEN           (1024 * 1024)
 210
 211 /* Serial Port - controlled on board with jumper J8
 212  * open - index 2
 213  * shorted - index 1
 214  */
 215 #define CONFIG_SYS_NS16550_SERIAL
 216 #define CONFIG_SYS_NS16550_REG_SIZE     1
 217 #define CONFIG_SYS_NS16550_CLK          (get_bus_freq(0) / 2)
 218
 219 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x11C500)
 220 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x11C600)
 221 #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR + 0x11D500)
 222 #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR + 0x11D600)
 223
 224 #define CONFIG_KM_CONSOLE_TTY   "ttyS0"
 225
 226 /* I2C */
 227 /* QRIO GPIOs used for deblocking */
 228 #define KM_I2C_DEBLOCK_PORT     QRIO_GPIO_A
 229 #define KM_I2C_DEBLOCK_SCL      20
 230 #define KM_I2C_DEBLOCK_SDA      21
 231
 232 #define CONFIG_SYS_I2C
 233 #define CONFIG_SYS_I2C_INIT_BOARD
 234 #define CONFIG_SYS_I2C_SPEED            100000 /* deblocking */
 235 #define CONFIG_SYS_NUM_I2C_BUSES        3
 236 #define CONFIG_SYS_I2C_MAX_HOPS         1
 237 #define CONFIG_SYS_I2C_FSL              /* Use FSL I2C driver */
 238 #define CONFIG_I2C_MULTI_BUS
 239 #define CONFIG_I2C_CMD_TREE
 240 #define CONFIG_SYS_FSL_I2C_SPEED        400000
 241 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 242 #define CONFIG_SYS_FSL_I2C_OFFSET       0x118000
 243 #define CONFIG_SYS_I2C_BUSES    {       {0, {I2C_NULL_HOP} }, \
 244                                         {0, {{I2C_MUX_PCA9547, 0x70, 1 } } }, \
 245                                         {0, {{I2C_MUX_PCA9547, 0x70, 2 } } }, \
 246                                 }
 247 #ifndef __ASSEMBLY__
 248 void set_sda(int state);
 249 void set_scl(int state);
 250 int get_sda(void);
 251 int get_scl(void);
 252 #endif
 253
 254 #define CONFIG_KM_IVM_BUS               1       /* I2C1 (Mux-Port 1)*/
 255
 256 /*
 257  * eSPI - Enhanced SPI
 258  */
 259
 260 /*
 261  * General PCI
 262  * Memory space is mapped 1-1, but I/O space must start from 0.
 263  */
 264
 265 /* controller 1, direct to uli, tgtid 3, Base address 20000 */
 266 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 267 #define CONFIG_SYS_PCIE1_MEM_BUS        0xe0000000
 268 #define CONFIG_SYS_PCIE1_MEM_PHYS       0xc00000000ull
 269 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 270 #define CONFIG_SYS_PCIE1_IO_VIRT        0xf8000000
 271 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 272 #define CONFIG_SYS_PCIE1_IO_PHYS        0xff8000000ull
 273 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 274
 275 /* controller 3, Slot 1, tgtid 1, Base address 202000 */
 276 #define CONFIG_SYS_PCIE3_MEM_VIRT       0xa0000000
 277 #define CONFIG_SYS_PCIE3_MEM_BUS        0xe0000000
 278 #define CONFIG_SYS_PCIE3_MEM_PHYS       0xc20000000ull
 279 #define CONFIG_SYS_PCIE3_MEM_SIZE       0x20000000      /* 512M */
 280 #define CONFIG_SYS_PCIE3_IO_VIRT        0xf8010000
 281 #define CONFIG_SYS_PCIE3_IO_BUS         0x00000000
 282 #define CONFIG_SYS_PCIE3_IO_PHYS        0xff8010000ull
 283 #define CONFIG_SYS_PCIE3_IO_SIZE        0x00010000      /* 64k */
 284
 285 /* Qman/Bman */
 286 #define CONFIG_SYS_BMAN_NUM_PORTALS     10
 287 #define CONFIG_SYS_BMAN_MEM_BASE        0xf4000000
 288 #define CONFIG_SYS_BMAN_MEM_PHYS        0xff4000000ull
 289 #define CONFIG_SYS_BMAN_MEM_SIZE        0x00200000
 290 #define CONFIG_SYS_BMAN_SP_CENA_SIZE    0x4000
 291 #define CONFIG_SYS_BMAN_SP_CINH_SIZE    0x1000
 292 #define CONFIG_SYS_BMAN_CENA_BASE       CONFIG_SYS_BMAN_MEM_BASE
 293 #define CONFIG_SYS_BMAN_CENA_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 294 #define CONFIG_SYS_BMAN_CINH_BASE       (CONFIG_SYS_BMAN_MEM_BASE + \
 295                                         CONFIG_SYS_BMAN_CENA_SIZE)
 296 #define CONFIG_SYS_BMAN_CINH_SIZE       (CONFIG_SYS_BMAN_MEM_SIZE >> 1)
 297 #define CONFIG_SYS_BMAN_SWP_ISDR_REG    0xE08
 298 #define CONFIG_SYS_QMAN_NUM_PORTALS     10
 299 #define CONFIG_SYS_QMAN_MEM_BASE        0xf4200000
 300 #define CONFIG_SYS_QMAN_MEM_PHYS        0xff4200000ull
 301 #define CONFIG_SYS_QMAN_MEM_SIZE        0x00200000
 302 #define CONFIG_SYS_QMAN_SP_CENA_SIZE    0x4000
 303 #define CONFIG_SYS_QMAN_SP_CINH_SIZE    0x1000
 304 #define CONFIG_SYS_QMAN_CENA_BASE       CONFIG_SYS_QMAN_MEM_BASE
 305 #define CONFIG_SYS_QMAN_CENA_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 306 #define CONFIG_SYS_QMAN_CINH_BASE       (CONFIG_SYS_QMAN_MEM_BASE + \
 307                                         CONFIG_SYS_QMAN_CENA_SIZE)
 308 #define CONFIG_SYS_QMAN_CINH_SIZE       (CONFIG_SYS_QMAN_MEM_SIZE >> 1)
 309 #define CONFIG_SYS_QMAN_SWP_ISDR_REG    0xE08
 310
 311 #define CONFIG_SYS_DPAA_FMAN
 312 #define CONFIG_SYS_DPAA_PME
 313 /* Default address of microcode for the Linux Fman driver
 314  * env is stored at 0x100000, sector size is 0x10000, x2 (redundant)
 315  * ucode is stored after env, so we got 0x120000.
 316  */
 317 #define CONFIG_SYS_FMAN_FW_ADDR 0x120000
 318 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 319 #define CONFIG_SYS_FDT_PAD              (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
 320
 321 #define CONFIG_PHYLIB_10G
 322
 323 #define CONFIG_PCI_INDIRECT_BRIDGE
 324
 325 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 326
 327 /* RGMII (FM1@DTESC5) is used as debug itf, it's the only one configured */
 328 #define CONFIG_SYS_FM1_DTSEC5_PHY_ADDR  0x11
 329 #define CONFIG_SYS_TBIPA_VALUE  8
 330 #define CONFIG_ETHPRIME         "FM1@DTSEC5"
 331
 332 /*
 333  * Environment
 334  */
 335 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 336 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 337
 338 /*
 339  * Hardware Watchdog
 340  */
 341 #define CONFIG_WATCHDOG                 /* enable CPU watchdog */
 342 #define CONFIG_WATCHDOG_PRESC 34        /* wdog prescaler 2^(64-34) (~10min) */
 343 #define CONFIG_WATCHDOG_RC WRC_CHIP     /* reset chip on watchdog event */
 344
 345 /*
 346  * additionnal command line configuration.
 347  */
 348
 349 /* we don't need flash support */
 350 #undef CONFIG_JFFS2_CMDLINE
 351
 352 /*
 353  * For booting Linux, the board info and command line data
 354  * have to be in the first 64 MB of memory, since this is
 355  * the maximum mapped by the Linux kernel during initialization.
 356  */
 357 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux */
 358 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 359
 360 #ifdef CONFIG_CMD_KGDB
 361 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 362 #endif
 363
 364 #define __USB_PHY_TYPE  utmi
 365 #define CONFIG_USB_EHCI_FSL
 366
 367 /*
 368  * Environment Configuration
 369  */
 370 #define CONFIG_ENV_OVERWRITE
 371 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
 372 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
 373 #endif
 374
 375 /* architecture specific default bootargs */
 376 #define CONFIG_KM_DEF_BOOT_ARGS_CPU             ""
 377
 378 /* FIXME: FDT_ADDR is unspecified */
 379 #define CONFIG_KM_DEF_ENV_CPU                                           \
 380         "boot=bootm ${load_addr_r} - ${fdt_addr_r}\0"                   \
 381         "cramfsloadfdt="                                                \
 382                 "cramfsload ${fdt_addr_r} "                             \
 383                 "fdt_0x${IVM_BoardId}_0x${IVM_HWKey}.dtb\0"             \
 384         "fdt_addr_r=" __stringify(CONFIG_KM_FDT_ADDR) "\0"              \
 385         "u-boot=" CONFIG_HOSTNAME "/u-boot.pbl\0"               \
 386         "update="                                                       \
 387                 "sf probe 0;sf erase 0 +${filesize};"                   \
 388                 "sf write ${load_addr_r} 0 ${filesize};\0"              \
 389         "set_fdthigh=true\0"                                            \
 390         "checkfdt=true\0"                                               \
 391         ""
 392
 393 #define CONFIG_HW_ENV_SETTINGS                                          \
 394         "hwconfig=fsl_ddr:ctlr_intlv=cacheline\0"                       \
 395         "usb_phy_type=" __stringify(__USB_PHY_TYPE) "\0"                \
 396         "usb_dr_mode=host\0"
 397
 398 #define CONFIG_KM_NEW_ENV                                               \
 399         "newenv=sf probe 0;"                                            \
 400                 "sf erase " __stringify(CONFIG_ENV_OFFSET) " "          \
 401                 __stringify(CONFIG_ENV_TOTAL_SIZE)"\0"
 402
 403 /* ppc_82xx is the equivalent to ppc_6xx, the generic ppc toolchain */
 404 #ifndef CONFIG_KM_DEF_ARCH
 405 #define CONFIG_KM_DEF_ARCH      "arch=ppc_82xx\0"
 406 #endif
 407
 408 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 409         CONFIG_KM_DEF_ENV                                               \
 410         CONFIG_KM_DEF_ARCH                                              \
 411         CONFIG_KM_NEW_ENV                                               \
 412         CONFIG_HW_ENV_SETTINGS                                          \
 413         "EEprom_ivm=pca9547:70:9\0"                                     \
 414         ""
 415
 416 /* App2 Local bus */
 417 #define CONFIG_SYS_LBAPP2_BASE          0xE0000000
 418 #define CONFIG_SYS_LBAPP2_BASE_PHYS     0xFE0000000ull
 419
 420 #define CONFIG_SYS_LBAPP2_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_LBAPP2_BASE_PHYS) \
 421                                 | BR_PS_8       /* Port Size 8 bits */ \
 422                                 | BR_DECC_OFF   /* no error corr */ \
 423                                 | BR_MS_GPCM    /* MSEL = GPCM */ \
 424                                 | BR_V)         /* valid */
 425
 426 #define CONFIG_SYS_LBAPP2_OR_PRELIM (OR_AM_256MB        /* length 256MB */ \
 427                                 | OR_GPCM_ACS_DIV2 /* LCS 1/2 clk after */ \
 428                                 | OR_GPCM_CSNT /* LCS 1/4 clk before */ \
 429                                 | OR_GPCM_SCY_2 /* 2 clk wait cycles */ \
 430                                 | OR_GPCM_TRLX /* relaxed tmgs */ \
 431                                 | OR_GPCM_EAD) /* extra bus clk cycles */
 432 /* Local bus app2 Base Address */
 433 #define CONFIG_SYS_BR3_PRELIM  CONFIG_SYS_LBAPP2_BR_PRELIM
 434 /* Local bus app2 Options */
 435 #define CONFIG_SYS_OR3_PRELIM  CONFIG_SYS_LBAPP2_OR_PRELIM
 436
 437 #endif  /* __CONFIG_H */