include/configs/korat.h

   1 /*
   2  * (C) Copyright 2007-2009
   3  * Larry Johnson, lrj@acm.org
   4  *
   5  * (C) Copyright 2006-2007
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * (C) Copyright 2006
   9  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  10  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  11  *
  12  * SPDX-License-Identifier:     GPL-2.0+
  13  */
  14
  15 /*
  16  * korat.h - configuration for Korat board
  17  */
  18 #ifndef __CONFIG_H
  19 #define __CONFIG_H
  20
  21 /*
  22  * High Level Configuration Options
  23  */
  24 #define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  25 #define CONFIG_SYS_CLK_FREQ     33333333
  26
  27 #ifdef CONFIG_KORAT_PERMANENT
  28 #define CONFIG_SYS_TEXT_BASE    0xFFFA0000
  29 #else
  30 #define CONFIG_SYS_TEXT_BASE    0xF7F60000
  31 #endif
  32
  33 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  34 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  35
  36 /*
  37  * Manufacturer's information serial EEPROM parameters
  38  */
  39 #define MAN_DATA_EEPROM_ADDR    0x53    /* EEPROM I2C address           */
  40 #define MAN_INFO_FIELD          2
  41 #define MAN_INFO_LENGTH         9
  42 #define MAN_MAC_ADDR_FIELD      3
  43 #define MAN_MAC_ADDR_LENGTH     12
  44
  45 /*
  46  * Base addresses -- Note these are effective addresses where the actual
  47  * resources get mapped (not physical addresses).
  48  */
  49 #define CONFIG_SYS_MONITOR_LEN          (384 * 1024) /* Reserve 384 kiB for Monitor  */
  50 #define CONFIG_SYS_MALLOC_LEN           (256 * 1024) /* Reserve 256 kiB for malloc() */
  51
  52 #define CONFIG_SYS_SDRAM_BASE           0x00000000      /* _must_ be 0          */
  53 #define CONFIG_SYS_FLASH0_SIZE          0x01000000
  54 #define CONFIG_SYS_FLASH0_ADDR          (-CONFIG_SYS_FLASH0_SIZE)
  55 #define CONFIG_SYS_FLASH1_TOP           0xF8000000
  56 #define CONFIG_SYS_FLASH1_MAX_SIZE      0x08000000
  57 #define CONFIG_SYS_FLASH1_ADDR          (CONFIG_SYS_FLASH1_TOP - CONFIG_SYS_FLASH1_MAX_SIZE)
  58 #define CONFIG_SYS_FLASH_BASE           CONFIG_SYS_FLASH1_ADDR  /* start of FLASH       */
  59 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
  60 #define CONFIG_SYS_OCM_BASE             0xe0010000      /* ocm                  */
  61 #define CONFIG_SYS_OCM_DATA_ADDR        CONFIG_SYS_OCM_BASE
  62 #define CONFIG_SYS_PCI_BASE             0xe0000000      /* Internal PCI regs    */
  63 #define CONFIG_SYS_PCI_MEMBASE          0x80000000      /* mapped pci memory    */
  64 #define CONFIG_SYS_PCI_MEMBASE2         (CONFIG_SYS_PCI_MEMBASE + 0x20000000)
  65
  66 #define CONFIG_SYS_USB2D0_BASE          0xe0000100
  67 #define CONFIG_SYS_USB_DEVICE           0xe0000000
  68 #define CONFIG_SYS_USB_HOST             0xe0000400
  69 #define CONFIG_SYS_CPLD_BASE            0xc0000000
  70
  71 /*
  72  * Initial RAM & stack pointer
  73  */
  74 /* 440EPx has 16KB of internal SRAM, so no need for D-Cache             */
  75 #undef CONFIG_SYS_INIT_RAM_DCACHE
  76 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_BASE     /* OCM                  */
  77 #define CONFIG_SYS_INIT_RAM_SIZE        (4 << 10)
  78 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  79 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  80
  81 /*
  82  * Serial Port
  83  */
  84 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  85 #define CONFIG_SYS_NS16550
  86 #define CONFIG_SYS_NS16550_SERIAL
  87 #define CONFIG_SYS_NS16550_REG_SIZE     1
  88 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
  89 #define CONFIG_SYS_EXT_SERIAL_CLOCK     11059200        /* ext. 11.059MHz clk   */
  90 #define CONFIG_BAUDRATE         115200
  91
  92 #define CONFIG_SYS_BAUDRATE_TABLE                                               \
  93         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  94
  95 /*
  96  * Environment
  97  */
  98 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environ vars   */
  99
 100 /*
 101  * FLASH related
 102  */
 103 #define CONFIG_SYS_FLASH_CFI                    /* The flash is CFI compatible        */
 104 #define CONFIG_FLASH_CFI_DRIVER         /* Use common CFI driver              */
 105 #define CONFIG_FLASH_CFI_LEGACY         /* Allow hard-coded config for FLASH0 */
 106
 107 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH1_ADDR, CONFIG_SYS_FLASH0_ADDR }
 108
 109 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max number of memory banks         */
 110 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* max number of sectors on one chip  */
 111
 112 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)    */
 113 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)    */
 114
 115 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)   */
 116 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection      */
 117
 118 #define CONFIG_SYS_FLASH_EMPTY_INFO           /* print 'E' for empty sector on flinfo */
 119 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash      */
 120
 121 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector        */
 122 #define CONFIG_ENV_ADDR         (CONFIG_SYS_FLASH1_TOP - CONFIG_ENV_SECT_SIZE)
 123 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector   */
 124
 125 /* Address and size of Redundant Environment Sector */
 126 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
 127 #define CONFIG_ENV_SIZE_REDUND  CONFIG_ENV_SIZE
 128
 129 /*
 130  * DDR SDRAM
 131  */
 132 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 133 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
 134 #define CONFIG_ZERO_SDRAM               /* Zero SDRAM after setup       */
 135 #define CONFIG_DDR_ECC                  /* Use ECC when available       */
 136 #define SPD_EEPROM_ADDRESS      {0x50}
 137 #define CONFIG_PROG_SDRAM_TLB
 138 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10) /* don't use last 4 KiB as    */
 139                                         /* per 440EPx Errata CHIP_11    */
 140
 141 /*
 142  * I2C
 143  */
 144 #define CONFIG_SYS_I2C
 145 #define CONFIG_SYS_I2C_PPC4XX
 146 #define CONFIG_SYS_I2C_PPC4XX_CH0
 147 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 148 #define CONFIG_SYS_I2C_PPC4XX_SLAVE_0           0x7F
 149
 150 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 151 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 152 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 155
 156 /* I2C RTC */
 157 #define CONFIG_RTC_M41T60       1
 158 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 159
 160 /* I2C SYSMON (LM73)                                                    */
 161 #define CONFIG_DTT_LM73         1       /* National Semi's LM73         */
 162 #define CONFIG_DTT_SENSORS      {2}     /* Sensor addresses             */
 163 #define CONFIG_SYS_DTT_MAX_TEMP 70
 164 #define CONFIG_SYS_DTT_MIN_TEMP -30
 165
 166 #define CONFIG_PREBOOT  "echo;"                                         \
 167         "echo Type \\\"run flash_cf\\\" to mount from CompactFlash(R);" \
 168         "echo"
 169
 170 #undef  CONFIG_BOOTARGS
 171
 172 /* Setup some board specific values for the default environment variables */
 173 #define CONFIG_HOSTNAME         korat
 174
 175 /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
 176 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 177         "u_boot=korat/u-boot.bin\0"                                     \
 178         "load=tftp 200000 ${u_boot}\0"                                  \
 179         "update=protect off F7F60000 F7FBFFFF;erase F7F60000 F7FBFFFF;" \
 180                 "cp.b ${fileaddr} F7F60000 ${filesize};protect on "     \
 181                 "F7F60000 F7FBFFFF\0"                                   \
 182         "upd=run load update\0"                                         \
 183         "bootfile=korat/uImage\0"                                       \
 184         "dtb=korat/korat.dtb\0"                                         \
 185         "kernel_addr=F4000000\0"                                        \
 186         "ramdisk_addr=F4400000\0"                                       \
 187         "dtb_addr=F41E0000\0"                                           \
 188         "udl=tftp 200000 ${bootfile}; erase F4000000 F41DFFFF; "        \
 189                 "cp.b ${fileaddr} F4000000 ${filesize}\0"               \
 190         "udd=tftp 200000 ${dtb}; erase F41E0000 F41FFFFF; "             \
 191                 "cp.b ${fileaddr} F41E0000 ${filesize}\0"               \
 192         "ll=setenv kernel_addr 200000; setenv dtb_addr 1000000; "       \
 193                 "tftp ${kernel_addr} ${uImage}; tftp ${dtb_addr} "      \
 194                 "${dtb}\0"                                              \
 195         "rd_size=73728\0"                                               \
 196         "ramargs=setenv bootargs root=/dev/ram rw "                     \
 197                 "ramdisk_size=${rd_size}\0"                             \
 198         "usbdev=sda1\0"                                                 \
 199         "usbargs=setenv bootargs root=/dev/${usbdev} ro rootdelay=10\0" \
 200         "rootpath=/opt/eldk/ppc_4xxFP\0"                                \
 201         "netdev=eth0\0"                                                 \
 202         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 203                 "nfsroot=${serverip}:${rootpath}\0"                     \
 204         "pciclk=33\0"                                                   \
 205         "addide=setenv bootargs ${bootargs} ide=reverse "               \
 206                 "idebus=${pciclk}\0"                                    \
 207         "addip=setenv bootargs ${bootargs} "                            \
 208                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 209                 ":${hostname}:${netdev}:off panic=1\0"                  \
 210         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 211         "flash_cf=run usbargs addide addip addtty; "                    \
 212                 "bootm ${kernel_addr} - ${dtb_addr}\0"                  \
 213         "flash_nfs=run nfsargs addide addip addtty; "                   \
 214                 "bootm ${kernel_addr} - ${dtb_addr}\0"                  \
 215         "flash_self=run ramargs addip addtty; "                         \
 216                 "bootm ${kernel_addr} ${ramdisk_addr} ${dtb_addr}\0"    \
 217         ""
 218
 219 #define CONFIG_BOOTCOMMAND      "run flash_cf"
 220
 221 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 222
 223 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 224 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change        */
 225
 226 #define CONFIG_PPC4xx_EMAC
 227 #define CONFIG_IBM_EMAC4_V4     1
 228 #define CONFIG_MII              1       /* MII PHY management           */
 229 #define CONFIG_PHY_ADDR         2       /* PHY address, See schematics  */
 230 #define CONFIG_PHY_DYNAMIC_ANEG 1
 231
 232 #undef CONFIG_PHY_RESET                 /* Don't do software PHY reset  */
 233 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 234
 235 #define CONFIG_HAS_ETH0
 236 #define CONFIG_SYS_RX_ETH_BUFFER        32      /* Number of ethernet rx        */
 237                                         /*   buffers & descriptors      */
 238 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 239 #define CONFIG_PHY1_ADDR        3
 240
 241 /* USB */
 242 #define CONFIG_USB_OHCI
 243 #define CONFIG_USB_STORAGE
 244
 245 /* Comment this out to enable USB 1.1 device */
 246 #define USB_2_0_DEVICE
 247
 248 /* Partitions */
 249 #define CONFIG_MAC_PARTITION
 250 #define CONFIG_DOS_PARTITION
 251 #define CONFIG_ISO_PARTITION
 252
 253 /*
 254  * BOOTP options
 255  */
 256 #define CONFIG_BOOTP_BOOTFILESIZE
 257 #define CONFIG_BOOTP_BOOTPATH
 258 #define CONFIG_BOOTP_GATEWAY
 259 #define CONFIG_BOOTP_HOSTNAME
 260 #define CONFIG_BOOTP_SUBNETMASK
 261
 262 /*
 263  * Command line configuration.
 264  */
 265 #include <config_cmd_default.h>
 266
 267 #define CONFIG_CMD_ASKENV
 268 #define CONFIG_CMD_DATE
 269 #define CONFIG_CMD_DHCP
 270 #define CONFIG_CMD_DTT
 271 #define CONFIG_CMD_DIAG
 272 #define CONFIG_CMD_EEPROM
 273 #define CONFIG_CMD_ELF
 274 #define CONFIG_CMD_FAT
 275 #define CONFIG_CMD_I2C
 276 #define CONFIG_CMD_IRQ
 277 #define CONFIG_CMD_MII
 278 #define CONFIG_CMD_NET
 279 #define CONFIG_CMD_NFS
 280 #define CONFIG_CMD_PCI
 281 #define CONFIG_CMD_PING
 282 #define CONFIG_CMD_REGINFO
 283 #define CONFIG_CMD_SDRAM
 284 #define CONFIG_CMD_USB
 285
 286 /* POST support */
 287 #define CONFIG_POST             (CONFIG_SYS_POST_CACHE  | \
 288                                  CONFIG_SYS_POST_CPU    | \
 289                                  CONFIG_SYS_POST_ECC    | \
 290                                  CONFIG_SYS_POST_ETHER  | \
 291                                  CONFIG_SYS_POST_FPU    | \
 292                                  CONFIG_SYS_POST_I2C    | \
 293                                  CONFIG_SYS_POST_MEMORY | \
 294                                  CONFIG_SYS_POST_RTC    | \
 295                                  CONFIG_SYS_POST_SPR    | \
 296                                  CONFIG_SYS_POST_UART)
 297
 298 #define CONFIG_LOGBUFFER
 299 #define CONFIG_SYS_POST_CACHE_ADDR      0xC8000000      /* free virtual address     */
 300
 301 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    /* Otherwise it catches logbuffer as output */
 302
 303 #define CONFIG_SUPPORT_VFAT
 304
 305 /*
 306  * Miscellaneous configurable options
 307  */
 308 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 309 #if defined(CONFIG_CMD_KGDB)
 310 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 311 #else
 312 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 313 #endif
 314 #define CONFIG_SYS_PBSIZE              (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 315                                         /* Print Buffer Size            */
 316 #define CONFIG_SYS_MAXARGS              16      /* max number of command args   */
 317 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size  */
 318
 319 #define CONFIG_SYS_MEMTEST_START        0x0400000 /* memtest works on           */
 320 #define CONFIG_SYS_MEMTEST_END          0x0C00000 /* 4 ... 12 MB in DRAM        */
 321
 322 #define CONFIG_SYS_LOAD_ADDR            0x100000  /* default load address       */
 323 #define CONFIG_SYS_EXTBDINFO            1  /* To use extended board_into (bd_t) */
 324
 325 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 326 #define CONFIG_LOOPW            1       /* enable loopw command         */
 327 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 328 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 329 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 330
 331 /*
 332  * Korat-specific options
 333  */
 334 #define CONFIG_SYS_KORAT_MAN_RESET_MS   10000   /* timeout for manufacturer reset */
 335
 336 /*
 337  * PCI stuff
 338  */
 339 /* General PCI */
 340 #define CONFIG_PCI                      /* include pci support          */
 341 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 342 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 343 #define CONFIG_SYS_PCI_CACHE_LINE_SIZE  0       /* to avoid problems with PNP   */
 344 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 345 #define CONFIG_SYS_PCI_TARGBASE 0x80000000      /* PCIaddr mapped to    */
 346                                                 /*   CONFIG_SYS_PCI_MEMBASE     */
 347 /* Board-specific PCI */
 348 #define CONFIG_SYS_PCI_TARGET_INIT
 349 #define CONFIG_SYS_PCI_MASTER_INIT
 350 #define CONFIG_SYS_PCI_BOARD_FIXUP_IRQ
 351
 352 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC                         */
 353 #define CONFIG_SYS_PCI_SUBSYS_ID       0xcafe   /* Whatever                     */
 354
 355 /*
 356  * For booting Linux, the board info and command line data have to be in the
 357  * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
 358  * during initialization.
 359  */
 360 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20) /* Initial Memory map for Linux */
 361
 362 /*
 363  * External Bus Controller (EBC) Setup
 364  */
 365
 366 /* Memory Bank 0 (NOR-FLASH) initialization                             */
 367 #if CONFIG_SYS_FLASH0_SIZE == 0x01000000
 368 #define CONFIG_SYS_EBC_PB0AP            0x04017300
 369 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH0_ADDR | 0x0009A000)
 370 #elif CONFIG_SYS_FLASH0_SIZE == 0x04000000
 371 #define CONFIG_SYS_EBC_PB0AP            0x04017300
 372 #define CONFIG_SYS_EBC_PB0CR            (CONFIG_SYS_FLASH0_ADDR | 0x000DA000)
 373 #else
 374 #error Unable to configure chip select for current CONFIG_SYS_FLASH0_SIZE
 375 #endif
 376
 377 /* Memory Bank 1 (NOR-FLASH) initialization                             */
 378 #if CONFIG_SYS_FLASH1_MAX_SIZE == 0x08000000
 379 #define CONFIG_SYS_EBC_PB1AP            0x04017300
 380 #define CONFIG_SYS_EBC_PB1CR            (CONFIG_SYS_FLASH1_ADDR | 0x000FA000)
 381 #else
 382 #error Unable to configure chip select for current CONFIG_SYS_FLASH1_MAX_SIZE
 383 #endif
 384
 385 /* Memory Bank 2 (CPLD) initialization                                  */
 386 #define CONFIG_SYS_EBC_PB2AP            0x04017300
 387 #define CONFIG_SYS_EBC_PB2CR            (CONFIG_SYS_CPLD_BASE | 0x00038000)
 388
 389 /*
 390  * GPIO Setup
 391  *
 392  * Korat GPIO usage:
 393  *
 394  *                   Init.
 395  * Pin    Source I/O value Function
 396  * ------ ------ --- ----- ---------------------------------
 397  * GPIO00  Alt1  I/O   x   PerAddr07
 398  * GPIO01  Alt1  I/O   x   PerAddr06
 399  * GPIO02  Alt1  I/O   x   PerAddr05
 400  * GPIO03  GPIO   x    x   GPIO03 to expansion bus connector
 401  * GPIO04  GPIO   x    x   GPIO04 to expansion bus connector
 402  * GPIO05  GPIO   x    x   GPIO05 to expansion bus connector
 403  * GPIO06  Alt1   O    x   PerCS1 (2nd NOR flash)
 404  * GPIO07  Alt1   O    x   PerCS2 (CPLD)
 405  * GPIO08  Alt1   O    x   PerCS3 to expansion bus connector
 406  * GPIO09  Alt1   O    x   PerCS4 to expansion bus connector
 407  * GPIO10  Alt1   O    x   PerCS5 to expansion bus connector
 408  * GPIO11  Alt1   I    x   PerErr
 409  * GPIO12  GPIO   O    0   ATMega !Reset
 410  * GPIO13  GPIO   x    x   Test Point 2 (TP2)
 411  * GPIO14  GPIO   O    1   Write protect EEPROM #1 (0xA8)
 412  * GPIO15  GPIO   O    0   CPU Run LED !On
 413  * GPIO16  Alt1   O    x   GMC1TxD0
 414  * GPIO17  Alt1   O    x   GMC1TxD1
 415  * GPIO18  Alt1   O    x   GMC1TxD2
 416  * GPIO19  Alt1   O    x   GMC1TxD3
 417  * GPIO20  Alt1   I    x   RejectPkt0
 418  * GPIO21  Alt1   I    x   RejectPkt1
 419  * GPIO22  GPIO   I    x   PGOOD_DDR
 420  * GPIO23  Alt1   O    x   SCPD0
 421  * GPIO24  Alt1   O    x   GMC0TxD2
 422  * GPIO25  Alt1   O    x   GMC0TxD3
 423  * GPIO26  GPIO? I/O   x   IIC0SDA (selected in SDR0_PFC4)
 424  * GPIO27  GPIO   O    0   PHY #0 1000BASE-X select
 425  * GPIO28  GPIO   O    0   PHY #1 1000BASE-X select
 426  * GPIO29  GPIO   I    x   Test jumper !Present
 427  * GPIO30  GPIO   I    x   SFP module #0 !Present
 428  * GPIO31  GPIO   I    x   SFP module #1 !Present
 429  *
 430  * GPIO32  GPIO   O    1   SFP module #0 Tx !Enable
 431  * GPIO33  GPIO   O    1   SFP module #1 Tx !Enable
 432  * GPIO34  Alt2   I    x   !UART1_CTS
 433  * GPIO35  Alt2   O    x   !UART1_RTS
 434  * GPIO36  Alt1   I    x   !UART0_CTS
 435  * GPIO37  Alt1   O    x   !UART0_RTS
 436  * GPIO38  Alt2   O    x   UART1_Tx
 437  * GPIO39  Alt2   I    x   UART1_Rx
 438  * GPIO40  Alt1   I    x   IRQ0 (Ethernet 0)
 439  * GPIO41  Alt1   I    x   IRQ1 (Ethernet 1)
 440  * GPIO42  Alt1   I    x   IRQ2 (PCI interrupt)
 441  * GPIO43  Alt1   I    x   IRQ3 (System Alert from CPLD)
 442  * GPIO44  xxxx   x    x   (grounded through pulldown)
 443  * GPIO45  GPIO   O    0   PHY #0 Enable
 444  * GPIO46  GPIO   O    0   PHY #1 Enable
 445  * GPIO47  GPIO   I    x   Reset switch !Pressed
 446  * GPIO48  GPIO   I    x   Shutdown switch !Pressed
 447  * GPIO49  xxxx   x    x   (reserved for trace port)
 448  *   .      .     .    .               .
 449  *   .      .     .    .               .
 450  *   .      .     .    .               .
 451  * GPIO63  xxxx   x    x   (reserved for trace port)
 452  */
 453
 454 #define CONFIG_SYS_GPIO_ATMEGA_RESET_   12
 455 #define CONFIG_SYS_GPIO_ATMEGA_SS_      13
 456 #define CONFIG_SYS_GPIO_PHY0_FIBER_SEL  27
 457 #define CONFIG_SYS_GPIO_PHY1_FIBER_SEL  28
 458 #define CONFIG_SYS_GPIO_SFP0_PRESENT_   30
 459 #define CONFIG_SYS_GPIO_SFP1_PRESENT_   31
 460 #define CONFIG_SYS_GPIO_SFP0_TX_EN_     32
 461 #define CONFIG_SYS_GPIO_SFP1_TX_EN_     33
 462 #define CONFIG_SYS_GPIO_PHY0_EN 45
 463 #define CONFIG_SYS_GPIO_PHY1_EN 46
 464 #define CONFIG_SYS_GPIO_RESET_PRESSED_  47
 465
 466 /*
 467  * PPC440 GPIO Configuration
 468  */
 469 #define CONFIG_SYS_4xx_GPIO_TABLE { /*    Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 470 {                                                                                       \
 471 /* GPIO Core 0 */                                                                       \
 472 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 473 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 474 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 475 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 476 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 477 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 478 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 479 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 480 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 481 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 482 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 483 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 484 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 485 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 486 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14                                */      \
 487 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 488 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 489 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 490 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 491 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 492 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 493 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 494 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 495 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 496 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 497 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 498 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 499 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 500 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28                USB2D_TXVALID   */      \
 501 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 502 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 503 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 504 },                                                                                      \
 505 {                                                                                       \
 506 /* GPIO Core 1 */                                                                       \
 507 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 508 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 509 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 510 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 511 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)   UART3_SIN*/ \
 512 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 513 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 514 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 515 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 516 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 517 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 518 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 519 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 520 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 521 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 522 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 523 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 524 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 525 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 526 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 527 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 528 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 529 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 530 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 531 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 532 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 533 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 534 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 535 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 536 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 537 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 538 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 539 }                                                                                       \
 540 }
 541
 542 #if defined(CONFIG_CMD_KGDB)
 543 #define CONFIG_KGDB_BAUDRATE    230400 /* speed to run kgdb serial port */
 544 #endif
 545
 546 /* Pass open firmware flat tree */
 547 #define CONFIG_OF_LIBFDT        1
 548 #define CONFIG_OF_BOARD_SETUP   1
 549
 550 #endif /* __CONFIG_H */