include/configs/korat.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Larry Johnson, lrj@acm.org
   4  *
   5  * (C) Copyright 2006-2007
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * (C) Copyright 2006
   9  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
  10  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
  11  *
  12  * This program is free software; you can redistribute it and/or
  13  * modify it under the terms of the GNU General Public License as
  14  * published by the Free Software Foundation; either version 2 of
  15  * the License, or (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  25  * MA 02111-1307 USA
  26  */
  27
  28 /*
  29  * korat.h - configuration for Korat board
  30  */
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*
  35  * High Level Configuration Options
  36  */
  37 #define CONFIG_440EPX           1       /* Specific PPC440EPx           */
  38 #define CONFIG_4xx              1       /* ... PPC4xx family            */
  39 #define CONFIG_SYS_CLK_FREQ     33333333
  40
  41 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  42 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  43
  44 /*
  45  * Manufacturer's information serial EEPROM parameters
  46  */
  47 #define MAN_DATA_EEPROM_ADDR    0x53    /* EEPROM I2C address           */
  48 #define MAN_INFO_FIELD          2
  49 #define MAN_INFO_LENGTH         9
  50 #define MAN_MAC_ADDR_FIELD      3
  51 #define MAN_MAC_ADDR_LENGTH     12
  52
  53 /*
  54  * Base addresses -- Note these are effective addresses where the actual
  55  * resources get mapped (not physical addresses).
  56  */
  57 #define CFG_MONITOR_LEN         (384 * 1024) /* Reserve 384 kiB for Monitor  */
  58 #define CFG_MALLOC_LEN          (256 * 1024) /* Reserve 256 kiB for malloc() */
  59
  60 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  61 #define CFG_FLASH0_SIZE         0x01000000
  62 #define CFG_FLASH0_ADDR         (-CFG_FLASH0_SIZE)
  63 #define CFG_FLASH1_TOP          0xF8000000
  64 #define CFG_FLASH1_MAX_SIZE     0x08000000
  65 #define CFG_FLASH1_ADDR         (CFG_FLASH1_TOP - CFG_FLASH1_MAX_SIZE)
  66 #define CFG_FLASH_BASE          CFG_FLASH1_ADDR /* start of FLASH       */
  67 #define CFG_MONITOR_BASE        TEXT_BASE
  68 #define CFG_OCM_BASE            0xe0010000      /* ocm                  */
  69 #define CFG_OCM_DATA_ADDR       CFG_OCM_BASE
  70 #define CFG_PCI_BASE            0xe0000000      /* Internal PCI regs    */
  71 #define CFG_PCI_MEMBASE         0x80000000      /* mapped pci memory    */
  72
  73 /* Don't change either of these */
  74 #define CFG_PERIPHERAL_BASE     0xef600000      /* internal peripherals */
  75
  76 #define CFG_USB2D0_BASE         0xe0000100
  77 #define CFG_USB_DEVICE          0xe0000000
  78 #define CFG_USB_HOST            0xe0000400
  79 #define CFG_CPLD_BASE           0xc0000000
  80
  81 /*
  82  * Initial RAM & stack pointer
  83  */
  84 /* 440EPx has 16KB of internal SRAM, so no need for D-Cache             */
  85 #undef CFG_INIT_RAM_DCACHE
  86 #define CFG_INIT_RAM_ADDR       CFG_OCM_BASE    /* OCM                  */
  87 #define CFG_INIT_RAM_END        (4 << 10)
  88 #define CFG_GBL_DATA_SIZE       256     /* num bytes initial data       */
  89 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  90 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  91
  92 /*
  93  * Serial Port
  94  */
  95 #define CFG_EXT_SERIAL_CLOCK    11059200        /* ext. 11.059MHz clk   */
  96 #define CONFIG_BAUDRATE         115200
  97 #define CONFIG_SERIAL_MULTI     1
  98 /* define this if you want console on UART1 */
  99 #undef CONFIG_UART1_CONSOLE
 100
 101 #define CFG_BAUDRATE_TABLE                                              \
 102         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 103
 104 /*
 105  * Environment
 106  */
 107 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environ vars   */
 108
 109 /*
 110  * FLASH related
 111  */
 112 #define CFG_FLASH_CFI                   /* The flash is CFI compatible        */
 113 #define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver              */
 114 #define CONFIG_FLASH_CFI_LEGACY         /* Allow hard-coded config for FLASH0 */
 115
 116 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH1_ADDR, CFG_FLASH0_ADDR }
 117
 118 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks         */
 119 #define CFG_MAX_FLASH_SECT      1024    /* max number of sectors on one chip  */
 120
 121 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)    */
 122 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)    */
 123
 124 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)   */
 125 #define CFG_FLASH_PROTECTION    1       /* use hardware flash protection      */
 126
 127 #define CFG_FLASH_EMPTY_INFO          /* print 'E' for empty sector on flinfo */
 128 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash      */
 129
 130 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector        */
 131 #define CFG_ENV_ADDR            (CFG_FLASH1_TOP - CFG_ENV_SECT_SIZE)
 132 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector   */
 133
 134 /* Address and size of Redundant Environment Sector */
 135 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
 136 #define CFG_ENV_SIZE_REDUND     CFG_ENV_SIZE
 137
 138 /*
 139  * DDR SDRAM
 140  */
 141 #define CFG_MBYTES_SDRAM        (512)   /* 512 MiB      TODO: remove    */
 142 #define CONFIG_DDR_DATA_EYE             /* use DDR2 optimization        */
 143 #define CONFIG_SPD_EEPROM               /* Use SPD EEPROM for setup     */
 144 #define CONFIG_ZERO_SDRAM               /* Zero SDRAM after setup       */
 145 #define CONFIG_DDR_ECC                  /* Use ECC when available       */
 146 #define SPD_EEPROM_ADDRESS      {0x50}
 147 #define CONFIG_PROG_SDRAM_TLB
 148 #define CFG_MEM_TOP_HIDE        (4 << 10) /* don't use last 4kbytes     */
 149                                         /* 440EPx errata CHIP 11        */
 150
 151 /*
 152  * I2C
 153  */
 154 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 155 #undef  CONFIG_SOFT_I2C                 /* I2C bit-banged               */
 156 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 157 #define CFG_I2C_SLAVE           0x7F
 158
 159 #define CFG_I2C_MULTI_EEPROMS
 160 #define CFG_I2C_EEPROM_ADDR     (0xa8>>1)
 161 #define CFG_I2C_EEPROM_ADDR_LEN 1
 162 #define CFG_EEPROM_PAGE_WRITE_BITS 3
 163 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10
 164
 165 /* I2C RTC */
 166 #define CONFIG_RTC_M41T60       1
 167 #define CFG_I2C_RTC_ADDR        0x68
 168
 169 /* I2C SYSMON (LM73)                                                    */
 170 #define CONFIG_DTT_LM73         1       /* National Semi's LM73         */
 171 #define CONFIG_DTT_SENSORS      {2}     /* Sensor addresses             */
 172 #define CFG_DTT_MAX_TEMP        70
 173 #define CFG_DTT_MIN_TEMP        -30
 174
 175 #define CONFIG_PREBOOT  "echo;"                                         \
 176         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 177         "echo"
 178
 179 #undef  CONFIG_BOOTARGS
 180
 181 /* Setup some board specific values for the default environment variables */
 182 #define CONFIG_HOSTNAME         korat
 183 #define CFG_BOOTFILE            "bootfile=/tftpboot/korat/uImage\0"
 184 #define CFG_ROOTPATH            "rootpath=/opt/eldk/ppc_4xxFP\0"
 185
 186 /* Note: kernel_addr and ramdisk_addr assume that FLASH1 is 64 MiB. */
 187 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 188         CFG_BOOTFILE                                                    \
 189         CFG_ROOTPATH                                                    \
 190         "netdev=eth0\0"                                                 \
 191         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 192                 "nfsroot=${serverip}:${rootpath}\0"                     \
 193         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 194         "addip=setenv bootargs ${bootargs} "                            \
 195                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 196                 ":${hostname}:${netdev}:off panic=1\0"                  \
 197         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 198         "flash_nfs=run nfsargs addip addtty;"                           \
 199                 "bootm ${kernel_addr}\0"                                \
 200         "flash_self=run ramargs addip addtty;"                          \
 201                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 202         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;"     \
 203                 "bootm\0"                                               \
 204         "kernel_addr=F4000000\0"                                        \
 205         "ramdisk_addr=F4400000\0"                                       \
 206         "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 207         "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;"   \
 208                 "cp.b 200000 FFFA0000 60000\0"                          \
 209         "upd=run load update\0"                                         \
 210         ""
 211 #define CONFIG_BOOTCOMMAND      "run flash_self"
 212
 213 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 214
 215 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 216 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 217
 218 #define CONFIG_IBM_EMAC4_V4     1
 219 #define CONFIG_MII              1       /* MII PHY management           */
 220 #define CONFIG_PHY_ADDR         2       /* PHY address, See schematics  */
 221 #define CONFIG_PHY_DYNAMIC_ANEG 1
 222
 223 #undef CONFIG_PHY_RESET                 /* Don't do software PHY reset  */
 224 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 225
 226 #define CONFIG_HAS_ETH0
 227 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx        */
 228                                         /*   buffers & descriptors      */
 229 #define CONFIG_NET_MULTI        1
 230 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 231 #define CONFIG_PHY1_ADDR        3
 232
 233 /* USB */
 234 #define CONFIG_USB_OHCI
 235 #define CONFIG_USB_STORAGE
 236
 237 /* Comment this out to enable USB 1.1 device */
 238 #define USB_2_0_DEVICE
 239
 240 /* Partitions */
 241 #define CONFIG_MAC_PARTITION
 242 #define CONFIG_DOS_PARTITION
 243 #define CONFIG_ISO_PARTITION
 244
 245 /*
 246  * BOOTP options
 247  */
 248 #define CONFIG_BOOTP_BOOTFILESIZE
 249 #define CONFIG_BOOTP_BOOTPATH
 250 #define CONFIG_BOOTP_GATEWAY
 251 #define CONFIG_BOOTP_HOSTNAME
 252 #define CONFIG_BOOTP_SUBNETMASK
 253
 254 /*
 255  * Command line configuration.
 256  */
 257 #include <config_cmd_default.h>
 258
 259 #define CONFIG_CMD_ASKENV
 260 #define CONFIG_CMD_DATE
 261 #define CONFIG_CMD_DHCP
 262 #define CONFIG_CMD_DTT
 263 #define CONFIG_CMD_DIAG
 264 #define CONFIG_CMD_EEPROM
 265 #define CONFIG_CMD_ELF
 266 #define CONFIG_CMD_FAT
 267 #define CONFIG_CMD_I2C
 268 #define CONFIG_I2C_CMD_TREE
 269 #define CONFIG_CMD_IRQ
 270 #define CONFIG_CMD_MII
 271 #define CONFIG_CMD_NET
 272 #define CONFIG_CMD_NFS
 273 #define CONFIG_CMD_PCI
 274 #define CONFIG_CMD_PING
 275 #define CONFIG_CMD_REGINFO
 276 #define CONFIG_CMD_SDRAM
 277 #define CONFIG_CMD_USB
 278
 279 /* POST support */
 280 #define CONFIG_POST             (CFG_POST_CACHE    | \
 281                                  CFG_POST_CPU      | \
 282                                  CFG_POST_ECC      | \
 283                                  CFG_POST_ETHER    | \
 284                                  CFG_POST_FPU      | \
 285                                  CFG_POST_I2C      | \
 286                                  CFG_POST_MEMORY   | \
 287                                  CFG_POST_RTC      | \
 288                                  CFG_POST_SPR      | \
 289                                  CFG_POST_UART)
 290
 291 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
 292 #define CONFIG_LOGBUFFER
 293 #define CFG_POST_CACHE_ADDR     0xC8000000      /* free virtual address     */
 294
 295 #define CFG_CONSOLE_IS_IN_ENV   /* Otherwise it catches logbuffer as output */
 296
 297 #define CONFIG_SUPPORT_VFAT
 298
 299 /*
 300  * Miscellaneous configurable options
 301  */
 302 #define CFG_LONGHELP                    /* undef to save memory         */
 303 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 304 #if defined(CONFIG_CMD_KGDB)
 305 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 306 #else
 307 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 308 #endif
 309 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
 310                                         /* Print Buffer Size            */
 311 #define CFG_MAXARGS             16      /* max number of command args   */
 312 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 313
 314 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 315 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 316
 317 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 318 #define CFG_EXTBDINFO           1  /* To use extended board_into (bd_t) */
 319
 320 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 321
 322 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 323 #define CONFIG_LOOPW            1       /* enable loopw command         */
 324 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 325 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 326 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 327
 328 /*
 329  * Korat-specific options
 330  */
 331 #define CFG_KORAT_MAN_RESET_MS  10000   /* timeout for manufacturer reset */
 332
 333 /*
 334  * PCI stuff
 335  */
 336 /* General PCI */
 337 #define CONFIG_PCI                      /* include pci support          */
 338 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 339 #define CFG_PCI_CACHE_LINE_SIZE 0       /* to avoid problems with PNP   */
 340 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 341 #define CFG_PCI_TARGBASE        0x80000000      /* PCIaddr mapped to    */
 342                                                 /*   CFG_PCI_MEMBASE    */
 343 /* Board-specific PCI */
 344 #define CFG_PCI_TARGET_INIT
 345 #define CFG_PCI_MASTER_INIT
 346
 347 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC                         */
 348 #define CFG_PCI_SUBSYS_ID       0xcafe  /* Whatever                     */
 349
 350 /*
 351  * For booting Linux, the board info and command line data have to be in the
 352  * first 8 MB of memory, since this is the maximum mapped by the Linux kernel
 353  * during initialization.
 354  */
 355 #define CFG_BOOTMAPSZ           (8 << 20) /* Initial Memory map for Linux */
 356
 357 /*
 358  * External Bus Controller (EBC) Setup
 359  */
 360
 361 /* Memory Bank 0 (NOR-FLASH) initialization                             */
 362 #if CFG_FLASH0_SIZE == 0x01000000
 363 #define CFG_EBC_PB0AP           0x04017300
 364 #define CFG_EBC_PB0CR           (CFG_FLASH0_ADDR | 0x0009A000)
 365 #elif CFG_FLASH0_SIZE == 0x04000000
 366 #define CFG_EBC_PB0AP           0x04017300
 367 #define CFG_EBC_PB0CR           (CFG_FLASH0_ADDR | 0x000DA000)
 368 #else
 369 #error Unable to configure chip select for current CFG_FLASH0_SIZE
 370 #endif
 371
 372 /* Memory Bank 1 (NOR-FLASH) initialization                             */
 373 #if CFG_FLASH1_MAX_SIZE == 0x08000000
 374 #define CFG_EBC_PB1AP           0x04017300
 375 #define CFG_EBC_PB1CR           (CFG_FLASH1_ADDR | 0x000FA000)
 376 #else
 377 #error Unable to configure chip select for current CFG_FLASH1_MAX_SIZE
 378 #endif
 379
 380 /* Memory Bank 2 (CPLD) initialization                                  */
 381 #define CFG_EBC_PB2AP           0x04017300
 382 #define CFG_EBC_PB2CR           (CFG_CPLD_BASE | 0x00038000)
 383
 384 /*
 385  * GPIO Setup
 386  *
 387  * Korat GPIO usage:
 388  *
 389  *                   Init.
 390  * Pin    Source I/O value Function
 391  * ------ ------ --- ----- ---------------------------------
 392  * GPIO00  Alt1  I/O   x   PerAddr07
 393  * GPIO01  Alt1  I/O   x   PerAddr06
 394  * GPIO02  Alt1  I/O   x   PerAddr05
 395  * GPIO03  GPIO   x    x   GPIO03 to expansion bus connector
 396  * GPIO04  GPIO   x    x   GPIO04 to expansion bus connector
 397  * GPIO05  GPIO   x    x   GPIO05 to expansion bus connector
 398  * GPIO06  Alt1   O    x   PerCS1 (2nd NOR flash)
 399  * GPIO07  Alt1   O    x   PerCS2 (CPLD)
 400  * GPIO08  Alt1   O    x   PerCS3 to expansion bus connector
 401  * GPIO09  Alt1   O    x   PerCS4 to expansion bus connector
 402  * GPIO10  Alt1   O    x   PerCS5 to expansion bus connector
 403  * GPIO11  Alt1   I    x   PerErr
 404  * GPIO12  GPIO   O    0   ATMega !Reset
 405  * GPIO13  GPIO   O    1   SPI Atmega !SS
 406  * GPIO14  GPIO   O    1   Write protect EEPROM #1 (0xA8)
 407  * GPIO15  GPIO   O    0   CPU Run LED !On
 408  * GPIO16  Alt1   O    x   GMC1TxD0
 409  * GPIO17  Alt1   O    x   GMC1TxD1
 410  * GPIO18  Alt1   O    x   GMC1TxD2
 411  * GPIO19  Alt1   O    x   GMC1TxD3
 412  * GPIO20  Alt1   I    x   RejectPkt0
 413  * GPIO21  Alt1   I    x   RejectPkt1
 414  * GPIO22  GPIO   I    x   PGOOD_DDR
 415  * GPIO23  Alt1   O    x   SCPD0
 416  * GPIO24  Alt1   O    x   GMC0TxD2
 417  * GPIO25  Alt1   O    x   GMC0TxD3
 418  * GPIO26  GPIO? I/O   x   IIC0SDA (selected in SDR0_PFC4)
 419  * GPIO27  GPIO   O    0   PHY #0 1000BASE-X select
 420  * GPIO28  GPIO   O    0   PHY #1 1000BASE-X select
 421  * GPIO29  GPIO   I    x   Test jumper !Present
 422  * GPIO30  GPIO   I    x   SFP module #0 !Present
 423  * GPIO31  GPIO   I    x   SFP module #1 !Present
 424  *
 425  * GPIO32  GPIO   O    1   SFP module #0 Tx !Enable
 426  * GPIO33  GPIO   O    1   SFP module #1 Tx !Enable
 427  * GPIO34  Alt2   I    x   !UART1_CTS
 428  * GPIO35  Alt2   O    x   !UART1_RTS
 429  * GPIO36  Alt1   I    x   !UART0_CTS
 430  * GPIO37  Alt1   O    x   !UART0_RTS
 431  * GPIO38  Alt2   O    x   UART1_Tx
 432  * GPIO39  Alt2   I    x   UART1_Rx
 433  * GPIO40  Alt1   I    x   IRQ0 (Ethernet 0)
 434  * GPIO41  Alt1   I    x   IRQ1 (Ethernet 1)
 435  * GPIO42  Alt1   I    x   IRQ2 (PCI interrupt)
 436  * GPIO43  Alt1   I    x   IRQ3 (System Alert from CPLD)
 437  * GPIO44  xxxx   x    x   (grounded through pulldown)
 438  * GPIO45  GPIO   O    0   PHY #0 Enable
 439  * GPIO46  GPIO   O    0   PHY #1 Enable
 440  * GPIO47  GPIO   I    x   Reset switch !Pressed
 441  * GPIO48  GPIO   I    x   Shutdown switch !Pressed
 442  * GPIO49  xxxx   x    x   (reserved for trace port)
 443  *   .      .     .    .               .
 444  *   .      .     .    .               .
 445  *   .      .     .    .               .
 446  * GPIO63  xxxx   x    x   (reserved for trace port)
 447  */
 448
 449 #define CFG_GPIO_ATMEGA_RESET_  12
 450 #define CFG_GPIO_ATMEGA_SS_     13
 451 #define CFG_GPIO_PHY0_FIBER_SEL 27
 452 #define CFG_GPIO_PHY1_FIBER_SEL 28
 453 #define CFG_GPIO_SFP0_PRESENT_  30
 454 #define CFG_GPIO_SFP1_PRESENT_  31
 455 #define CFG_GPIO_SFP0_TX_EN_    32
 456 #define CFG_GPIO_SFP1_TX_EN_    33
 457 #define CFG_GPIO_PHY0_EN        45
 458 #define CFG_GPIO_PHY1_EN        46
 459 #define CFG_GPIO_RESET_PRESSED_ 47
 460
 461 /*
 462  * PPC440 GPIO Configuration
 463  */
 464 #define CFG_4xx_GPIO_TABLE { /*   Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 465 {                                                                                       \
 466 /* GPIO Core 0 */                                                                       \
 467 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 468 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 469 {GPIO0_BASE, GPIO_BI , GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 470 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 471 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 472 {GPIO0_BASE, GPIO_DIS, GPIO_SEL , GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 473 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 474 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 475 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 476 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 477 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 478 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 479 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 480 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO13                                */      \
 481 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14                                */      \
 482 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO15                                */      \
 483 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO16 GMCTxD(4)                      */      \
 484 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO17 GMCTxD(5)                      */      \
 485 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO18 GMCTxD(6)                      */      \
 486 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO19 GMCTxD(7)                      */      \
 487 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 488 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 489 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 490 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 491 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO24 GMCTxD(2)                      */      \
 492 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO25 GMCTxD(3)                      */      \
 493 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 494 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 495 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28                USB2D_TXVALID   */      \
 496 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 497 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 498 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 499 },                                                                                      \
 500 {                                                                                       \
 501 /* GPIO Core 1 */                                                                       \
 502 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 503 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 504 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 505 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 506 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)   UART3_SIN*/ \
 507 {GPIO1_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_1}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 508 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_1}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 509 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 510 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 511 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 512 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 513 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 514 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 515 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 516 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 517 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 518 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 519 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 520 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 521 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 522 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 523 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 524 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 525 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 526 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 527 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 528 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 529 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 530 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 531 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 532 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 533 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 534 }                                                                                       \
 535 }
 536
 537 /*
 538  * Internal Definitions
 539  *
 540  * Boot Flags
 541  */
 542 #define BOOTFLAG_COLD   0x01    /* Normal Power-On: Boot from FLASH     */
 543 #define BOOTFLAG_WARM   0x02    /* Software reboot                      */
 544
 545 #if defined(CONFIG_CMD_KGDB)
 546 #define CONFIG_KGDB_BAUDRATE    230400 /* speed to run kgdb serial port */
 547 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use     */
 548 #endif
 549
 550 /* Pass open firmware flat tree */
 551 #define CONFIG_OF_LIBFDT        1
 552 #define CONFIG_OF_BOARD_SETUP   1
 553
 554 #endif /* __CONFIG_H */