include/configs/kvme080.h

   1 /*
   2  * (C) Copyright 2005
   3  * Sangmoon Kim, dogoil@etinsys.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 #define CONFIG_MPC824X          1
  28 #define CONFIG_MPC8245          1
  29 #define CONFIG_KVME080          1
  30
  31 #define CONFIG_CONS_INDEX       1
  32
  33 #define CONFIG_BAUDRATE         115200
  34
  35 #define CONFIG_BOOTDELAY        5
  36
  37 #define CONFIG_IPADDR           192.168.0.2
  38 #define CONFIG_NETMASK          255.255.255.0
  39 #define CONFIG_SERVERIP         192.168.0.1
  40
  41 #define CONFIG_BOOTARGS \
  42         "console=ttyS0,115200 " \
  43         "root=/dev/nfs rw nfsroot=192.168.0.1:/opt/eldk/ppc_82xx " \
  44         "ip=192.168.0.2:192.168.0.1:192.168.0.1:255.255.255.0:" \
  45         "kvme080:eth0:none " \
  46         "mtdparts=phys_mapped_flash:12m(root),-(kernel)"
  47
  48 #define CONFIG_BOOTCOMMAND \
  49         "tftp 800000 kvme080/uImage; " \
  50         "bootm 800000"
  51
  52 #define CONFIG_LOADADDR         800000
  53
  54 #define CONFIG_BOARD_EARLY_INIT_F
  55 #define CONFIG_BOARD_EARLY_INIT_R
  56 #define CONFIG_MISC_INIT_R
  57
  58 #define CONFIG_LOADS_ECHO       1
  59 #undef  CFG_LOADS_BAUD_CHANGE
  60
  61 #undef  CONFIG_WATCHDOG
  62
  63 #define CONFIG_BOOTP_MASK       (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE)
  64
  65 #define CONFIG_MAC_PARTITION
  66 #define CONFIG_DOS_PARTITION
  67
  68 #define CONFIG_RTC_DS164x
  69
  70 #define CONFIG_COMMANDS         ( CONFIG_CMD_DFL        | \
  71                                   CFG_CMD_ASKENV        | \
  72                                   CFG_CMD_CACHE         | \
  73                                   CFG_CMD_DATE          | \
  74                                   CFG_CMD_DHCP          | \
  75                                   CFG_CMD_DIAG          | \
  76                                   CFG_CMD_EEPROM        | \
  77                                   CFG_CMD_ELF           | \
  78                                   CFG_CMD_I2C           | \
  79                                   CFG_CMD_JFFS2         | \
  80                                   CFG_CMD_NFS           | \
  81                                   CFG_CMD_PCI           | \
  82                                   CFG_CMD_PING          | \
  83                                   CFG_CMD_SDRAM         | \
  84                                   CFG_CMD_SNTP)
  85
  86 #define CONFIG_NETCONSOLE
  87
  88 #include <cmd_confdefs.h>
  89
  90 #define CFG_LONGHELP
  91 #define CFG_PROMPT              "=> "
  92 #define CFG_CBSIZE              256
  93 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)
  94 #define CFG_MAXARGS             16
  95 #define CFG_BARGSIZE            CFG_CBSIZE
  96
  97 #define CFG_MEMTEST_START       0x00400000
  98 #define CFG_MEMTEST_END         0x07C00000
  99
 100 #define CFG_LOAD_ADDR           0x00100000
 101 #define CFG_HZ                  1000
 102
 103 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 104
 105 #define CFG_INIT_RAM_ADDR       0x40000000
 106 #define CFG_INIT_RAM_END        0x1000
 107 #define CFG_GBL_DATA_SIZE       128
 108 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 109
 110 #define CFG_SDRAM_BASE          0x00000000
 111 #define CFG_FLASH_BASE          0x7C000000
 112 #define CFG_EUMB_ADDR           0xFC000000
 113 #define CFG_NVRAM_BASE_ADDR     0xFF000000
 114 #define CFG_NS16550_COM1        0xFF080000
 115 #define CFG_NS16550_COM2        0xFF080010
 116 #define CFG_NS16550_COM3        0xFF080020
 117 #define CFG_NS16550_COM4        0xFF080030
 118 #define CFG_RESET_ADDRESS       0xFFF00100
 119
 120 #define CFG_MAX_RAM_SIZE        0x20000000
 121 #define CFG_FLASH_SIZE          (16 * 1024 * 1024)
 122 #define CFG_NVRAM_SIZE          0x7FFF8
 123
 124 #define CONFIG_VERY_BIG_RAM
 125
 126 #define CFG_MONITOR_LEN         0x00040000
 127 #define CFG_MONITOR_BASE        TEXT_BASE
 128 #define CFG_MALLOC_LEN          (512 << 10)
 129
 130 #define CFG_BOOTMAPSZ           (8 << 20)
 131
 132 #define CFG_FLASH_CFI
 133 #define CFG_FLASH_CFI_DRIVER
 134 #define CFG_FLASH_USE_BUFFER_WRITE
 135 #define CFG_FLASH_PROTECTION
 136 #define CFG_FLASH_EMPTY_INFO
 137 #define CFG_FLASH_PROTECT_CLEAR
 138
 139 #define CFG_MAX_FLASH_BANKS     1
 140 #define CFG_MAX_FLASH_SECT      256
 141
 142 #define CFG_FLASH_ERASE_TOUT    120000
 143 #define CFG_FLASH_WRITE_TOUT    500
 144
 145 #define CFG_JFFS2_FIRST_BANK    0
 146 #define CFG_JFFS2_NUM_BANKS     1
 147
 148 #define CFG_ENV_IS_IN_NVRAM     1
 149 #define CONFIG_ENV_OVERWRITE    1
 150 #define CFG_NVRAM_ACCESS_ROUTINE
 151 #define CFG_ENV_ADDR            CFG_NVRAM_BASE_ADDR
 152 #define CFG_ENV_SIZE            0x400
 153 #define CFG_ENV_OFFSET          0
 154
 155 #define CFG_NS16550
 156 #define CFG_NS16550_SERIAL
 157 #define CFG_NS16550_REG_SIZE    1
 158 #define CFG_NS16550_CLK         14745600
 159
 160 #define CONFIG_PCI
 161 #define CONFIG_PCI_PNP
 162
 163 #define CONFIG_NET_MULTI
 164 #define CONFIG_EEPRO100
 165 #define CONFIG_EEPRO100_SROM_WRITE
 166
 167 #define CFG_RX_ETH_BUFFER       8
 168
 169 #define CONFIG_HARD_I2C         1
 170 #define CFG_I2C_SPEED           400000
 171 #define CFG_I2C_SLAVE           0x7F
 172
 173 #define CFG_I2C_EEPROM_ADDR             0x57
 174 #define CFG_I2C_EEPROM_ADDR_LEN         1
 175 #define CFG_EEPROM_PAGE_WRITE_BITS      3
 176 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10
 177
 178 #define CONFIG_SYS_CLK_FREQ     33333333
 179
 180 #define CFG_CACHELINE_SIZE      32
 181 #if CONFIG_COMMANDS & CFG_CMD_KGDB
 182 #  define CFG_CACHELINE_SHIFT   5
 183 #endif
 184
 185 #define CFG_DLL_EXTEND          0x00
 186 #define CFG_PCI_HOLD_DEL        0x20
 187
 188 #define CFG_ROMNAL              15
 189 #define CFG_ROMFAL              31
 190
 191 #define CFG_REFINT              430
 192
 193 #define CFG_DBUS_SIZE2          1
 194
 195 #define CFG_BSTOPRE             121
 196 #define CFG_REFREC              8
 197 #define CFG_RDLAT               4
 198 #define CFG_PRETOACT            3
 199 #define CFG_ACTTOPRE            5
 200 #define CFG_ACTORW              3
 201 #define CFG_SDMODE_CAS_LAT      3
 202 #define CFG_SDMODE_WRAP         0
 203
 204 #define CFG_REGISTERD_TYPE_BUFFER       1
 205 #define CFG_EXTROM                      1
 206 #define CFG_REGDIMM                     0
 207
 208 #define CFG_BANK0_START         0x00000000
 209 #define CFG_BANK0_END           (0x4000000 - 1)
 210 #define CFG_BANK0_ENABLE        1
 211 #define CFG_BANK1_START         0x04000000
 212 #define CFG_BANK1_END           (0x8000000 - 1)
 213 #define CFG_BANK1_ENABLE        1
 214 #define CFG_BANK2_START         0x3ff00000
 215 #define CFG_BANK2_END           0x3fffffff
 216 #define CFG_BANK2_ENABLE        0
 217 #define CFG_BANK3_START         0x3ff00000
 218 #define CFG_BANK3_END           0x3fffffff
 219 #define CFG_BANK3_ENABLE        0
 220 #define CFG_BANK4_START         0x00000000
 221 #define CFG_BANK4_END           0x00000000
 222 #define CFG_BANK4_ENABLE        0
 223 #define CFG_BANK5_START         0x00000000
 224 #define CFG_BANK5_END           0x00000000
 225 #define CFG_BANK5_ENABLE        0
 226 #define CFG_BANK6_START         0x00000000
 227 #define CFG_BANK6_END           0x00000000
 228 #define CFG_BANK6_ENABLE        0
 229 #define CFG_BANK7_START         0x00000000
 230 #define CFG_BANK7_END           0x00000000
 231 #define CFG_BANK7_ENABLE        0
 232
 233 #define CFG_BANK_ENABLE         0x03
 234
 235 #define CFG_ODCR                0x75
 236 #define CFG_PGMAX               0x32
 237
 238 #define CFG_IBAT0L      (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
 239 #define CFG_IBAT0U      (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
 240
 241 #define CFG_IBAT1L      (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
 242 #define CFG_IBAT1U      (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
 243
 244 #define CFG_IBAT2L      (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 245 #define CFG_IBAT2U      (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 246
 247 #define CFG_IBAT3L      (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
 248 #define CFG_IBAT3U      (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
 249
 250 #define CFG_DBAT0L      CFG_IBAT0L
 251 #define CFG_DBAT0U      CFG_IBAT0U
 252 #define CFG_DBAT1L      CFG_IBAT1L
 253 #define CFG_DBAT1U      CFG_IBAT1U
 254 #define CFG_DBAT2L      CFG_IBAT2L
 255 #define CFG_DBAT2U      CFG_IBAT2U
 256 #define CFG_DBAT3L      CFG_IBAT3L
 257 #define CFG_DBAT3U      CFG_IBAT3U
 258
 259 #define BOOTFLAG_COLD   0x01
 260 #define BOOTFLAG_WARM   0x02
 261
 262 #endif  /* __CONFIG_H */