include/configs/kzm9g.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright (C) 2012 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com>
   4  * Copyright (C) 2012 Renesas Solutions Corp.
   5  */
   6
   7 #ifndef __KZM9G_H
   8 #define __KZM9G_H
   9
  10 #define CONFIG_SH73A0
  11 #define CONFIG_MACH_TYPE MACH_TYPE_KZM9G
  12
  13 #include <asm/arch/rmobile.h>
  14
  15 #define CONFIG_CMDLINE_TAG
  16 #define CONFIG_SETUP_MEMORY_TAGS
  17 #define CONFIG_INITRD_TAG
  18
  19 /* MEMORY */
  20 #define KZM_SDRAM_BASE  (0x40000000)
  21 #define PHYS_SDRAM              KZM_SDRAM_BASE
  22 #define PHYS_SDRAM_SIZE         (512 * 1024 * 1024)
  23
  24 /* NOR Flash */
  25 #define KZM_FLASH_BASE  (0x00000000)
  26 #define CONFIG_SYS_FLASH_BASE           (KZM_FLASH_BASE)
  27 #define CONFIG_SYS_FLASH_CFI_WIDTH      (FLASH_CFI_16BIT)
  28 #define CONFIG_SYS_MAX_FLASH_BANKS      (1)
  29 #define CONFIG_SYS_MAX_FLASH_SECT       (512)
  30
  31 /* prompt */
  32 #define CONFIG_SYS_PBSIZE               256
  33 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 }
  34
  35 /* SCIF */
  36 #define CONFIG_CONS_SCIF4
  37
  38 #define CONFIG_SYS_MEMTEST_START        (KZM_SDRAM_BASE)
  39 #define CONFIG_SYS_MEMTEST_END \
  40         (CONFIG_SYS_MEMTEST_START + (60 * 1024 * 1024))
  41 #undef  CONFIG_SYS_MEMTEST_SCRATCH
  42 #undef  CONFIG_SYS_LOADS_BAUD_CHANGE
  43
  44 #define CONFIG_SYS_INIT_RAM_ADDR        (0xE5600000) /* on MERAM */
  45 #define CONFIG_SYS_INIT_RAM_SIZE        (0x10000)
  46 #define LOW_LEVEL_MERAM_STACK           (CONFIG_SYS_INIT_RAM_ADDR - 4)
  47 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_INIT_RAM_ADDR + \
  48                                          CONFIG_SYS_INIT_RAM_SIZE - \
  49                                          GENERATED_GBL_DATA_SIZE)
  50 #define CONFIG_SDRAM_OFFSET_FOR_RT      (16 * 1024 * 1024)
  51 #define CONFIG_SYS_SDRAM_BASE   (KZM_SDRAM_BASE + CONFIG_SDRAM_OFFSET_FOR_RT)
  52 #define CONFIG_SYS_SDRAM_SIZE   (PHYS_SDRAM_SIZE - CONFIG_SDRAM_OFFSET_FOR_RT)
  53 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_SDRAM_BASE + 32 * 1024 * 1024)
  54
  55 #define CONFIG_SYS_MONITOR_BASE (KZM_FLASH_BASE)
  56 #define CONFIG_SYS_MALLOC_LEN   (CONFIG_ENV_SIZE + 128 * 1024)
  57 #define CONFIG_SYS_BOOTMAPSZ    (8 * 1024 * 1024)
  58
  59 #define CONFIG_STANDALONE_LOAD_ADDR     0x41000000
  60
  61 /* FLASH */
  62 #undef  CONFIG_SYS_FLASH_QUIET_TEST
  63 #define CONFIG_SYS_FLASH_EMPTY_INFO
  64 #define FLASH_SECTOR_SIZE       (256 * 1024)    /* 256 KB sectors */
  65
  66 /* Timeout for Flash erase operations (in ms) */
  67 #define CONFIG_SYS_FLASH_ERASE_TOUT     (3 * 1000)
  68 /* Timeout for Flash write operations (in ms) */
  69 #define CONFIG_SYS_FLASH_WRITE_TOUT     (3 * 1000)
  70 /* Timeout for Flash set sector lock bit operations (in ms) */
  71 #define CONFIG_SYS_FLASH_LOCK_TOUT              (3 * 1000)
  72 /* Timeout for Flash clear lock bit operations (in ms) */
  73 #define CONFIG_SYS_FLASH_UNLOCK_TOUT    (3 * 1000)
  74
  75 #undef  CONFIG_SYS_DIRECT_FLASH_TFTP
  76
  77 /* GPIO / PFC */
  78 #define CONFIG_SH_GPIO_PFC
  79
  80 /* Clock */
  81 #define CONFIG_GLOBAL_TIMER
  82 #define CONFIG_SYS_CLK_FREQ     (48000000)
  83 #define CONFIG_SYS_CPU_CLK      (1196000000)
  84 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
  85 #define TMU_CLK_DIVIDER         (4)     /* 4 (default), 16, 64, 256 or 1024 */
  86
  87 #define CONFIG_NFS_TIMEOUT 10000UL
  88
  89 /* I2C */
  90 #define CONFIG_SYS_I2C
  91 #define CONFIG_SYS_I2C_SH
  92 #define CONFIG_SYS_I2C_SH_NUM_CONTROLLERS 5
  93 #define CONFIG_SYS_I2C_SH_BASE0 0xE6820000
  94 #define CONFIG_SYS_I2C_SH_SPEED0        100000
  95 #define CONFIG_SYS_I2C_SH_BASE1 0xE6822000
  96 #define CONFIG_SYS_I2C_SH_SPEED1        100000
  97 #define CONFIG_SYS_I2C_SH_BASE2 0xE6824000
  98 #define CONFIG_SYS_I2C_SH_SPEED2        100000
  99 #define CONFIG_SYS_I2C_SH_BASE3 0xE6826000
 100 #define CONFIG_SYS_I2C_SH_SPEED3        100000
 101 #define CONFIG_SYS_I2C_SH_BASE4 0xE6828000
 102 #define CONFIG_SYS_I2C_SH_SPEED4        100000
 103 #define CONFIG_SH_I2C_8BIT
 104 #define CONFIG_SH_I2C_DATA_HIGH 4
 105 #define CONFIG_SH_I2C_DATA_LOW  5
 106 #define CONFIG_SH_I2C_CLOCK     104000000 /* 104 MHz */
 107
 108 #endif /* __KZM9G_H */