include/configs/logodl.h

   1 /*
   2  * (C) Copyright 2003
   3  * Robert Schwebel, Pengutronix, r.schwebel@pengutronix.de.
   4  *
   5  * Configuration for the Logotronic DL board.
   6  *
   7  * See file CREDITS for list of people who contributed to this
   8  * project.
   9  *
  10  * This program is free software; you can redistribute it and/or
  11  * modify it under the terms of the GNU General Public License as
  12  * published by the Free Software Foundation; either version 2 of
  13  * the License, or (at your option) any later version.
  14  *
  15  * This program is distributed in the hope that it will be useful,
  16  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  18  * GNU General Public License for more details.
  19  *
  20  * You should have received a copy of the GNU General Public License
  21  * along with this program; if not, write to the Free Software
  22  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23  * MA 02111-1307 USA
  24  */
  25
  26 /*
  27  * include/configs/logodl.h - configuration options, board specific
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 /*
  34  * High Level Configuration Options
  35  * (easy to change)
  36  */
  37 #define CONFIG_PXA250           1       /* This is an PXA250 CPU            */
  38 #define CONFIG_GEALOG           1       /* on a Logotronic GEALOG SG board  */
  39
  40 #undef CONFIG_USE_IRQ                   /* we don't need IRQ/FIQ stuff      */
  41                                         /* for timer/console/ethernet       */
  42
  43 /* we will never enable dcache, because we have to setup MMU first */
  44 #define CONFIG_SYS_NO_DCACHE
  45
  46 /*
  47  * Hardware drivers
  48  */
  49
  50 /*
  51  * select serial console configuration
  52  */
  53 #define CONFIG_PXA_SERIAL
  54 #define CONFIG_FFUART           1       /* we use FFUART                    */
  55
  56 /* allow to overwrite serial and ethaddr */
  57 #define CONFIG_ENV_OVERWRITE
  58
  59 #define CONFIG_BAUDRATE         19200
  60 #undef CONFIG_MISC_INIT_R               /* FIXME: misc_init_r() missing     */
  61
  62
  63 /*
  64  * BOOTP options
  65  */
  66 #define CONFIG_BOOTP_BOOTFILESIZE
  67 #define CONFIG_BOOTP_BOOTPATH
  68 #define CONFIG_BOOTP_GATEWAY
  69 #define CONFIG_BOOTP_HOSTNAME
  70
  71
  72 /*
  73  * Command line configuration.
  74  */
  75 #define CONFIG_CMD_ASKENV
  76 #define CONFIG_CMD_ECHO
  77 #define CONFIG_CMD_SAVEENV
  78 #define CONFIG_CMD_FLASH
  79 #define CONFIG_CMD_MEMORY
  80 #define CONFIG_CMD_RUN
  81
  82
  83 #define CONFIG_BOOTDELAY        3
  84 /* #define CONFIG_BOOTARGS      "root=/dev/nfs ip=bootp console=ttyS0,19200" */
  85 #define CONFIG_BOOTARGS         "console=ttyS0,19200"
  86 #define CONFIG_ETHADDR          FF:FF:FF:FF:FF:FF
  87 #define CONFIG_NETMASK          255.255.255.0
  88 #define CONFIG_IPADDR           192.168.1.56
  89 #define CONFIG_SERVERIP         192.168.1.2
  90 #define CONFIG_BOOTCOMMAND      "bootm 0x40000"
  91 #define CONFIG_SHOW_BOOT_PROGRESS
  92
  93 #define CONFIG_CMDLINE_TAG      1
  94
  95 /*
  96  * Miscellaneous configurable options
  97  */
  98
  99 /*
 100  * Size of malloc() pool; this lives below the uppermost 128 KiB which are
 101  * used for the RAM copy of the uboot code
 102  *
 103  */
 104 #define CONFIG_SYS_MALLOC_LEN           (256*1024)
 105
 106 #define CONFIG_SYS_LONGHELP                             /* undef to save memory         */
 107 #define CONFIG_SYS_PROMPT               "uboot> "       /* Monitor Command Prompt       */
 108 #define CONFIG_SYS_CBSIZE               256             /* Console I/O Buffer Size      */
 109 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
 110 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 111 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 112
 113 #define CONFIG_SYS_MEMTEST_START        0x08000000      /* memtest works on             */
 114 #define CONFIG_SYS_MEMTEST_END         0x0800ffff       /* 64 KiB                       */
 115
 116 #define CONFIG_SYS_LOAD_ADDR           0x08000000      /* load kernel to this address   */
 117
 118 #define CONFIG_SYS_HZ                   1000
 119                                                 /* RS: the oscillator is actually 3680130?? */
 120
 121 #define CONFIG_SYS_CPUSPEED            0x141           /* set core clock to 200/200/100 MHz */
 122                                                 /* 0101000001 */
 123                                                 /*      ^^^^^ Memory Speed 99.53 MHz         */
 124                                                 /*    ^^      Run Mode Speed = 2x Mem Speed  */
 125                                                 /* ^^         Turbo Mode Sp. = 1x Run M. Sp. */
 126
 127 #define CONFIG_SYS_MONITOR_LEN          0x20000         /* 128 KiB */
 128
 129                                                 /* valid baudrates */
 130 #define CONFIG_SYS_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 131
 132 /*
 133  * SMSC91C111 Network Card
 134  */
 135 #if 0
 136 #define CONFIG_NET_MULTI
 137 #define CONFIG_SMC91111         1
 138 #define CONFIG_SMC91111_BASE            0x10000000 /* chip select 4         */
 139 #undef  CONFIG_SMC_USE_32_BIT                      /* 16 bit bus access     */
 140 #undef  CONFIG_SMC_91111_EXT_PHY                   /* we use internal phy   */
 141 #undef  CONFIG_SHOW_ACTIVITY
 142 #define CONFIG_NET_RETRY_COUNT          10         /* # of retries          */
 143 #endif
 144
 145 /*
 146  * Stack sizes
 147  *
 148  * The stack sizes are set up in start.S using the settings below
 149  */
 150 #define CONFIG_STACKSIZE        (128*1024)      /* regular stack */
 151 #ifdef  CONFIG_USE_IRQ
 152 #define CONFIG_STACKSIZE_IRQ    (4*1024)        /* IRQ stack */
 153 #define CONFIG_STACKSIZE_FIQ    (4*1024)        /* FIQ stack */
 154 #endif
 155
 156 /*
 157  * Physical Memory Map
 158  */
 159 #define CONFIG_NR_DRAM_BANKS    1               /* we have 1 bank of RAM    */
 160 #define PHYS_SDRAM_1            0x08000000      /* SRAM Bank #1             */
 161 #define PHYS_SDRAM_1_SIZE       (4*1024*1024)   /* 4 MB                     */
 162
 163 #define PHYS_FLASH_1            0x00000000      /* Flash Bank #1            */
 164 #define PHYS_FLASH_2            0x01000000      /* Flash Bank #2            */
 165 #define PHYS_FLASH_SIZE         (32*1024*1024)  /* 32 MB                    */
 166
 167 #define CONFIG_SYS_DRAM_BASE            PHYS_SDRAM_1    /* RAM starts here          */
 168 #define CONFIG_SYS_DRAM_SIZE            PHYS_SDRAM_1_SIZE
 169
 170 #define CONFIG_SYS_FLASH_BASE          PHYS_FLASH_1
 171
 172
 173 /*
 174  * GPIO settings
 175  *
 176  * GP?? == FOOBAR    is 0/1
 177  */
 178
 179 #define _BIT0       0x00000001
 180 #define _BIT1       0x00000002
 181 #define _BIT2       0x00000004
 182 #define _BIT3       0x00000008
 183
 184 #define _BIT4       0x00000010
 185 #define _BIT5       0x00000020
 186 #define _BIT6       0x00000040
 187 #define _BIT7       0x00000080
 188
 189 #define _BIT8       0x00000100
 190 #define _BIT9       0x00000200
 191 #define _BIT10      0x00000400
 192 #define _BIT11      0x00000800
 193
 194 #define _BIT12      0x00001000
 195 #define _BIT13      0x00002000
 196 #define _BIT14      0x00004000
 197 #define _BIT15      0x00008000
 198
 199 #define _BIT16      0x00010000
 200 #define _BIT17      0x00020000
 201 #define _BIT18      0x00040000
 202 #define _BIT19      0x00080000
 203
 204 #define _BIT20      0x00100000
 205 #define _BIT21      0x00200000
 206 #define _BIT22      0x00400000
 207 #define _BIT23      0x00800000
 208
 209 #define _BIT24      0x01000000
 210 #define _BIT25      0x02000000
 211 #define _BIT26      0x04000000
 212 #define _BIT27      0x08000000
 213
 214 #define _BIT28      0x10000000
 215 #define _BIT29      0x20000000
 216 #define _BIT30      0x40000000
 217 #define _BIT31      0x80000000
 218
 219
 220 #define CONFIG_SYS_LED_A_BIT           (_BIT18)
 221 #define CONFIG_SYS_LED_A_SR            GPSR0
 222 #define CONFIG_SYS_LED_A_CR            GPCR0
 223
 224 #define CONFIG_SYS_LED_B_BIT           (_BIT16)
 225 #define CONFIG_SYS_LED_B_SR            GPSR1
 226 #define CONFIG_SYS_LED_B_CR            GPCR1
 227
 228
 229 /* LED A: off, LED B: off */
 230 #define CONFIG_SYS_GPSR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT18)
 231 #define CONFIG_SYS_GPSR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
 232 #define CONFIG_SYS_GPSR2_VAL       (_BIT14+_BIT15+_BIT16)
 233
 234 #define CONFIG_SYS_GPCR0_VAL       0x00000000
 235 #define CONFIG_SYS_GPCR1_VAL       0x00000000
 236 #define CONFIG_SYS_GPCR2_VAL       0x00000000
 237
 238 #define CONFIG_SYS_GPDR0_VAL       (_BIT1+_BIT6+_BIT8+_BIT9+_BIT11+_BIT15+_BIT16+_BIT17+_BIT18)
 239 #define CONFIG_SYS_GPDR1_VAL       (_BIT0+_BIT1+_BIT16+_BIT24+_BIT25  +_BIT7+_BIT8+_BIT9+_BIT11+_BIT13)
 240 #define CONFIG_SYS_GPDR2_VAL       (_BIT14+_BIT15+_BIT16)
 241
 242 #define CONFIG_SYS_GAFR0_L_VAL     (_BIT22+_BIT24+_BIT31)
 243 #define CONFIG_SYS_GAFR0_U_VAL     (_BIT15+_BIT17+_BIT19+\
 244                              _BIT20+_BIT22+_BIT24+_BIT26+_BIT29+_BIT31)
 245 #define CONFIG_SYS_GAFR1_L_VAL     (_BIT3+_BIT4+_BIT6+_BIT8+_BIT10+_BIT12+_BIT15+_BIT17+_BIT19+\
 246                              _BIT20+_BIT23+_BIT24+_BIT27+_BIT28+_BIT31)
 247 #define CONFIG_SYS_GAFR1_U_VAL     (_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
 248 #define CONFIG_SYS_GAFR2_L_VAL     (_BIT1+_BIT3+_BIT5+_BIT7+_BIT9+_BIT11+_BIT13+_BIT15+_BIT17+\
 249                              _BIT19+_BIT21+_BIT23+_BIT25+_BIT27+_BIT29+_BIT31)
 250 #define CONFIG_SYS_GAFR2_U_VAL     (_BIT1)
 251
 252 #define CONFIG_SYS_PSSR_VAL        (0x20)
 253
 254 /*
 255  * Memory settings
 256  */
 257 #define CONFIG_SYS_MSC0_VAL     0x123c2980
 258 #define CONFIG_SYS_MSC1_VAL     0x123c2661
 259 #define CONFIG_SYS_MSC2_VAL     0x7ff87ff8
 260
 261
 262 /* no sdram/pcmcia here */
 263 #define CONFIG_SYS_MDCNFG_VAL           0x00000000
 264 #define CONFIG_SYS_MDREFR_VAL           0x00000000
 265 #define CONFIG_SYS_MDREFR_VAL_100       0x00000000
 266 #define CONFIG_SYS_MDMRS_VAL            0x00000000
 267
 268 /* only SRAM */
 269 #define SXCNFG_SETTINGS 0x00000000
 270
 271 /*
 272  * PCMCIA and CF Interfaces
 273  */
 274
 275 #define CONFIG_SYS_MECR_VAL        0x00000000
 276 #define CONFIG_SYS_MCMEM0_VAL      0x00010504
 277 #define CONFIG_SYS_MCMEM1_VAL      0x00010504
 278 #define CONFIG_SYS_MCATT0_VAL      0x00010504
 279 #define CONFIG_SYS_MCATT1_VAL      0x00010504
 280 #define CONFIG_SYS_MCIO0_VAL       0x00004715
 281 #define CONFIG_SYS_MCIO1_VAL       0x00004715
 282
 283
 284 /*
 285  * FLASH and environment organization
 286  */
 287 #define CONFIG_SYS_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 288 #define CONFIG_SYS_MAX_FLASH_SECT      128  /* max number of sectors on one chip    */
 289
 290 /* timeout values are in ticks */
 291 #define CONFIG_SYS_FLASH_ERASE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 292 #define CONFIG_SYS_FLASH_WRITE_TOUT    (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 293
 294 /* FIXME */
 295 #define CONFIG_ENV_IS_IN_FLASH  1
 296 #define CONFIG_ENV_ADDR            (PHYS_FLASH_1 + 0x1C000)        /* Addr of Environment Sector   */
 297 #define CONFIG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 298
 299 #endif  /* __CONFIG_H */