]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/ls1021aqds.h
common/board_f.c: modify the macro to use get_clocks() more common
[people/ms/u-boot.git] / include / configs / ls1021aqds.h
1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_LS102XA
11
12 #define CONFIG_ARMV7_PSCI
13
14 #define CONFIG_FSL_CLK
15
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
18
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
21
22 #define CONFIG_DEEP_SLEEP
23 #if defined(CONFIG_DEEP_SLEEP)
24 #define CONFIG_SILENT_CONSOLE
25 #endif
26
27 /*
28 * Size of malloc() pool
29 */
30 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
31
32 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
33 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
34
35 /*
36 * Generic Timer Definitions
37 */
38 #define GENERIC_TIMER_CLK 12500000
39
40 #ifndef __ASSEMBLY__
41 unsigned long get_board_sys_clk(void);
42 unsigned long get_board_ddr_clk(void);
43 #endif
44
45 #ifdef CONFIG_QSPI_BOOT
46 #define CONFIG_SYS_CLK_FREQ 100000000
47 #define CONFIG_DDR_CLK_FREQ 100000000
48 #define CONFIG_QIXIS_I2C_ACCESS
49 #else
50 #define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
51 #define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
52 #endif
53
54 #ifdef CONFIG_RAMBOOT_PBL
55 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021aqds/ls102xa_pbi.cfg
56 #endif
57
58 #ifdef CONFIG_SD_BOOT
59 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
60 #define CONFIG_SPL_FRAMEWORK
61 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
62 #define CONFIG_SPL_LIBCOMMON_SUPPORT
63 #define CONFIG_SPL_LIBGENERIC_SUPPORT
64 #define CONFIG_SPL_ENV_SUPPORT
65 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
66 #define CONFIG_SPL_I2C_SUPPORT
67 #define CONFIG_SPL_WATCHDOG_SUPPORT
68 #define CONFIG_SPL_SERIAL_SUPPORT
69 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
70 #define CONFIG_SPL_MMC_SUPPORT
71 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
72 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
73
74 #define CONFIG_SPL_TEXT_BASE 0x10000000
75 #define CONFIG_SPL_MAX_SIZE 0x1a000
76 #define CONFIG_SPL_STACK 0x1001d000
77 #define CONFIG_SPL_PAD_TO 0x1c000
78 #define CONFIG_SYS_TEXT_BASE 0x82000000
79
80 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
81 CONFIG_SYS_MONITOR_LEN)
82 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
83 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
84 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
85 #define CONFIG_SYS_MONITOR_LEN 0x80000
86 #endif
87
88 #ifdef CONFIG_QSPI_BOOT
89 #define CONFIG_SYS_TEXT_BASE 0x40010000
90 #define CONFIG_SYS_NO_FLASH
91 #endif
92
93 #ifdef CONFIG_NAND_BOOT
94 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021aqds/ls102xa_rcw_nand.cfg
95 #define CONFIG_SPL_FRAMEWORK
96 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
97 #define CONFIG_SPL_LIBCOMMON_SUPPORT
98 #define CONFIG_SPL_LIBGENERIC_SUPPORT
99 #define CONFIG_SPL_ENV_SUPPORT
100 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
101 #define CONFIG_SPL_I2C_SUPPORT
102 #define CONFIG_SPL_WATCHDOG_SUPPORT
103 #define CONFIG_SPL_SERIAL_SUPPORT
104 #define CONFIG_SPL_NAND_SUPPORT
105 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
106
107 #define CONFIG_SPL_TEXT_BASE 0x10000000
108 #define CONFIG_SPL_MAX_SIZE 0x1a000
109 #define CONFIG_SPL_STACK 0x1001d000
110 #define CONFIG_SPL_PAD_TO 0x1c000
111 #define CONFIG_SYS_TEXT_BASE 0x82000000
112
113 #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10)
114 #define CONFIG_SYS_NAND_U_BOOT_OFFS CONFIG_SPL_PAD_TO
115 #define CONFIG_SYS_NAND_PAGE_SIZE 2048
116 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
117 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
118
119 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
120 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
121 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
122 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
123 #define CONFIG_SYS_MONITOR_LEN 0x80000
124 #endif
125
126 #ifndef CONFIG_SYS_TEXT_BASE
127 #define CONFIG_SYS_TEXT_BASE 0x60100000
128 #endif
129
130 #define CONFIG_NR_DRAM_BANKS 1
131
132 #define CONFIG_DDR_SPD
133 #define SPD_EEPROM_ADDRESS 0x51
134 #define CONFIG_SYS_SPD_BUS_NUM 0
135
136 #define CONFIG_FSL_DDR_INTERACTIVE /* Interactive debugging */
137 #ifndef CONFIG_SYS_FSL_DDR4
138 #define CONFIG_SYS_FSL_DDR3 /* Use DDR3 memory */
139 #define CONFIG_SYS_DDR_RAW_TIMING
140 #endif
141 #define CONFIG_DIMM_SLOTS_PER_CTLR 1
142 #define CONFIG_CHIP_SELECTS_PER_CTRL 4
143
144 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
145 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
146
147 #define CONFIG_DDR_ECC
148 #ifdef CONFIG_DDR_ECC
149 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
150 #define CONFIG_MEM_INIT_VALUE 0xdeadbeef
151 #endif
152
153 #define CONFIG_SYS_HAS_SERDES
154
155 #define CONFIG_FSL_CAAM /* Enable CAAM */
156
157 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
158 !defined(CONFIG_QSPI_BOOT)
159 #define CONFIG_U_QE
160 #endif
161
162 /*
163 * IFC Definitions
164 */
165 #ifndef CONFIG_QSPI_BOOT
166 #define CONFIG_FSL_IFC
167 #define CONFIG_SYS_FLASH_BASE 0x60000000
168 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
169
170 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
171 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
172 CSPR_PORT_SIZE_16 | \
173 CSPR_MSEL_NOR | \
174 CSPR_V)
175 #define CONFIG_SYS_NOR1_CSPR_EXT (0x0)
176 #define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
177 + 0x8000000) | \
178 CSPR_PORT_SIZE_16 | \
179 CSPR_MSEL_NOR | \
180 CSPR_V)
181 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
182
183 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
184 CSOR_NOR_TRHZ_80)
185 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
186 FTIM0_NOR_TEADC(0x5) | \
187 FTIM0_NOR_TEAHC(0x5))
188 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
189 FTIM1_NOR_TRAD_NOR(0x1a) | \
190 FTIM1_NOR_TSEQRAD_NOR(0x13))
191 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
192 FTIM2_NOR_TCH(0x4) | \
193 FTIM2_NOR_TWPH(0xe) | \
194 FTIM2_NOR_TWP(0x1c))
195 #define CONFIG_SYS_NOR_FTIM3 0
196
197 #define CONFIG_FLASH_CFI_DRIVER
198 #define CONFIG_SYS_FLASH_CFI
199 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
200 #define CONFIG_SYS_FLASH_QUIET_TEST
201 #define CONFIG_FLASH_SHOW_PROGRESS 45
202 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
203 #define CONFIG_SYS_WRITE_SWAPPED_DATA
204
205 #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
206 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
207 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
208 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
209
210 #define CONFIG_SYS_FLASH_EMPTY_INFO
211 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS, \
212 CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
213
214 /*
215 * NAND Flash Definitions
216 */
217 #define CONFIG_NAND_FSL_IFC
218
219 #define CONFIG_SYS_NAND_BASE 0x7e800000
220 #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
221
222 #define CONFIG_SYS_NAND_CSPR_EXT (0x0)
223
224 #define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
225 | CSPR_PORT_SIZE_8 \
226 | CSPR_MSEL_NAND \
227 | CSPR_V)
228 #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
229 #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
230 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
231 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
232 | CSOR_NAND_RAL_3 /* RAL = 3 Bytes */ \
233 | CSOR_NAND_PGS_2K /* Page Size = 2K */ \
234 | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \
235 | CSOR_NAND_PB(64)) /* 64 Pages Per Block */
236
237 #define CONFIG_SYS_NAND_ONFI_DETECTION
238
239 #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x7) | \
240 FTIM0_NAND_TWP(0x18) | \
241 FTIM0_NAND_TWCHT(0x7) | \
242 FTIM0_NAND_TWH(0xa))
243 #define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
244 FTIM1_NAND_TWBE(0x39) | \
245 FTIM1_NAND_TRR(0xe) | \
246 FTIM1_NAND_TRP(0x18))
247 #define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0xf) | \
248 FTIM2_NAND_TREH(0xa) | \
249 FTIM2_NAND_TWHRE(0x1e))
250 #define CONFIG_SYS_NAND_FTIM3 0x0
251
252 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
253 #define CONFIG_SYS_MAX_NAND_DEVICE 1
254 #define CONFIG_CMD_NAND
255
256 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
257 #endif
258
259 /*
260 * QIXIS Definitions
261 */
262 #define CONFIG_FSL_QIXIS
263
264 #ifdef CONFIG_FSL_QIXIS
265 #define QIXIS_BASE 0x7fb00000
266 #define QIXIS_BASE_PHYS QIXIS_BASE
267 #define CONFIG_SYS_I2C_FPGA_ADDR 0x66
268 #define QIXIS_LBMAP_SWITCH 6
269 #define QIXIS_LBMAP_MASK 0x0f
270 #define QIXIS_LBMAP_SHIFT 0
271 #define QIXIS_LBMAP_DFLTBANK 0x00
272 #define QIXIS_LBMAP_ALTBANK 0x04
273 #define QIXIS_RST_CTL_RESET 0x44
274 #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
275 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21
276 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
277
278 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
279 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
280 CSPR_PORT_SIZE_8 | \
281 CSPR_MSEL_GPCM | \
282 CSPR_V)
283 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
284 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
285 CSOR_NOR_NOR_MODE_AVD_NOR | \
286 CSOR_NOR_TRHZ_80)
287
288 /*
289 * QIXIS Timing parameters for IFC GPCM
290 */
291 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xe) | \
292 FTIM0_GPCM_TEADC(0xe) | \
293 FTIM0_GPCM_TEAHC(0xe))
294 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xe) | \
295 FTIM1_GPCM_TRAD(0x1f))
296 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xe) | \
297 FTIM2_GPCM_TCH(0xe) | \
298 FTIM2_GPCM_TWP(0xf0))
299 #define CONFIG_SYS_FPGA_FTIM3 0x0
300 #endif
301
302 #if defined(CONFIG_NAND_BOOT)
303 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
304 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
305 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
306 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
307 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
308 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
309 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
310 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
311 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR0_CSPR_EXT
312 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR0_CSPR
313 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
314 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
315 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
316 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
317 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
318 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
319 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
320 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
321 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
322 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
323 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
324 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
325 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
326 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
327 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
328 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
329 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
330 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
331 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
332 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
333 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
334 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
335 #else
336 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
337 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
338 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
339 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
340 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
341 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
342 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
343 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
344 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NOR1_CSPR_EXT
345 #define CONFIG_SYS_CSPR1 CONFIG_SYS_NOR1_CSPR
346 #define CONFIG_SYS_AMASK1 CONFIG_SYS_NOR_AMASK
347 #define CONFIG_SYS_CSOR1 CONFIG_SYS_NOR_CSOR
348 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NOR_FTIM0
349 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NOR_FTIM1
350 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NOR_FTIM2
351 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NOR_FTIM3
352 #define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NAND_CSPR_EXT
353 #define CONFIG_SYS_CSPR2 CONFIG_SYS_NAND_CSPR
354 #define CONFIG_SYS_AMASK2 CONFIG_SYS_NAND_AMASK
355 #define CONFIG_SYS_CSOR2 CONFIG_SYS_NAND_CSOR
356 #define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NAND_FTIM0
357 #define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NAND_FTIM1
358 #define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NAND_FTIM2
359 #define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NAND_FTIM3
360 #define CONFIG_SYS_CSPR3_EXT CONFIG_SYS_FPGA_CSPR_EXT
361 #define CONFIG_SYS_CSPR3 CONFIG_SYS_FPGA_CSPR
362 #define CONFIG_SYS_AMASK3 CONFIG_SYS_FPGA_AMASK
363 #define CONFIG_SYS_CSOR3 CONFIG_SYS_FPGA_CSOR
364 #define CONFIG_SYS_CS3_FTIM0 CONFIG_SYS_FPGA_FTIM0
365 #define CONFIG_SYS_CS3_FTIM1 CONFIG_SYS_FPGA_FTIM1
366 #define CONFIG_SYS_CS3_FTIM2 CONFIG_SYS_FPGA_FTIM2
367 #define CONFIG_SYS_CS3_FTIM3 CONFIG_SYS_FPGA_FTIM3
368 #endif
369
370 /*
371 * Serial Port
372 */
373 #ifdef CONFIG_LPUART
374 #define CONFIG_FSL_LPUART
375 #define CONFIG_LPUART_32B_REG
376 #else
377 #define CONFIG_CONS_INDEX 1
378 #define CONFIG_SYS_NS16550
379 #define CONFIG_SYS_NS16550_SERIAL
380 #define CONFIG_SYS_NS16550_REG_SIZE 1
381 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
382 #endif
383
384 #define CONFIG_BAUDRATE 115200
385
386 /*
387 * I2C
388 */
389 #define CONFIG_CMD_I2C
390 #define CONFIG_SYS_I2C
391 #define CONFIG_SYS_I2C_MXC
392 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
393 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
394 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
395
396 /*
397 * I2C bus multiplexer
398 */
399 #define I2C_MUX_PCA_ADDR_PRI 0x77
400 #define I2C_MUX_CH_DEFAULT 0x8
401 #define I2C_MUX_CH_CH7301 0xC
402
403 /*
404 * MMC
405 */
406 #define CONFIG_MMC
407 #define CONFIG_CMD_MMC
408 #define CONFIG_FSL_ESDHC
409 #define CONFIG_GENERIC_MMC
410
411 #define CONFIG_CMD_FAT
412 #define CONFIG_DOS_PARTITION
413
414 /* SPI */
415 #ifdef CONFIG_QSPI_BOOT
416 /* QSPI */
417 #define CONFIG_FSL_QSPI
418 #define QSPI0_AMBA_BASE 0x40000000
419 #define FSL_QSPI_FLASH_SIZE (1 << 24)
420 #define FSL_QSPI_FLASH_NUM 2
421 #define CONFIG_SPI_FLASH_SPANSION
422
423 /* DSPI */
424 #define CONFIG_FSL_DSPI
425
426 /* DM SPI */
427 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
428 #define CONFIG_CMD_SF
429 #define CONFIG_DM_SPI_FLASH
430 #define CONFIG_SPI_FLASH_DATAFLASH
431 #endif
432 #endif
433
434 /*
435 * USB
436 */
437 /* EHCI Support - disbaled by default */
438 /*#define CONFIG_HAS_FSL_DR_USB*/
439
440 #ifdef CONFIG_HAS_FSL_DR_USB
441 #define CONFIG_USB_EHCI
442 #define CONFIG_USB_EHCI_FSL
443 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
444 #endif
445
446 /*XHCI Support - enabled by default*/
447 #define CONFIG_HAS_FSL_XHCI_USB
448
449 #ifdef CONFIG_HAS_FSL_XHCI_USB
450 #define CONFIG_USB_XHCI_FSL
451 #define CONFIG_USB_XHCI_DWC3
452 #define CONFIG_USB_XHCI
453 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
454 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
455 #endif
456
457 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
458 #define CONFIG_CMD_USB
459 #define CONFIG_USB_STORAGE
460 #define CONFIG_CMD_EXT2
461 #endif
462
463 /*
464 * Video
465 */
466 #define CONFIG_FSL_DCU_FB
467
468 #ifdef CONFIG_FSL_DCU_FB
469 #define CONFIG_VIDEO
470 #define CONFIG_CMD_BMP
471 #define CONFIG_CFB_CONSOLE
472 #define CONFIG_VGA_AS_SINGLE_DEVICE
473 #define CONFIG_VIDEO_LOGO
474 #define CONFIG_VIDEO_BMP_LOGO
475
476 #define CONFIG_FSL_DIU_CH7301
477 #define CONFIG_SYS_I2C_DVI_BUS_NUM 0
478 #define CONFIG_SYS_I2C_QIXIS_ADDR 0x66
479 #define CONFIG_SYS_I2C_DVI_ADDR 0x75
480 #endif
481
482 /*
483 * eTSEC
484 */
485 #define CONFIG_TSEC_ENET
486
487 #ifdef CONFIG_TSEC_ENET
488 #define CONFIG_MII
489 #define CONFIG_MII_DEFAULT_TSEC 3
490 #define CONFIG_TSEC1 1
491 #define CONFIG_TSEC1_NAME "eTSEC1"
492 #define CONFIG_TSEC2 1
493 #define CONFIG_TSEC2_NAME "eTSEC2"
494 #define CONFIG_TSEC3 1
495 #define CONFIG_TSEC3_NAME "eTSEC3"
496
497 #define TSEC1_PHY_ADDR 1
498 #define TSEC2_PHY_ADDR 2
499 #define TSEC3_PHY_ADDR 3
500
501 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
502 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
503 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
504
505 #define TSEC1_PHYIDX 0
506 #define TSEC2_PHYIDX 0
507 #define TSEC3_PHYIDX 0
508
509 #define CONFIG_ETHPRIME "eTSEC1"
510
511 #define CONFIG_PHY_GIGE
512 #define CONFIG_PHYLIB
513 #define CONFIG_PHY_REALTEK
514
515 #define CONFIG_HAS_ETH0
516 #define CONFIG_HAS_ETH1
517 #define CONFIG_HAS_ETH2
518
519 #define CONFIG_FSL_SGMII_RISER 1
520 #define SGMII_RISER_PHY_OFFSET 0x1b
521
522 #ifdef CONFIG_FSL_SGMII_RISER
523 #define CONFIG_SYS_TBIPA_VALUE 8
524 #endif
525
526 #endif
527
528 /* PCIe */
529 #define CONFIG_PCI /* Enable PCI/PCIE */
530 #define CONFIG_PCIE1 /* PCIE controler 1 */
531 #define CONFIG_PCIE2 /* PCIE controler 2 */
532 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
533 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
534
535 #define CONFIG_SYS_PCI_64BIT
536
537 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
538 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
539 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
540 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
541
542 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
543 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
544 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
545
546 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
547 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
548 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
549
550 #ifdef CONFIG_PCI
551 #define CONFIG_PCI_PNP
552 #define CONFIG_PCI_SCAN_SHOW
553 #define CONFIG_CMD_PCI
554 #endif
555
556 #define CONFIG_CMD_PING
557 #define CONFIG_CMD_DHCP
558 #define CONFIG_CMD_MII
559
560 #define CONFIG_CMDLINE_TAG
561 #define CONFIG_CMDLINE_EDITING
562
563 #define CONFIG_ARMV7_NONSEC
564 #define CONFIG_ARMV7_VIRT
565 #define CONFIG_PEN_ADDR_BIG_ENDIAN
566 #define CONFIG_LS102XA_NS_ACCESS
567 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
568 #define CONFIG_TIMER_CLK_FREQ 12500000
569
570 #define CONFIG_HWCONFIG
571 #define HWCONFIG_BUFFER_SIZE 256
572
573 #define CONFIG_FSL_DEVICE_DISABLE
574
575 #define CONFIG_BOOTDELAY 3
576
577 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
578
579 #ifdef CONFIG_LPUART
580 #define CONFIG_EXTRA_ENV_SETTINGS \
581 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
582 "fdt_high=0xcfffffff\0" \
583 "initrd_high=0xcfffffff\0" \
584 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
585 #else
586 #define CONFIG_EXTRA_ENV_SETTINGS \
587 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
588 "fdt_high=0xcfffffff\0" \
589 "initrd_high=0xcfffffff\0" \
590 "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
591 #endif
592
593 /*
594 * Miscellaneous configurable options
595 */
596 #define CONFIG_SYS_LONGHELP /* undef to save memory */
597 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
598 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
599 #define CONFIG_AUTO_COMPLETE
600 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
601 #define CONFIG_SYS_PBSIZE \
602 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
603 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
604 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
605
606 #define CONFIG_CMD_GREPENV
607 #define CONFIG_CMD_MEMINFO
608 #define CONFIG_CMD_MEMTEST
609 #define CONFIG_SYS_MEMTEST_START 0x80000000
610 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
611
612 #define CONFIG_SYS_LOAD_ADDR 0x82000000
613
614 #define CONFIG_LS102XA_STREAM_ID
615
616 /*
617 * Stack sizes
618 * The stack sizes are set up in start.S using the settings below
619 */
620 #define CONFIG_STACKSIZE (30 * 1024)
621
622 #define CONFIG_SYS_INIT_SP_OFFSET \
623 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
624 #define CONFIG_SYS_INIT_SP_ADDR \
625 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
626
627 #ifdef CONFIG_SPL_BUILD
628 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
629 #else
630 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
631 #endif
632
633 /*
634 * Environment
635 */
636 #define CONFIG_ENV_OVERWRITE
637
638 #if defined(CONFIG_SD_BOOT)
639 #define CONFIG_ENV_OFFSET 0x100000
640 #define CONFIG_ENV_IS_IN_MMC
641 #define CONFIG_SYS_MMC_ENV_DEV 0
642 #define CONFIG_ENV_SIZE 0x2000
643 #elif defined(CONFIG_QSPI_BOOT)
644 #define CONFIG_ENV_IS_IN_SPI_FLASH
645 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */
646 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
647 #define CONFIG_ENV_SECT_SIZE 0x10000
648 #elif defined(CONFIG_NAND_BOOT)
649 #define CONFIG_ENV_IS_IN_NAND
650 #define CONFIG_ENV_SIZE 0x2000
651 #define CONFIG_ENV_OFFSET (10 * CONFIG_SYS_NAND_BLOCK_SIZE)
652 #else
653 #define CONFIG_ENV_IS_IN_FLASH
654 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
655 #define CONFIG_ENV_SIZE 0x2000
656 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
657 #endif
658
659 #define CONFIG_OF_LIBFDT
660 #define CONFIG_OF_BOARD_SETUP
661 #define CONFIG_CMD_BOOTZ
662
663 #define CONFIG_MISC_INIT_R
664
665 /* Hash command with SHA acceleration supported in hardware */
666 #define CONFIG_CMD_HASH
667 #define CONFIG_SHA_HW_ACCEL
668
669 #ifdef CONFIG_SECURE_BOOT
670 #define CONFIG_CMD_BLOB
671 #include <asm/fsl_secure_boot.h>
672 #endif
673
674 #endif