include/configs/ls1021aqds.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #include <config_cmd_default.h>
  11
  12 #define CONFIG_LS102XA
  13
  14 #define CONFIG_SYS_GENERIC_BOARD
  15
  16 #define CONFIG_DISPLAY_CPUINFO
  17 #define CONFIG_DISPLAY_BOARDINFO
  18
  19 #define CONFIG_SKIP_LOWLEVEL_INIT
  20 #define CONFIG_BOARD_EARLY_INIT_F
  21
  22 /*
  23  * Size of malloc() pool
  24  */
  25 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  26
  27 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  28 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  29
  30 /*
  31  * Generic Timer Definitions
  32  */
  33 #define GENERIC_TIMER_CLK               12500000
  34
  35 #ifndef __ASSEMBLY__
  36 unsigned long get_board_sys_clk(void);
  37 unsigned long get_board_ddr_clk(void);
  38 #endif
  39
  40 #define CONFIG_SYS_CLK_FREQ             get_board_sys_clk()
  41 #define CONFIG_DDR_CLK_FREQ             get_board_ddr_clk()
  42
  43 #ifdef CONFIG_RAMBOOT_PBL
  44 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021aqds/ls102xa_pbi.cfg
  45 #endif
  46
  47 #ifdef CONFIG_SD_BOOT
  48 #define CONFIG_SYS_FSL_PBL_RCW  board/freescale/ls1021aqds/ls102xa_rcw_sd.cfg
  49 #define CONFIG_SPL_FRAMEWORK
  50 #define CONFIG_SPL_LDSCRIPT     "arch/$(ARCH)/cpu/u-boot-spl.lds"
  51 #define CONFIG_SPL_LIBCOMMON_SUPPORT
  52 #define CONFIG_SPL_LIBGENERIC_SUPPORT
  53 #define CONFIG_SPL_ENV_SUPPORT
  54 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
  55 #define CONFIG_SPL_I2C_SUPPORT
  56 #define CONFIG_SPL_WATCHDOG_SUPPORT
  57 #define CONFIG_SPL_SERIAL_SUPPORT
  58 #define CONFIG_SPL_DRIVERS_MISC_SUPPORT
  59 #define CONFIG_SPL_MMC_SUPPORT
  60 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR         0xe8
  61 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS              0x400
  62
  63 #define CONFIG_SPL_TEXT_BASE            0x10000000
  64 #define CONFIG_SPL_MAX_SIZE             0x1a000
  65 #define CONFIG_SPL_STACK                0x1001d000
  66 #define CONFIG_SPL_PAD_TO               0x1c000
  67 #define CONFIG_SYS_TEXT_BASE            0x82000000
  68
  69 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
  70 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
  71 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
  72 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
  73 #define CONFIG_SYS_MONITOR_LEN          0x80000
  74 #endif
  75
  76 #ifndef CONFIG_SYS_TEXT_BASE
  77 #define CONFIG_SYS_TEXT_BASE            0x67f80000
  78 #endif
  79
  80 #define CONFIG_NR_DRAM_BANKS            1
  81
  82 #define CONFIG_DDR_SPD
  83 #define SPD_EEPROM_ADDRESS              0x51
  84 #define CONFIG_SYS_SPD_BUS_NUM          0
  85
  86 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  87 #ifndef CONFIG_SYS_FSL_DDR4
  88 #define CONFIG_SYS_FSL_DDR3             /* Use DDR3 memory */
  89 #define CONFIG_SYS_DDR_RAW_TIMING
  90 #endif
  91 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  92 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
  93
  94 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  95 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  96
  97 #define CONFIG_DDR_ECC
  98 #ifdef CONFIG_DDR_ECC
  99 #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
 100 #define CONFIG_MEM_INIT_VALUE           0xdeadbeef
 101 #endif
 102
 103 #define CONFIG_SYS_HAS_SERDES
 104
 105 #define CONFIG_FSL_CAAM                 /* Enable CAAM */
 106
 107 #if !defined(CONFIG_SDCARD) && !defined(CONFIG_NAND) && !defined(CONFIG_SPI)
 108 #define CONFIG_U_QE
 109 #endif
 110
 111 /*
 112  * IFC Definitions
 113  */
 114 #define CONFIG_FSL_IFC
 115 #define CONFIG_SYS_FLASH_BASE           0x60000000
 116 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 117
 118 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 119 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 120                                 CSPR_PORT_SIZE_16 | \
 121                                 CSPR_MSEL_NOR | \
 122                                 CSPR_V)
 123 #define CONFIG_SYS_NOR1_CSPR_EXT        (0x0)
 124 #define CONFIG_SYS_NOR1_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
 125                                 + 0x8000000) | \
 126                                 CSPR_PORT_SIZE_16 | \
 127                                 CSPR_MSEL_NOR | \
 128                                 CSPR_V)
 129 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 130
 131 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 132                                         CSOR_NOR_TRHZ_80)
 133 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 134                                         FTIM0_NOR_TEADC(0x5) | \
 135                                         FTIM0_NOR_TEAHC(0x5))
 136 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 137                                         FTIM1_NOR_TRAD_NOR(0x1a) | \
 138                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 139 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 140                                         FTIM2_NOR_TCH(0x4) | \
 141                                         FTIM2_NOR_TWPH(0xe) | \
 142                                         FTIM2_NOR_TWP(0x1c))
 143 #define CONFIG_SYS_NOR_FTIM3            0
 144
 145 #define CONFIG_FLASH_CFI_DRIVER
 146 #define CONFIG_SYS_FLASH_CFI
 147 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 148 #define CONFIG_SYS_FLASH_QUIET_TEST
 149 #define CONFIG_FLASH_SHOW_PROGRESS      45
 150 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 151 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 152
 153 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* number of banks */
 154 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 155 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 156 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 157
 158 #define CONFIG_SYS_FLASH_EMPTY_INFO
 159 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS, \
 160                                         CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000}
 161
 162 /*
 163  * NAND Flash Definitions
 164  */
 165 #define CONFIG_NAND_FSL_IFC
 166
 167 #define CONFIG_SYS_NAND_BASE            0x7e800000
 168 #define CONFIG_SYS_NAND_BASE_PHYS       CONFIG_SYS_NAND_BASE
 169
 170 #define CONFIG_SYS_NAND_CSPR_EXT        (0x0)
 171
 172 #define CONFIG_SYS_NAND_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
 173                                 | CSPR_PORT_SIZE_8      \
 174                                 | CSPR_MSEL_NAND        \
 175                                 | CSPR_V)
 176 #define CONFIG_SYS_NAND_AMASK   IFC_AMASK(64*1024)
 177 #define CONFIG_SYS_NAND_CSOR    (CSOR_NAND_ECC_ENC_EN   /* ECC on encode */ \
 178                                 | CSOR_NAND_ECC_DEC_EN  /* ECC on decode */ \
 179                                 | CSOR_NAND_ECC_MODE_4  /* 4-bit ECC */ \
 180                                 | CSOR_NAND_RAL_3       /* RAL = 3 Bytes */ \
 181                                 | CSOR_NAND_PGS_2K      /* Page Size = 2K */ \
 182                                 | CSOR_NAND_SPRZ_64     /* Spare size = 64 */ \
 183                                 | CSOR_NAND_PB(64))     /* 64 Pages Per Block */
 184
 185 #define CONFIG_SYS_NAND_ONFI_DETECTION
 186
 187 #define CONFIG_SYS_NAND_FTIM0           (FTIM0_NAND_TCCST(0x7) | \
 188                                         FTIM0_NAND_TWP(0x18)   | \
 189                                         FTIM0_NAND_TWCHT(0x7) | \
 190                                         FTIM0_NAND_TWH(0xa))
 191 #define CONFIG_SYS_NAND_FTIM1           (FTIM1_NAND_TADLE(0x32) | \
 192                                         FTIM1_NAND_TWBE(0x39)  | \
 193                                         FTIM1_NAND_TRR(0xe)   | \
 194                                         FTIM1_NAND_TRP(0x18))
 195 #define CONFIG_SYS_NAND_FTIM2           (FTIM2_NAND_TRAD(0xf) | \
 196                                         FTIM2_NAND_TREH(0xa) | \
 197                                         FTIM2_NAND_TWHRE(0x1e))
 198 #define CONFIG_SYS_NAND_FTIM3           0x0
 199
 200 #define CONFIG_SYS_NAND_BASE_LIST       { CONFIG_SYS_NAND_BASE }
 201 #define CONFIG_SYS_MAX_NAND_DEVICE      1
 202 #define CONFIG_MTD_NAND_VERIFY_WRITE
 203 #define CONFIG_CMD_NAND
 204
 205 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 206
 207 /*
 208  * QIXIS Definitions
 209  */
 210 #define CONFIG_FSL_QIXIS
 211
 212 #ifdef CONFIG_FSL_QIXIS
 213 #define QIXIS_BASE                      0x7fb00000
 214 #define QIXIS_BASE_PHYS                 QIXIS_BASE
 215 #define CONFIG_SYS_I2C_FPGA_ADDR        0x66
 216 #define QIXIS_LBMAP_SWITCH              6
 217 #define QIXIS_LBMAP_MASK                0x0f
 218 #define QIXIS_LBMAP_SHIFT               0
 219 #define QIXIS_LBMAP_DFLTBANK            0x00
 220 #define QIXIS_LBMAP_ALTBANK             0x04
 221 #define QIXIS_RST_CTL_RESET             0x44
 222 #define QIXIS_RCFG_CTL_RECONFIG_IDLE    0x20
 223 #define QIXIS_RCFG_CTL_RECONFIG_START   0x21
 224 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE   0x08
 225
 226 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 227 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(QIXIS_BASE_PHYS) | \
 228                                         CSPR_PORT_SIZE_8 | \
 229                                         CSPR_MSEL_GPCM | \
 230                                         CSPR_V)
 231 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 232 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 233                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 234                                         CSOR_NOR_TRHZ_80)
 235
 236 /*
 237  * QIXIS Timing parameters for IFC GPCM
 238  */
 239 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xe) | \
 240                                         FTIM0_GPCM_TEADC(0xe) | \
 241                                         FTIM0_GPCM_TEAHC(0xe))
 242 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xe) | \
 243                                         FTIM1_GPCM_TRAD(0x1f))
 244 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xe) | \
 245                                         FTIM2_GPCM_TCH(0xe) | \
 246                                         FTIM2_GPCM_TWP(0xf0))
 247 #define CONFIG_SYS_FPGA_FTIM3           0x0
 248 #endif
 249
 250 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 251 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 252 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 253 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 254 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 255 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 256 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 257 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 258 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_NOR1_CSPR_EXT
 259 #define CONFIG_SYS_CSPR1                CONFIG_SYS_NOR1_CSPR
 260 #define CONFIG_SYS_AMASK1               CONFIG_SYS_NOR_AMASK
 261 #define CONFIG_SYS_CSOR1                CONFIG_SYS_NOR_CSOR
 262 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_NOR_FTIM0
 263 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_NOR_FTIM1
 264 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_NOR_FTIM2
 265 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_NOR_FTIM3
 266 #define CONFIG_SYS_CSPR2_EXT            CONFIG_SYS_NAND_CSPR_EXT
 267 #define CONFIG_SYS_CSPR2                CONFIG_SYS_NAND_CSPR
 268 #define CONFIG_SYS_AMASK2               CONFIG_SYS_NAND_AMASK
 269 #define CONFIG_SYS_CSOR2                CONFIG_SYS_NAND_CSOR
 270 #define CONFIG_SYS_CS2_FTIM0            CONFIG_SYS_NAND_FTIM0
 271 #define CONFIG_SYS_CS2_FTIM1            CONFIG_SYS_NAND_FTIM1
 272 #define CONFIG_SYS_CS2_FTIM2            CONFIG_SYS_NAND_FTIM2
 273 #define CONFIG_SYS_CS2_FTIM3            CONFIG_SYS_NAND_FTIM3
 274 #define CONFIG_SYS_CSPR3_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 275 #define CONFIG_SYS_CSPR3                CONFIG_SYS_FPGA_CSPR
 276 #define CONFIG_SYS_AMASK3               CONFIG_SYS_FPGA_AMASK
 277 #define CONFIG_SYS_CSOR3                CONFIG_SYS_FPGA_CSOR
 278 #define CONFIG_SYS_CS3_FTIM0            CONFIG_SYS_FPGA_FTIM0
 279 #define CONFIG_SYS_CS3_FTIM1            CONFIG_SYS_FPGA_FTIM1
 280 #define CONFIG_SYS_CS3_FTIM2            CONFIG_SYS_FPGA_FTIM2
 281 #define CONFIG_SYS_CS3_FTIM3            CONFIG_SYS_FPGA_FTIM3
 282
 283 /*
 284  * Serial Port
 285  */
 286 #define CONFIG_CONS_INDEX               1
 287 #define CONFIG_SYS_NS16550
 288 #define CONFIG_SYS_NS16550_SERIAL
 289 #define CONFIG_SYS_NS16550_REG_SIZE     1
 290 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 291
 292 #define CONFIG_BAUDRATE                 115200
 293
 294 /*
 295  * I2C
 296  */
 297 #define CONFIG_CMD_I2C
 298 #define CONFIG_SYS_I2C
 299 #define CONFIG_SYS_I2C_MXC
 300
 301 /*
 302  * I2C bus multiplexer
 303  */
 304 #define I2C_MUX_PCA_ADDR_PRI            0x77
 305 #define I2C_MUX_CH_DEFAULT              0x8
 306
 307 /*
 308  * MMC
 309  */
 310 #define CONFIG_MMC
 311 #define CONFIG_CMD_MMC
 312 #define CONFIG_FSL_ESDHC
 313 #define CONFIG_GENERIC_MMC
 314
 315 #define CONFIG_CMD_FAT
 316 #define CONFIG_DOS_PARTITION
 317
 318 /*
 319  * USB
 320  */
 321 #define CONFIG_HAS_FSL_DR_USB
 322
 323 #ifdef CONFIG_HAS_FSL_DR_USB
 324 #define CONFIG_USB_EHCI
 325
 326 #ifdef CONFIG_USB_EHCI
 327 #define CONFIG_CMD_USB
 328 #define CONFIG_USB_STORAGE
 329 #define CONFIG_USB_EHCI_FSL
 330 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 331 #define CONFIG_CMD_EXT2
 332 #endif
 333 #endif
 334
 335 /*
 336  * eTSEC
 337  */
 338 #define CONFIG_TSEC_ENET
 339
 340 #ifdef CONFIG_TSEC_ENET
 341 #define CONFIG_MII
 342 #define CONFIG_MII_DEFAULT_TSEC         3
 343 #define CONFIG_TSEC1                    1
 344 #define CONFIG_TSEC1_NAME               "eTSEC1"
 345 #define CONFIG_TSEC2                    1
 346 #define CONFIG_TSEC2_NAME               "eTSEC2"
 347 #define CONFIG_TSEC3                    1
 348 #define CONFIG_TSEC3_NAME               "eTSEC3"
 349
 350 #define TSEC1_PHY_ADDR                  1
 351 #define TSEC2_PHY_ADDR                  2
 352 #define TSEC3_PHY_ADDR                  3
 353
 354 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 355 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 356 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 357
 358 #define TSEC1_PHYIDX                    0
 359 #define TSEC2_PHYIDX                    0
 360 #define TSEC3_PHYIDX                    0
 361
 362 #define CONFIG_ETHPRIME                 "eTSEC1"
 363
 364 #define CONFIG_PHY_GIGE
 365 #define CONFIG_PHYLIB
 366 #define CONFIG_PHY_REALTEK
 367
 368 #define CONFIG_HAS_ETH0
 369 #define CONFIG_HAS_ETH1
 370 #define CONFIG_HAS_ETH2
 371
 372 #define CONFIG_FSL_SGMII_RISER          1
 373 #define SGMII_RISER_PHY_OFFSET          0x1b
 374
 375 #ifdef CONFIG_FSL_SGMII_RISER
 376 #define CONFIG_SYS_TBIPA_VALUE          8
 377 #endif
 378
 379 #endif
 380
 381 /* PCIe */
 382 #define CONFIG_PCI              /* Enable PCI/PCIE */
 383 #define CONFIG_PCIE1            /* PCIE controler 1 */
 384 #define CONFIG_PCIE2            /* PCIE controler 2 */
 385 #define CONFIG_PCIE_LAYERSCAPE  /* Use common FSL Layerscape PCIe code */
 386 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
 387
 388 #define CONFIG_CMD_PING
 389 #define CONFIG_CMD_DHCP
 390 #define CONFIG_CMD_MII
 391 #define CONFIG_CMD_NET
 392
 393 #define CONFIG_CMDLINE_TAG
 394 #define CONFIG_CMDLINE_EDITING
 395
 396 #define CONFIG_CMD_IMLS
 397
 398 #define CONFIG_HWCONFIG
 399 #define HWCONFIG_BUFFER_SIZE            128
 400
 401 #define CONFIG_BOOTDELAY                3
 402
 403 #define CONFIG_SYS_QE_FW_ADDR     0x67f40000
 404
 405 #define CONFIG_EXTRA_ENV_SETTINGS       \
 406         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 407         "fdt_high=0xcfffffff\0"         \
 408         "initrd_high=0xcfffffff\0"      \
 409         "hwconfig=fsl_ddr:ctlr_intlv=null,bank_intlv=null\0"
 410
 411 /*
 412  * Miscellaneous configurable options
 413  */
 414 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 415 #define CONFIG_SYS_HUSH_PARSER          /* use "hush" command parser */
 416 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 417 #define CONFIG_AUTO_COMPLETE
 418 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size */
 419 #define CONFIG_SYS_PBSIZE               \
 420                 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 421 #define CONFIG_SYS_MAXARGS              16      /* max number of command args */
 422 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 423
 424 #define CONFIG_CMD_ENV_EXISTS
 425 #define CONFIG_CMD_GREPENV
 426 #define CONFIG_CMD_MEMINFO
 427 #define CONFIG_CMD_MEMTEST
 428 #define CONFIG_SYS_MEMTEST_START        0x80000000
 429 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 430
 431 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 432
 433 /*
 434  * Stack sizes
 435  * The stack sizes are set up in start.S using the settings below
 436  */
 437 #define CONFIG_STACKSIZE                (30 * 1024)
 438
 439 #define CONFIG_SYS_INIT_SP_OFFSET \
 440         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 441 #define CONFIG_SYS_INIT_SP_ADDR \
 442         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 443
 444 #ifdef CONFIG_SPL_BUILD
 445 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 446 #else
 447 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 448 #endif
 449
 450 /*
 451  * Environment
 452  */
 453 #define CONFIG_ENV_OVERWRITE
 454
 455 #if defined(CONFIG_SD_BOOT)
 456 #define CONFIG_ENV_OFFSET               0x100000
 457 #define CONFIG_ENV_IS_IN_MMC
 458 #define CONFIG_SYS_MMC_ENV_DEV          0
 459 #define CONFIG_ENV_SIZE                 0x2000
 460 #else
 461 #define CONFIG_ENV_IS_IN_FLASH
 462 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
 463 #define CONFIG_ENV_SIZE                 0x2000
 464 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 465 #endif
 466
 467 #define CONFIG_OF_LIBFDT
 468 #define CONFIG_OF_BOARD_SETUP
 469 #define CONFIG_CMD_BOOTZ
 470
 471 #define CONFIG_MISC_INIT_R
 472
 473 /* Hash command with SHA acceleration supported in hardware */
 474 #define CONFIG_CMD_HASH
 475 #define CONFIG_SHA_HW_ACCEL
 476
 477 #ifdef CONFIG_SECURE_BOOT
 478 #define CONFIG_CMD_BLOB
 479 #endif
 480
 481 #endif