include/configs/ls1021atwr.h

   1 /*
   2  * Copyright 2014 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __CONFIG_H
   8 #define __CONFIG_H
   9
  10 #define CONFIG_ARMV7_PSCI_1_0
  11
  12 #define CONFIG_ARMV7_SECURE_BASE        OCRAM_BASE_S_ADDR
  13
  14 #define CONFIG_SYS_FSL_CLK
  15
  16 #define CONFIG_SKIP_LOWLEVEL_INIT
  17 #define CONFIG_DEEP_SLEEP
  18
  19 /*
  20  * Size of malloc() pool
  21  */
  22 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
  23
  24 #define CONFIG_SYS_INIT_RAM_ADDR        OCRAM_BASE_ADDR
  25 #define CONFIG_SYS_INIT_RAM_SIZE        OCRAM_SIZE
  26
  27 /*
  28  * USB
  29  */
  30
  31 /*
  32  * EHCI Support - disbaled by default as
  33  * there is no signal coming out of soc on
  34  * this board for this controller. However,
  35  * the silicon still has this controller,
  36  * and anyone can use this controller by
  37  * taking signals out on their board.
  38  */
  39
  40 /*#define CONFIG_HAS_FSL_DR_USB*/
  41
  42 #ifdef CONFIG_HAS_FSL_DR_USB
  43 #define CONFIG_USB_EHCI_FSL
  44 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
  45 #endif
  46
  47 #define CONFIG_SYS_CLK_FREQ             100000000
  48 #define CONFIG_DDR_CLK_FREQ             100000000
  49
  50 #define DDR_SDRAM_CFG                   0x470c0008
  51 #define DDR_CS0_BNDS                    0x008000bf
  52 #define DDR_CS0_CONFIG                  0x80014302
  53 #define DDR_TIMING_CFG_0                0x50550004
  54 #define DDR_TIMING_CFG_1                0xbcb38c56
  55 #define DDR_TIMING_CFG_2                0x0040d120
  56 #define DDR_TIMING_CFG_3                0x010e1000
  57 #define DDR_TIMING_CFG_4                0x00000001
  58 #define DDR_TIMING_CFG_5                0x03401400
  59 #define DDR_SDRAM_CFG_2                 0x00401010
  60 #define DDR_SDRAM_MODE                  0x00061c60
  61 #define DDR_SDRAM_MODE_2                0x00180000
  62 #define DDR_SDRAM_INTERVAL              0x18600618
  63 #define DDR_DDR_WRLVL_CNTL              0x8655f605
  64 #define DDR_DDR_WRLVL_CNTL_2            0x05060607
  65 #define DDR_DDR_WRLVL_CNTL_3            0x05050505
  66 #define DDR_DDR_CDR1                    0x80040000
  67 #define DDR_DDR_CDR2                    0x00000001
  68 #define DDR_SDRAM_CLK_CNTL              0x02000000
  69 #define DDR_DDR_ZQ_CNTL                 0x89080600
  70 #define DDR_CS0_CONFIG_2                0
  71 #define DDR_SDRAM_CFG_MEM_EN            0x80000000
  72 #define SDRAM_CFG2_D_INIT               0x00000010
  73 #define DDR_CDR2_VREF_TRAIN_EN          0x00000080
  74 #define SDRAM_CFG2_FRC_SR               0x80000000
  75 #define SDRAM_CFG_BI                    0x00000001
  76
  77 #ifdef CONFIG_RAMBOOT_PBL
  78 #define CONFIG_SYS_FSL_PBL_PBI  board/freescale/ls1021atwr/ls102xa_pbi.cfg
  79 #endif
  80
  81 #ifdef CONFIG_SD_BOOT
  82 #ifdef CONFIG_SD_BOOT_QSPI
  83 #define CONFIG_SYS_FSL_PBL_RCW  \
  84         board/freescale/ls1021atwr/ls102xa_rcw_sd_qspi.cfg
  85 #else
  86 #define CONFIG_SYS_FSL_PBL_RCW  \
  87         board/freescale/ls1021atwr/ls102xa_rcw_sd_ifc.cfg
  88 #endif
  89 #define CONFIG_SPL_FRAMEWORK
  90
  91 #ifdef CONFIG_SECURE_BOOT
  92 /*
  93  * HDR would be appended at end of image and copied to DDR along
  94  * with U-Boot image.
  95  */
  96 #define CONFIG_U_BOOT_HDR_SIZE                          (16 << 10)
  97 #endif /* ifdef CONFIG_SECURE_BOOT */
  98
  99 #define CONFIG_SPL_TEXT_BASE            0x10000000
 100 #define CONFIG_SPL_MAX_SIZE             0x1a000
 101 #define CONFIG_SPL_STACK                0x1001d000
 102 #define CONFIG_SPL_PAD_TO               0x1c000
 103 #define CONFIG_SYS_TEXT_BASE            0x82000000
 104
 105 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SYS_TEXT_BASE + \
 106                 CONFIG_SYS_MONITOR_LEN)
 107 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x100000
 108 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 109 #define CONFIG_SPL_BSS_MAX_SIZE         0x80000
 110
 111 #ifdef CONFIG_U_BOOT_HDR_SIZE
 112 /*
 113  * HDR would be appended at end of image and copied to DDR along
 114  * with U-Boot image. Here u-boot max. size is 512K. So if binary
 115  * size increases then increase this size in case of secure boot as
 116  * it uses raw u-boot image instead of fit image.
 117  */
 118 #define CONFIG_SYS_MONITOR_LEN          (0x100000 + CONFIG_U_BOOT_HDR_SIZE)
 119 #else
 120 #define CONFIG_SYS_MONITOR_LEN          0x100000
 121 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
 122 #endif
 123
 124 #ifdef CONFIG_QSPI_BOOT
 125 #define CONFIG_SYS_TEXT_BASE            0x40100000
 126 #endif
 127
 128 #ifndef CONFIG_SYS_TEXT_BASE
 129 #define CONFIG_SYS_TEXT_BASE            0x60100000
 130 #endif
 131
 132 #define CONFIG_NR_DRAM_BANKS            1
 133 #define PHYS_SDRAM                      0x80000000
 134 #define PHYS_SDRAM_SIZE                 (1u * 1024 * 1024 * 1024)
 135
 136 #define CONFIG_SYS_DDR_SDRAM_BASE      0x80000000UL
 137 #define CONFIG_SYS_SDRAM_BASE          CONFIG_SYS_DDR_SDRAM_BASE
 138
 139 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
 140         !defined(CONFIG_QSPI_BOOT)
 141 #define CONFIG_U_QE
 142 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
 143 #endif
 144
 145 /*
 146  * IFC Definitions
 147  */
 148 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
 149 #define CONFIG_FSL_IFC
 150 #define CONFIG_SYS_FLASH_BASE           0x60000000
 151 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 152
 153 #define CONFIG_SYS_NOR0_CSPR_EXT        (0x0)
 154 #define CONFIG_SYS_NOR0_CSPR    (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
 155                                 CSPR_PORT_SIZE_16 | \
 156                                 CSPR_MSEL_NOR | \
 157                                 CSPR_V)
 158 #define CONFIG_SYS_NOR_AMASK            IFC_AMASK(128 * 1024 * 1024)
 159
 160 /* NOR Flash Timing Params */
 161 #define CONFIG_SYS_NOR_CSOR             (CSOR_NOR_ADM_SHIFT(4) | \
 162                                         CSOR_NOR_TRHZ_80)
 163 #define CONFIG_SYS_NOR_FTIM0            (FTIM0_NOR_TACSE(0x4) | \
 164                                         FTIM0_NOR_TEADC(0x5) | \
 165                                         FTIM0_NOR_TAVDS(0x0) | \
 166                                         FTIM0_NOR_TEAHC(0x5))
 167 #define CONFIG_SYS_NOR_FTIM1            (FTIM1_NOR_TACO(0x35) | \
 168                                         FTIM1_NOR_TRAD_NOR(0x1A) | \
 169                                         FTIM1_NOR_TSEQRAD_NOR(0x13))
 170 #define CONFIG_SYS_NOR_FTIM2            (FTIM2_NOR_TCS(0x4) | \
 171                                         FTIM2_NOR_TCH(0x4) | \
 172                                         FTIM2_NOR_TWP(0x1c) | \
 173                                         FTIM2_NOR_TWPH(0x0e))
 174 #define CONFIG_SYS_NOR_FTIM3            0
 175
 176 #define CONFIG_FLASH_CFI_DRIVER
 177 #define CONFIG_SYS_FLASH_CFI
 178 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 179 #define CONFIG_SYS_FLASH_QUIET_TEST
 180 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 181
 182 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 183 #define CONFIG_SYS_MAX_FLASH_SECT       1024    /* sectors per device */
 184 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 185 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 186
 187 #define CONFIG_SYS_FLASH_EMPTY_INFO
 188 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE_PHYS }
 189
 190 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
 191 #define CONFIG_SYS_WRITE_SWAPPED_DATA
 192 #endif
 193
 194 /* CPLD */
 195
 196 #define CONFIG_SYS_CPLD_BASE    0x7fb00000
 197 #define CPLD_BASE_PHYS          CONFIG_SYS_CPLD_BASE
 198
 199 #define CONFIG_SYS_FPGA_CSPR_EXT        (0x0)
 200 #define CONFIG_SYS_FPGA_CSPR            (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
 201                                         CSPR_PORT_SIZE_8 | \
 202                                         CSPR_MSEL_GPCM | \
 203                                         CSPR_V)
 204 #define CONFIG_SYS_FPGA_AMASK           IFC_AMASK(64 * 1024)
 205 #define CONFIG_SYS_FPGA_CSOR            (CSOR_NOR_ADM_SHIFT(4) | \
 206                                         CSOR_NOR_NOR_MODE_AVD_NOR | \
 207                                         CSOR_NOR_TRHZ_80)
 208
 209 /* CPLD Timing parameters for IFC GPCM */
 210 #define CONFIG_SYS_FPGA_FTIM0           (FTIM0_GPCM_TACSE(0xf) | \
 211                                         FTIM0_GPCM_TEADC(0xf) | \
 212                                         FTIM0_GPCM_TEAHC(0xf))
 213 #define CONFIG_SYS_FPGA_FTIM1           (FTIM1_GPCM_TACO(0xff) | \
 214                                         FTIM1_GPCM_TRAD(0x3f))
 215 #define CONFIG_SYS_FPGA_FTIM2           (FTIM2_GPCM_TCS(0xf) | \
 216                                         FTIM2_GPCM_TCH(0xf) | \
 217                                         FTIM2_GPCM_TWP(0xff))
 218 #define CONFIG_SYS_FPGA_FTIM3           0x0
 219 #define CONFIG_SYS_CSPR0_EXT            CONFIG_SYS_NOR0_CSPR_EXT
 220 #define CONFIG_SYS_CSPR0                CONFIG_SYS_NOR0_CSPR
 221 #define CONFIG_SYS_AMASK0               CONFIG_SYS_NOR_AMASK
 222 #define CONFIG_SYS_CSOR0                CONFIG_SYS_NOR_CSOR
 223 #define CONFIG_SYS_CS0_FTIM0            CONFIG_SYS_NOR_FTIM0
 224 #define CONFIG_SYS_CS0_FTIM1            CONFIG_SYS_NOR_FTIM1
 225 #define CONFIG_SYS_CS0_FTIM2            CONFIG_SYS_NOR_FTIM2
 226 #define CONFIG_SYS_CS0_FTIM3            CONFIG_SYS_NOR_FTIM3
 227 #define CONFIG_SYS_CSPR1_EXT            CONFIG_SYS_FPGA_CSPR_EXT
 228 #define CONFIG_SYS_CSPR1                CONFIG_SYS_FPGA_CSPR
 229 #define CONFIG_SYS_AMASK1               CONFIG_SYS_FPGA_AMASK
 230 #define CONFIG_SYS_CSOR1                CONFIG_SYS_FPGA_CSOR
 231 #define CONFIG_SYS_CS1_FTIM0            CONFIG_SYS_FPGA_FTIM0
 232 #define CONFIG_SYS_CS1_FTIM1            CONFIG_SYS_FPGA_FTIM1
 233 #define CONFIG_SYS_CS1_FTIM2            CONFIG_SYS_FPGA_FTIM2
 234 #define CONFIG_SYS_CS1_FTIM3            CONFIG_SYS_FPGA_FTIM3
 235
 236 /*
 237  * Serial Port
 238  */
 239 #ifdef CONFIG_LPUART
 240 #define CONFIG_LPUART_32B_REG
 241 #else
 242 #define CONFIG_CONS_INDEX               1
 243 #define CONFIG_SYS_NS16550_SERIAL
 244 #ifndef CONFIG_DM_SERIAL
 245 #define CONFIG_SYS_NS16550_REG_SIZE     1
 246 #endif
 247 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 248 #endif
 249
 250 /*
 251  * I2C
 252  */
 253 #define CONFIG_SYS_I2C
 254 #define CONFIG_SYS_I2C_MXC
 255 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
 256 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
 257 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
 258
 259 /* EEPROM */
 260 #define CONFIG_ID_EEPROM
 261 #define CONFIG_SYS_I2C_EEPROM_NXID
 262 #define CONFIG_SYS_EEPROM_BUS_NUM               1
 263 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x53
 264 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
 265 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       3
 266 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   5
 267
 268 /*
 269  * MMC
 270  */
 271 #define CONFIG_FSL_ESDHC
 272
 273 /* SPI */
 274 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 275 /* QSPI */
 276 #define QSPI0_AMBA_BASE                 0x40000000
 277 #define FSL_QSPI_FLASH_SIZE             (1 << 24)
 278 #define FSL_QSPI_FLASH_NUM              2
 279
 280 /* DSPI */
 281 #endif
 282
 283 /* DM SPI */
 284 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
 285 #define CONFIG_DM_SPI_FLASH
 286 #endif
 287
 288 /*
 289  * Video
 290  */
 291 #ifdef CONFIG_VIDEO_FSL_DCU_FB
 292 #define CONFIG_VIDEO_LOGO
 293 #define CONFIG_VIDEO_BMP_LOGO
 294
 295 #define CONFIG_FSL_DCU_SII9022A
 296 #define CONFIG_SYS_I2C_DVI_BUS_NUM      1
 297 #define CONFIG_SYS_I2C_DVI_ADDR         0x39
 298 #endif
 299
 300 /*
 301  * eTSEC
 302  */
 303 #define CONFIG_TSEC_ENET
 304
 305 #ifdef CONFIG_TSEC_ENET
 306 #define CONFIG_MII
 307 #define CONFIG_MII_DEFAULT_TSEC         1
 308 #define CONFIG_TSEC1                    1
 309 #define CONFIG_TSEC1_NAME               "eTSEC1"
 310 #define CONFIG_TSEC2                    1
 311 #define CONFIG_TSEC2_NAME               "eTSEC2"
 312 #define CONFIG_TSEC3                    1
 313 #define CONFIG_TSEC3_NAME               "eTSEC3"
 314
 315 #define TSEC1_PHY_ADDR                  2
 316 #define TSEC2_PHY_ADDR                  0
 317 #define TSEC3_PHY_ADDR                  1
 318
 319 #define TSEC1_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 320 #define TSEC2_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 321 #define TSEC3_FLAGS                     (TSEC_GIGABIT | TSEC_REDUCED)
 322
 323 #define TSEC1_PHYIDX                    0
 324 #define TSEC2_PHYIDX                    0
 325 #define TSEC3_PHYIDX                    0
 326
 327 #define CONFIG_ETHPRIME                 "eTSEC1"
 328
 329 #define CONFIG_PHY_ATHEROS
 330
 331 #define CONFIG_HAS_ETH0
 332 #define CONFIG_HAS_ETH1
 333 #define CONFIG_HAS_ETH2
 334 #endif
 335
 336 /* PCIe */
 337 #define CONFIG_PCIE1            /* PCIE controller 1 */
 338 #define CONFIG_PCIE2            /* PCIE controller 2 */
 339
 340 #ifdef CONFIG_PCI
 341 #define CONFIG_PCI_SCAN_SHOW
 342 #endif
 343
 344 #define CONFIG_CMDLINE_TAG
 345
 346 #define CONFIG_PEN_ADDR_BIG_ENDIAN
 347 #define CONFIG_LAYERSCAPE_NS_ACCESS
 348 #define CONFIG_SMP_PEN_ADDR             0x01ee0200
 349 #define COUNTER_FREQUENCY               12500000
 350
 351 #define CONFIG_HWCONFIG
 352 #define HWCONFIG_BUFFER_SIZE            256
 353
 354 #define CONFIG_FSL_DEVICE_DISABLE
 355
 356 #include <config_distro_defaults.h>
 357 #define BOOT_TARGET_DEVICES(func) \
 358         func(MMC, mmc, 0) \
 359         func(USB, usb, 0)
 360 #include <config_distro_bootcmd.h>
 361
 362 #ifdef CONFIG_LPUART
 363 #define CONFIG_EXTRA_ENV_SETTINGS       \
 364         "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
 365         "initrd_high=0xffffffff\0"      \
 366         "fdt_high=0xffffffff\0"         \
 367         "fdt_addr=0x64f00000\0"         \
 368         "kernel_addr=0x65000000\0"      \
 369         "scriptaddr=0x80000000\0"       \
 370         "scripthdraddr=0x80080000\0"    \
 371         "fdtheader_addr_r=0x80100000\0" \
 372         "kernelheader_addr_r=0x80200000\0"      \
 373         "kernel_addr_r=0x81000000\0"    \
 374         "fdt_addr_r=0x90000000\0"       \
 375         "ramdisk_addr_r=0xa0000000\0"   \
 376         "load_addr=0xa0000000\0"        \
 377         "kernel_size=0x2800000\0"       \
 378         "kernel_addr_sd=0x8000\0"       \
 379         "kernel_size_sd=0x14000\0"      \
 380         BOOTENV                         \
 381         "boot_scripts=ls1021atwr_boot.scr\0"    \
 382         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 383                 "scan_dev_for_boot_part="       \
 384                         "part list ${devtype} ${devnum} devplist; "     \
 385                         "env exists devplist || setenv devplist 1; "    \
 386                         "for distro_bootpart in ${devplist}; do "       \
 387                         "if fstype ${devtype} "                         \
 388                                 "${devnum}:${distro_bootpart} "         \
 389                                 "bootfstype; then "                     \
 390                                 "run scan_dev_for_boot; "               \
 391                         "fi; "                  \
 392                 "done\0"                        \
 393         "scan_dev_for_boot="                              \
 394                 "echo Scanning ${devtype} "               \
 395                                 "${devnum}:${distro_bootpart}...; "  \
 396                 "for prefix in ${boot_prefixes}; do "     \
 397                         "run scan_dev_for_scripts; "      \
 398                 "done;"                                   \
 399                 "\0"                                      \
 400         "boot_a_script="                                  \
 401                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 402                         "${scriptaddr} ${prefix}${script}; "    \
 403                 "env exists secureboot && load ${devtype} "     \
 404                         "${devnum}:${distro_bootpart} "         \
 405                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 406                         "&& esbc_validate ${scripthdraddr};"    \
 407                 "source ${scriptaddr}\0"          \
 408         "installer=load mmc 0:2 $load_addr "    \
 409                 "/flex_installer_arm32.itb; "           \
 410                 "bootm $load_addr#ls1021atwr\0" \
 411         "qspi_bootcmd=echo Trying load from qspi..;"    \
 412                 "sf probe && sf read $load_addr "       \
 413                 "$kernel_addr $kernel_size && bootm $load_addr#$board\0"        \
 414         "nor_bootcmd=echo Trying load from nor..;"      \
 415                 "cp.b $kernel_addr $load_addr "         \
 416                 "$kernel_size && bootm $load_addr#$board\0"
 417 #else
 418 #define CONFIG_EXTRA_ENV_SETTINGS       \
 419         "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
 420         "initrd_high=0xffffffff\0"      \
 421         "fdt_high=0xffffffff\0"         \
 422         "fdt_addr=0x64f00000\0"         \
 423         "kernel_addr=0x61000000\0"      \
 424         "kernelheader_addr=0x60800000\0"        \
 425         "scriptaddr=0x80000000\0"       \
 426         "scripthdraddr=0x80080000\0"    \
 427         "fdtheader_addr_r=0x80100000\0" \
 428         "kernelheader_addr_r=0x80200000\0"      \
 429         "kernel_addr_r=0x81000000\0"    \
 430         "kernelheader_size=0x40000\0"   \
 431         "fdt_addr_r=0x90000000\0"       \
 432         "ramdisk_addr_r=0xa0000000\0"   \
 433         "load_addr=0xa0000000\0"        \
 434         "kernel_size=0x2800000\0"       \
 435         "kernel_addr_sd=0x8000\0"       \
 436         "kernel_size_sd=0x14000\0"      \
 437         "kernelhdr_addr_sd=0x4000\0"            \
 438         "kernelhdr_size_sd=0x10\0"              \
 439         BOOTENV                         \
 440         "boot_scripts=ls1021atwr_boot.scr\0"    \
 441         "boot_script_hdr=hdr_ls1021atwr_bs.out\0"       \
 442                 "scan_dev_for_boot_part="       \
 443                         "part list ${devtype} ${devnum} devplist; "     \
 444                         "env exists devplist || setenv devplist 1; "    \
 445                         "for distro_bootpart in ${devplist}; do "       \
 446                         "if fstype ${devtype} "                         \
 447                                 "${devnum}:${distro_bootpart} "         \
 448                                 "bootfstype; then "                     \
 449                                 "run scan_dev_for_boot; "               \
 450                         "fi; "                  \
 451                 "done\0"                        \
 452         "scan_dev_for_boot="                              \
 453                 "echo Scanning ${devtype} "               \
 454                                 "${devnum}:${distro_bootpart}...; "  \
 455                 "for prefix in ${boot_prefixes}; do "     \
 456                         "run scan_dev_for_scripts; "      \
 457                 "done;"                                   \
 458                 "\0"                                      \
 459         "boot_a_script="                                  \
 460                 "load ${devtype} ${devnum}:${distro_bootpart} "  \
 461                         "${scriptaddr} ${prefix}${script}; "    \
 462                 "env exists secureboot && load ${devtype} "     \
 463                         "${devnum}:${distro_bootpart} "         \
 464                         "${scripthdraddr} ${prefix}${boot_script_hdr} " \
 465                         "&& esbc_validate ${scripthdraddr};"    \
 466                 "source ${scriptaddr}\0"          \
 467         "qspi_bootcmd=echo Trying load from qspi..;"    \
 468                 "sf probe && sf read $load_addr "       \
 469                 "$kernel_addr $kernel_size; env exists secureboot "     \
 470                 "&& sf read $kernelheader_addr_r $kernelheader_addr "   \
 471                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 472                 "bootm $load_addr#$board\0" \
 473         "nor_bootcmd=echo Trying load from nor..;"      \
 474                 "cp.b $kernel_addr $load_addr "         \
 475                 "$kernel_size; env exists secureboot "  \
 476                 "&& cp.b $kernelheader_addr $kernelheader_addr_r "      \
 477                 "$kernelheader_size && esbc_validate ${kernelheader_addr_r}; " \
 478                 "bootm $load_addr#$board\0"     \
 479         "sd_bootcmd=echo Trying load from SD ..;"       \
 480                 "mmcinfo && mmc read $load_addr "       \
 481                 "$kernel_addr_sd $kernel_size_sd && "   \
 482                 "env exists secureboot && mmc read $kernelheader_addr_r "               \
 483                 "$kernelhdr_addr_sd $kernelhdr_size_sd "                \
 484                 " && esbc_validate ${kernelheader_addr_r};"     \
 485                 "bootm $load_addr#$board\0"
 486 #endif
 487
 488 #undef CONFIG_BOOTCOMMAND
 489 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
 490 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run qspi_bootcmd"       \
 491                            "env exists secureboot && esbc_halt"
 492 #elif defined(CONFIG_SD_BOOT)
 493 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run sd_bootcmd; "       \
 494                            "env exists secureboot && esbc_halt;"
 495 #else
 496 #define CONFIG_BOOTCOMMAND "run distro_bootcmd; run nor_bootcmd;"       \
 497                            "env exists secureboot && esbc_halt;"
 498 #endif
 499
 500 /*
 501  * Miscellaneous configurable options
 502  */
 503 #define CONFIG_SYS_LONGHELP             /* undef to save memory */
 504 #define CONFIG_AUTO_COMPLETE
 505
 506 #define CONFIG_SYS_MEMTEST_START        0x80000000
 507 #define CONFIG_SYS_MEMTEST_END          0x9fffffff
 508
 509 #define CONFIG_SYS_LOAD_ADDR            0x82000000
 510
 511 #define CONFIG_LS102XA_STREAM_ID
 512
 513 #define CONFIG_SYS_INIT_SP_OFFSET \
 514         (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 515 #define CONFIG_SYS_INIT_SP_ADDR \
 516         (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
 517
 518 #ifdef CONFIG_SPL_BUILD
 519 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
 520 #else
 521 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
 522 #endif
 523
 524 #define CONFIG_SYS_QE_FW_ADDR     0x60940000
 525
 526 /*
 527  * Environment
 528  */
 529 #define CONFIG_ENV_OVERWRITE
 530
 531 #if defined(CONFIG_SD_BOOT)
 532 #define CONFIG_ENV_OFFSET               0x300000
 533 #define CONFIG_SYS_MMC_ENV_DEV          0
 534 #define CONFIG_ENV_SIZE                 0x20000
 535 #elif defined(CONFIG_QSPI_BOOT)
 536 #define CONFIG_ENV_SIZE                 0x2000
 537 #define CONFIG_ENV_OFFSET               0x300000
 538 #define CONFIG_ENV_SECT_SIZE            0x10000
 539 #else
 540 #define CONFIG_ENV_ADDR                 (CONFIG_SYS_FLASH_BASE + 0x300000)
 541 #define CONFIG_ENV_SIZE                 0x20000
 542 #define CONFIG_ENV_SECT_SIZE            0x20000 /* 128K (one sector) */
 543 #endif
 544
 545 #define CONFIG_MISC_INIT_R
 546
 547 #include <asm/fsl_secure_boot.h>
 548 #define CONFIG_SYS_BOOTM_LEN    (64 << 20) /* Increase max gunzip size */
 549
 550 #endif