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1 /*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7 #ifndef __CONFIG_H
8 #define __CONFIG_H
9
10 #define CONFIG_LS102XA
11
12 #define CONFIG_ARMV7_PSCI
13
14 #define CONFIG_FSL_CLK
15
16 #define CONFIG_DISPLAY_CPUINFO
17 #define CONFIG_DISPLAY_BOARDINFO
18
19 #define CONFIG_SKIP_LOWLEVEL_INIT
20 #define CONFIG_BOARD_EARLY_INIT_F
21 #define CONFIG_DEEP_SLEEP
22 #ifdef CONFIG_DEEP_SLEEP
23 #define CONFIG_SILENT_CONSOLE
24 #endif
25
26 /*
27 * Size of malloc() pool
28 */
29 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
30
31 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
32 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
33
34 /*
35 * USB
36 */
37
38 /*
39 * EHCI Support - disbaled by default as
40 * there is no signal coming out of soc on
41 * this board for this controller. However,
42 * the silicon still has this controller,
43 * and anyone can use this controller by
44 * taking signals out on their board.
45 */
46
47 /*#define CONFIG_HAS_FSL_DR_USB*/
48
49 #ifdef CONFIG_HAS_FSL_DR_USB
50 #define CONFIG_USB_EHCI
51 #define CONFIG_USB_EHCI_FSL
52 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
53 #endif
54
55 /* XHCI Support - enabled by default */
56 #define CONFIG_HAS_FSL_XHCI_USB
57
58 #ifdef CONFIG_HAS_FSL_XHCI_USB
59 #define CONFIG_USB_XHCI_FSL
60 #define CONFIG_USB_XHCI_DWC3
61 #define CONFIG_USB_XHCI
62 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
63 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
64 #endif
65
66 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
67 #define CONFIG_CMD_USB
68 #define CONFIG_USB_STORAGE
69 #define CONFIG_CMD_EXT2
70 #endif
71
72 /*
73 * Generic Timer Definitions
74 */
75 #define GENERIC_TIMER_CLK 12500000
76
77 #define CONFIG_SYS_CLK_FREQ 100000000
78 #define CONFIG_DDR_CLK_FREQ 100000000
79
80 #define DDR_SDRAM_CFG 0x470c0008
81 #define DDR_CS0_BNDS 0x008000bf
82 #define DDR_CS0_CONFIG 0x80014302
83 #define DDR_TIMING_CFG_0 0x50550004
84 #define DDR_TIMING_CFG_1 0xbcb38c56
85 #define DDR_TIMING_CFG_2 0x0040d120
86 #define DDR_TIMING_CFG_3 0x010e1000
87 #define DDR_TIMING_CFG_4 0x00000001
88 #define DDR_TIMING_CFG_5 0x03401400
89 #define DDR_SDRAM_CFG_2 0x00401010
90 #define DDR_SDRAM_MODE 0x00061c60
91 #define DDR_SDRAM_MODE_2 0x00180000
92 #define DDR_SDRAM_INTERVAL 0x18600618
93 #define DDR_DDR_WRLVL_CNTL 0x8655f605
94 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
95 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
96 #define DDR_DDR_CDR1 0x80040000
97 #define DDR_DDR_CDR2 0x00000001
98 #define DDR_SDRAM_CLK_CNTL 0x02000000
99 #define DDR_DDR_ZQ_CNTL 0x89080600
100 #define DDR_CS0_CONFIG_2 0
101 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
102 #define SDRAM_CFG2_D_INIT 0x00000010
103 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
104 #define SDRAM_CFG2_FRC_SR 0x80000000
105 #define SDRAM_CFG_BI 0x00000001
106
107 #ifdef CONFIG_RAMBOOT_PBL
108 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
109 #endif
110
111 #ifdef CONFIG_SD_BOOT
112 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
113 #define CONFIG_SPL_FRAMEWORK
114 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
115 #define CONFIG_SPL_LIBCOMMON_SUPPORT
116 #define CONFIG_SPL_LIBGENERIC_SUPPORT
117 #define CONFIG_SPL_ENV_SUPPORT
118 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
119 #define CONFIG_SPL_I2C_SUPPORT
120 #define CONFIG_SPL_WATCHDOG_SUPPORT
121 #define CONFIG_SPL_SERIAL_SUPPORT
122 #define CONFIG_SPL_MMC_SUPPORT
123 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
124 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
125
126 #define CONFIG_SPL_TEXT_BASE 0x10000000
127 #define CONFIG_SPL_MAX_SIZE 0x1a000
128 #define CONFIG_SPL_STACK 0x1001d000
129 #define CONFIG_SPL_PAD_TO 0x1c000
130 #define CONFIG_SYS_TEXT_BASE 0x82000000
131
132 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
133 CONFIG_SYS_MONITOR_LEN)
134 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
135 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
136 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
137 #define CONFIG_SYS_MONITOR_LEN 0x80000
138 #endif
139
140 #ifdef CONFIG_QSPI_BOOT
141 #define CONFIG_SYS_TEXT_BASE 0x40010000
142 #define CONFIG_SYS_NO_FLASH
143 #endif
144
145 #ifndef CONFIG_SYS_TEXT_BASE
146 #define CONFIG_SYS_TEXT_BASE 0x60100000
147 #endif
148
149 #define CONFIG_NR_DRAM_BANKS 1
150 #define PHYS_SDRAM 0x80000000
151 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
152
153 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
154 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
155
156 #define CONFIG_SYS_HAS_SERDES
157
158 #define CONFIG_FSL_CAAM /* Enable CAAM */
159
160 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
161 !defined(CONFIG_QSPI_BOOT)
162 #define CONFIG_U_QE
163 #endif
164
165 /*
166 * IFC Definitions
167 */
168 #ifndef CONFIG_QSPI_BOOT
169 #define CONFIG_FSL_IFC
170 #define CONFIG_SYS_FLASH_BASE 0x60000000
171 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
172
173 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
174 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
175 CSPR_PORT_SIZE_16 | \
176 CSPR_MSEL_NOR | \
177 CSPR_V)
178 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
179
180 /* NOR Flash Timing Params */
181 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
182 CSOR_NOR_TRHZ_80)
183 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
184 FTIM0_NOR_TEADC(0x5) | \
185 FTIM0_NOR_TAVDS(0x0) | \
186 FTIM0_NOR_TEAHC(0x5))
187 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
188 FTIM1_NOR_TRAD_NOR(0x1A) | \
189 FTIM1_NOR_TSEQRAD_NOR(0x13))
190 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
191 FTIM2_NOR_TCH(0x4) | \
192 FTIM2_NOR_TWP(0x1c) | \
193 FTIM2_NOR_TWPH(0x0e))
194 #define CONFIG_SYS_NOR_FTIM3 0
195
196 #define CONFIG_FLASH_CFI_DRIVER
197 #define CONFIG_SYS_FLASH_CFI
198 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
199 #define CONFIG_SYS_FLASH_QUIET_TEST
200 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
201
202 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
203 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
204 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
205 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
206
207 #define CONFIG_SYS_FLASH_EMPTY_INFO
208 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
209
210 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
211 #define CONFIG_SYS_WRITE_SWAPPED_DATA
212 #endif
213
214 /* CPLD */
215
216 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
217 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
218
219 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
220 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
221 CSPR_PORT_SIZE_8 | \
222 CSPR_MSEL_GPCM | \
223 CSPR_V)
224 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
225 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
226 CSOR_NOR_NOR_MODE_AVD_NOR | \
227 CSOR_NOR_TRHZ_80)
228
229 /* CPLD Timing parameters for IFC GPCM */
230 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
231 FTIM0_GPCM_TEADC(0xf) | \
232 FTIM0_GPCM_TEAHC(0xf))
233 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
234 FTIM1_GPCM_TRAD(0x3f))
235 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
236 FTIM2_GPCM_TCH(0xf) | \
237 FTIM2_GPCM_TWP(0xff))
238 #define CONFIG_SYS_FPGA_FTIM3 0x0
239 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
240 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
241 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
242 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
243 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
244 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
245 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
246 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
247 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
248 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
249 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
250 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
251 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
252 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
253 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
254 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
255
256 /*
257 * Serial Port
258 */
259 #ifdef CONFIG_LPUART
260 #define CONFIG_FSL_LPUART
261 #define CONFIG_LPUART_32B_REG
262 #else
263 #define CONFIG_CONS_INDEX 1
264 #define CONFIG_SYS_NS16550
265 #define CONFIG_SYS_NS16550_SERIAL
266 #define CONFIG_SYS_NS16550_REG_SIZE 1
267 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
268 #endif
269
270 #define CONFIG_BAUDRATE 115200
271
272 /*
273 * I2C
274 */
275 #define CONFIG_CMD_I2C
276 #define CONFIG_SYS_I2C
277 #define CONFIG_SYS_I2C_MXC
278 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
279 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
280 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
281
282 /* EEPROM */
283 #ifndef CONFIG_SD_BOOT
284 #define CONFIG_ID_EEPROM
285 #define CONFIG_SYS_I2C_EEPROM_NXID
286 #define CONFIG_SYS_EEPROM_BUS_NUM 1
287 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
288 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
289 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
290 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
291 #endif
292
293 /*
294 * MMC
295 */
296 #define CONFIG_MMC
297 #define CONFIG_CMD_MMC
298 #define CONFIG_FSL_ESDHC
299 #define CONFIG_GENERIC_MMC
300
301 #define CONFIG_CMD_FAT
302 #define CONFIG_DOS_PARTITION
303
304 /* SPI */
305 #ifdef CONFIG_QSPI_BOOT
306 /* QSPI */
307 #define CONFIG_FSL_QSPI
308 #define QSPI0_AMBA_BASE 0x40000000
309 #define FSL_QSPI_FLASH_SIZE (1 << 24)
310 #define FSL_QSPI_FLASH_NUM 2
311 #define CONFIG_SPI_FLASH_STMICRO
312
313 /* DSPI */
314 #define CONFIG_FSL_DSPI
315 #define CONFIG_SPI_FLASH_ATMEL
316 #endif
317
318 /* DM SPI */
319 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
320 #define CONFIG_CMD_SF
321 #define CONFIG_DM_SPI_FLASH
322 #endif
323
324 /*
325 * Video
326 */
327 #define CONFIG_FSL_DCU_FB
328
329 #ifdef CONFIG_FSL_DCU_FB
330 #define CONFIG_VIDEO
331 #define CONFIG_CMD_BMP
332 #define CONFIG_CFB_CONSOLE
333 #define CONFIG_VGA_AS_SINGLE_DEVICE
334 #define CONFIG_VIDEO_LOGO
335 #define CONFIG_VIDEO_BMP_LOGO
336
337 #define CONFIG_FSL_DCU_SII9022A
338 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
339 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
340 #endif
341
342 /*
343 * eTSEC
344 */
345 #define CONFIG_TSEC_ENET
346
347 #ifdef CONFIG_TSEC_ENET
348 #define CONFIG_MII
349 #define CONFIG_MII_DEFAULT_TSEC 1
350 #define CONFIG_TSEC1 1
351 #define CONFIG_TSEC1_NAME "eTSEC1"
352 #define CONFIG_TSEC2 1
353 #define CONFIG_TSEC2_NAME "eTSEC2"
354 #define CONFIG_TSEC3 1
355 #define CONFIG_TSEC3_NAME "eTSEC3"
356
357 #define TSEC1_PHY_ADDR 2
358 #define TSEC2_PHY_ADDR 0
359 #define TSEC3_PHY_ADDR 1
360
361 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
362 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
363 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
364
365 #define TSEC1_PHYIDX 0
366 #define TSEC2_PHYIDX 0
367 #define TSEC3_PHYIDX 0
368
369 #define CONFIG_ETHPRIME "eTSEC1"
370
371 #define CONFIG_PHY_GIGE
372 #define CONFIG_PHYLIB
373 #define CONFIG_PHY_ATHEROS
374
375 #define CONFIG_HAS_ETH0
376 #define CONFIG_HAS_ETH1
377 #define CONFIG_HAS_ETH2
378 #endif
379
380 /* PCIe */
381 #define CONFIG_PCI /* Enable PCI/PCIE */
382 #define CONFIG_PCIE1 /* PCIE controler 1 */
383 #define CONFIG_PCIE2 /* PCIE controler 2 */
384 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
385 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
386
387 #define CONFIG_SYS_PCI_64BIT
388
389 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
390 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
391 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
392 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
393
394 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
395 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
396 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
397
398 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
399 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
400 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
401
402 #ifdef CONFIG_PCI
403 #define CONFIG_PCI_PNP
404 #define CONFIG_PCI_SCAN_SHOW
405 #define CONFIG_CMD_PCI
406 #endif
407
408 #define CONFIG_CMD_PING
409 #define CONFIG_CMD_DHCP
410 #define CONFIG_CMD_MII
411
412 #define CONFIG_CMDLINE_TAG
413 #define CONFIG_CMDLINE_EDITING
414
415 #define CONFIG_ARMV7_NONSEC
416 #define CONFIG_ARMV7_VIRT
417 #define CONFIG_PEN_ADDR_BIG_ENDIAN
418 #define CONFIG_LS102XA_NS_ACCESS
419 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
420 #define CONFIG_TIMER_CLK_FREQ 12500000
421
422 #define CONFIG_HWCONFIG
423 #define HWCONFIG_BUFFER_SIZE 256
424
425 #define CONFIG_FSL_DEVICE_DISABLE
426
427 #define CONFIG_BOOTDELAY 3
428
429 #ifdef CONFIG_LPUART
430 #define CONFIG_EXTRA_ENV_SETTINGS \
431 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
432 "initrd_high=0xcfffffff\0" \
433 "fdt_high=0xcfffffff\0"
434 #else
435 #define CONFIG_EXTRA_ENV_SETTINGS \
436 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
437 "initrd_high=0xcfffffff\0" \
438 "fdt_high=0xcfffffff\0"
439 #endif
440
441 /*
442 * Miscellaneous configurable options
443 */
444 #define CONFIG_SYS_LONGHELP /* undef to save memory */
445 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
446 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
447 #define CONFIG_AUTO_COMPLETE
448 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
449 #define CONFIG_SYS_PBSIZE \
450 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
451 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
452 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
453
454 #define CONFIG_CMD_GREPENV
455 #define CONFIG_CMD_MEMINFO
456 #define CONFIG_CMD_MEMTEST
457 #define CONFIG_SYS_MEMTEST_START 0x80000000
458 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
459
460 #define CONFIG_SYS_LOAD_ADDR 0x82000000
461
462 #define CONFIG_LS102XA_STREAM_ID
463
464 /*
465 * Stack sizes
466 * The stack sizes are set up in start.S using the settings below
467 */
468 #define CONFIG_STACKSIZE (30 * 1024)
469
470 #define CONFIG_SYS_INIT_SP_OFFSET \
471 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
472 #define CONFIG_SYS_INIT_SP_ADDR \
473 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
474
475 #ifdef CONFIG_SPL_BUILD
476 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
477 #else
478 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
479 #endif
480
481 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
482
483 /*
484 * Environment
485 */
486 #define CONFIG_ENV_OVERWRITE
487
488 #if defined(CONFIG_SD_BOOT)
489 #define CONFIG_ENV_OFFSET 0x100000
490 #define CONFIG_ENV_IS_IN_MMC
491 #define CONFIG_SYS_MMC_ENV_DEV 0
492 #define CONFIG_ENV_SIZE 0x20000
493 #elif defined(CONFIG_QSPI_BOOT)
494 #define CONFIG_ENV_IS_IN_SPI_FLASH
495 #define CONFIG_ENV_SIZE 0x2000
496 #define CONFIG_ENV_OFFSET 0x100000
497 #define CONFIG_ENV_SECT_SIZE 0x10000
498 #else
499 #define CONFIG_ENV_IS_IN_FLASH
500 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
501 #define CONFIG_ENV_SIZE 0x20000
502 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
503 #endif
504
505 #define CONFIG_OF_LIBFDT
506 #define CONFIG_OF_BOARD_SETUP
507 #define CONFIG_CMD_BOOTZ
508
509 #define CONFIG_MISC_INIT_R
510
511 /* Hash command with SHA acceleration supported in hardware */
512 #define CONFIG_CMD_HASH
513 #define CONFIG_SHA_HW_ACCEL
514
515 #ifdef CONFIG_SECURE_BOOT
516 #define CONFIG_CMD_BLOB
517 #include <asm/fsl_secure_boot.h>
518 #endif
519
520 #endif