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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/ls1021atwr.h
88e936b407960792d9950f7f81c6d86c374345b9
2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #define CONFIG_LS102XA
12 #define CONFIG_ARMV7_PSCI
15 #define CONFIG_DISPLAY_CPUINFO
16 #define CONFIG_DISPLAY_BOARDINFO
18 #define CONFIG_SKIP_LOWLEVEL_INIT
19 #define CONFIG_BOARD_EARLY_INIT_F
20 #define CONFIG_DEEP_SLEEP
21 #ifdef CONFIG_DEEP_SLEEP
22 #define CONFIG_SILENT_CONSOLE
26 * Size of malloc() pool
28 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 16 * 1024 * 1024)
30 #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR
31 #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
38 * EHCI Support - disbaled by default as
39 * there is no signal coming out of soc on
40 * this board for this controller. However,
41 * the silicon still has this controller,
42 * and anyone can use this controller by
43 * taking signals out on their board.
46 /*#define CONFIG_HAS_FSL_DR_USB*/
48 #ifdef CONFIG_HAS_FSL_DR_USB
49 #define CONFIG_USB_EHCI
50 #define CONFIG_USB_EHCI_FSL
51 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
54 /* XHCI Support - enabled by default */
55 #define CONFIG_HAS_FSL_XHCI_USB
57 #ifdef CONFIG_HAS_FSL_XHCI_USB
58 #define CONFIG_USB_XHCI_FSL
59 #define CONFIG_USB_XHCI_DWC3
60 #define CONFIG_USB_XHCI
61 #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
62 #define CONFIG_SYS_USB_XHCI_MAX_ROOT_PORTS 2
65 #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_XHCI_USB)
66 #define CONFIG_CMD_USB
67 #define CONFIG_USB_STORAGE
68 #define CONFIG_CMD_EXT2
72 * Generic Timer Definitions
74 #define GENERIC_TIMER_CLK 12500000
76 #define CONFIG_SYS_CLK_FREQ 100000000
77 #define CONFIG_DDR_CLK_FREQ 100000000
79 #define DDR_SDRAM_CFG 0x470c0008
80 #define DDR_CS0_BNDS 0x008000bf
81 #define DDR_CS0_CONFIG 0x80014302
82 #define DDR_TIMING_CFG_0 0x50550004
83 #define DDR_TIMING_CFG_1 0xbcb38c56
84 #define DDR_TIMING_CFG_2 0x0040d120
85 #define DDR_TIMING_CFG_3 0x010e1000
86 #define DDR_TIMING_CFG_4 0x00000001
87 #define DDR_TIMING_CFG_5 0x03401400
88 #define DDR_SDRAM_CFG_2 0x00401010
89 #define DDR_SDRAM_MODE 0x00061c60
90 #define DDR_SDRAM_MODE_2 0x00180000
91 #define DDR_SDRAM_INTERVAL 0x18600618
92 #define DDR_DDR_WRLVL_CNTL 0x8655f605
93 #define DDR_DDR_WRLVL_CNTL_2 0x05060607
94 #define DDR_DDR_WRLVL_CNTL_3 0x05050505
95 #define DDR_DDR_CDR1 0x80040000
96 #define DDR_DDR_CDR2 0x00000001
97 #define DDR_SDRAM_CLK_CNTL 0x02000000
98 #define DDR_DDR_ZQ_CNTL 0x89080600
99 #define DDR_CS0_CONFIG_2 0
100 #define DDR_SDRAM_CFG_MEM_EN 0x80000000
101 #define SDRAM_CFG2_D_INIT 0x00000010
102 #define DDR_CDR2_VREF_TRAIN_EN 0x00000080
103 #define SDRAM_CFG2_FRC_SR 0x80000000
104 #define SDRAM_CFG_BI 0x00000001
106 #ifdef CONFIG_RAMBOOT_PBL
107 #define CONFIG_SYS_FSL_PBL_PBI board/freescale/ls1021atwr/ls102xa_pbi.cfg
110 #ifdef CONFIG_SD_BOOT
111 #define CONFIG_SYS_FSL_PBL_RCW board/freescale/ls1021atwr/ls102xa_rcw_sd.cfg
112 #define CONFIG_SPL_FRAMEWORK
113 #define CONFIG_SPL_LDSCRIPT "arch/$(ARCH)/cpu/u-boot-spl.lds"
114 #define CONFIG_SPL_LIBCOMMON_SUPPORT
115 #define CONFIG_SPL_LIBGENERIC_SUPPORT
116 #define CONFIG_SPL_ENV_SUPPORT
117 #define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
118 #define CONFIG_SPL_I2C_SUPPORT
119 #define CONFIG_SPL_WATCHDOG_SUPPORT
120 #define CONFIG_SPL_SERIAL_SUPPORT
121 #define CONFIG_SPL_MMC_SUPPORT
122 #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0xe8
123 #define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x400
125 #define CONFIG_SPL_TEXT_BASE 0x10000000
126 #define CONFIG_SPL_MAX_SIZE 0x1a000
127 #define CONFIG_SPL_STACK 0x1001d000
128 #define CONFIG_SPL_PAD_TO 0x1c000
129 #define CONFIG_SYS_TEXT_BASE 0x82000000
131 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
132 CONFIG_SYS_MONITOR_LEN)
133 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
134 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
135 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
136 #define CONFIG_SYS_MONITOR_LEN 0x80000
139 #ifdef CONFIG_QSPI_BOOT
140 #define CONFIG_SYS_TEXT_BASE 0x40010000
141 #define CONFIG_SYS_NO_FLASH
144 #ifndef CONFIG_SYS_TEXT_BASE
145 #define CONFIG_SYS_TEXT_BASE 0x60100000
148 #define CONFIG_NR_DRAM_BANKS 1
149 #define PHYS_SDRAM 0x80000000
150 #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
152 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL
153 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
155 #define CONFIG_SYS_HAS_SERDES
157 #define CONFIG_FSL_CAAM /* Enable CAAM */
159 #if !defined(CONFIG_SD_BOOT) && !defined(CONFIG_NAND_BOOT) && \
160 !defined(CONFIG_QSPI_BOOT)
167 #ifndef CONFIG_QSPI_BOOT
168 #define CONFIG_FSL_IFC
169 #define CONFIG_SYS_FLASH_BASE 0x60000000
170 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
172 #define CONFIG_SYS_NOR0_CSPR_EXT (0x0)
173 #define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
174 CSPR_PORT_SIZE_16 | \
177 #define CONFIG_SYS_NOR_AMASK IFC_AMASK(128 * 1024 * 1024)
179 /* NOR Flash Timing Params */
180 #define CONFIG_SYS_NOR_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
182 #define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
183 FTIM0_NOR_TEADC(0x5) | \
184 FTIM0_NOR_TAVDS(0x0) | \
185 FTIM0_NOR_TEAHC(0x5))
186 #define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
187 FTIM1_NOR_TRAD_NOR(0x1A) | \
188 FTIM1_NOR_TSEQRAD_NOR(0x13))
189 #define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
190 FTIM2_NOR_TCH(0x4) | \
191 FTIM2_NOR_TWP(0x1c) | \
192 FTIM2_NOR_TWPH(0x0e))
193 #define CONFIG_SYS_NOR_FTIM3 0
195 #define CONFIG_FLASH_CFI_DRIVER
196 #define CONFIG_SYS_FLASH_CFI
197 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
198 #define CONFIG_SYS_FLASH_QUIET_TEST
199 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
201 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
202 #define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
203 #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
204 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
206 #define CONFIG_SYS_FLASH_EMPTY_INFO
207 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS }
209 #define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
210 #define CONFIG_SYS_WRITE_SWAPPED_DATA
215 #define CONFIG_SYS_CPLD_BASE 0x7fb00000
216 #define CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
218 #define CONFIG_SYS_FPGA_CSPR_EXT (0x0)
219 #define CONFIG_SYS_FPGA_CSPR (CSPR_PHYS_ADDR(CPLD_BASE_PHYS) | \
223 #define CONFIG_SYS_FPGA_AMASK IFC_AMASK(64 * 1024)
224 #define CONFIG_SYS_FPGA_CSOR (CSOR_NOR_ADM_SHIFT(4) | \
225 CSOR_NOR_NOR_MODE_AVD_NOR | \
228 /* CPLD Timing parameters for IFC GPCM */
229 #define CONFIG_SYS_FPGA_FTIM0 (FTIM0_GPCM_TACSE(0xf) | \
230 FTIM0_GPCM_TEADC(0xf) | \
231 FTIM0_GPCM_TEAHC(0xf))
232 #define CONFIG_SYS_FPGA_FTIM1 (FTIM1_GPCM_TACO(0xff) | \
233 FTIM1_GPCM_TRAD(0x3f))
234 #define CONFIG_SYS_FPGA_FTIM2 (FTIM2_GPCM_TCS(0xf) | \
235 FTIM2_GPCM_TCH(0xf) | \
236 FTIM2_GPCM_TWP(0xff))
237 #define CONFIG_SYS_FPGA_FTIM3 0x0
238 #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
239 #define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
240 #define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
241 #define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
242 #define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
243 #define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
244 #define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
245 #define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
246 #define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_FPGA_CSPR_EXT
247 #define CONFIG_SYS_CSPR1 CONFIG_SYS_FPGA_CSPR
248 #define CONFIG_SYS_AMASK1 CONFIG_SYS_FPGA_AMASK
249 #define CONFIG_SYS_CSOR1 CONFIG_SYS_FPGA_CSOR
250 #define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_FPGA_FTIM0
251 #define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_FPGA_FTIM1
252 #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_FPGA_FTIM2
253 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_FPGA_FTIM3
259 #define CONFIG_FSL_LPUART
260 #define CONFIG_LPUART_32B_REG
262 #define CONFIG_CONS_INDEX 1
263 #define CONFIG_SYS_NS16550
264 #define CONFIG_SYS_NS16550_SERIAL
265 #define CONFIG_SYS_NS16550_REG_SIZE 1
266 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
269 #define CONFIG_BAUDRATE 115200
274 #define CONFIG_CMD_I2C
275 #define CONFIG_SYS_I2C
276 #define CONFIG_SYS_I2C_MXC
277 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
278 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
279 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
282 #ifndef CONFIG_SD_BOOT
283 #define CONFIG_ID_EEPROM
284 #define CONFIG_SYS_I2C_EEPROM_NXID
285 #define CONFIG_SYS_EEPROM_BUS_NUM 1
286 #define CONFIG_SYS_I2C_EEPROM_ADDR 0x53
287 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
288 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
289 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
296 #define CONFIG_CMD_MMC
297 #define CONFIG_FSL_ESDHC
298 #define CONFIG_GENERIC_MMC
300 #define CONFIG_CMD_FAT
301 #define CONFIG_DOS_PARTITION
304 #ifdef CONFIG_QSPI_BOOT
306 #define CONFIG_FSL_QSPI
307 #define QSPI0_AMBA_BASE 0x40000000
308 #define FSL_QSPI_FLASH_SIZE (1 << 24)
309 #define FSL_QSPI_FLASH_NUM 2
310 #define CONFIG_SPI_FLASH_STMICRO
313 #define CONFIG_FSL_DSPI
314 #define CONFIG_SPI_FLASH_ATMEL
318 #if defined(CONFIG_FSL_DSPI) || defined(CONFIG_FSL_QSPI)
319 #define CONFIG_CMD_SF
320 #define CONFIG_DM_SPI_FLASH
326 #define CONFIG_FSL_DCU_FB
328 #ifdef CONFIG_FSL_DCU_FB
330 #define CONFIG_CMD_BMP
331 #define CONFIG_CFB_CONSOLE
332 #define CONFIG_VGA_AS_SINGLE_DEVICE
333 #define CONFIG_VIDEO_LOGO
334 #define CONFIG_VIDEO_BMP_LOGO
336 #define CONFIG_FSL_DCU_SII9022A
337 #define CONFIG_SYS_I2C_DVI_BUS_NUM 1
338 #define CONFIG_SYS_I2C_DVI_ADDR 0x39
344 #define CONFIG_TSEC_ENET
346 #ifdef CONFIG_TSEC_ENET
348 #define CONFIG_MII_DEFAULT_TSEC 1
349 #define CONFIG_TSEC1 1
350 #define CONFIG_TSEC1_NAME "eTSEC1"
351 #define CONFIG_TSEC2 1
352 #define CONFIG_TSEC2_NAME "eTSEC2"
353 #define CONFIG_TSEC3 1
354 #define CONFIG_TSEC3_NAME "eTSEC3"
356 #define TSEC1_PHY_ADDR 2
357 #define TSEC2_PHY_ADDR 0
358 #define TSEC3_PHY_ADDR 1
360 #define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
361 #define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
362 #define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
364 #define TSEC1_PHYIDX 0
365 #define TSEC2_PHYIDX 0
366 #define TSEC3_PHYIDX 0
368 #define CONFIG_ETHPRIME "eTSEC1"
370 #define CONFIG_PHY_GIGE
371 #define CONFIG_PHYLIB
372 #define CONFIG_PHY_ATHEROS
374 #define CONFIG_HAS_ETH0
375 #define CONFIG_HAS_ETH1
376 #define CONFIG_HAS_ETH2
380 #define CONFIG_PCI /* Enable PCI/PCIE */
381 #define CONFIG_PCIE1 /* PCIE controler 1 */
382 #define CONFIG_PCIE2 /* PCIE controler 2 */
383 #define CONFIG_PCIE_LAYERSCAPE /* Use common FSL Layerscape PCIe code */
384 #define FSL_PCIE_COMPAT "fsl,ls1021a-pcie"
386 #define CONFIG_SYS_PCI_64BIT
388 #define CONFIG_SYS_PCIE_CFG0_PHYS_OFF 0x00000000
389 #define CONFIG_SYS_PCIE_CFG0_SIZE 0x00001000 /* 4k */
390 #define CONFIG_SYS_PCIE_CFG1_PHYS_OFF 0x00001000
391 #define CONFIG_SYS_PCIE_CFG1_SIZE 0x00001000 /* 4k */
393 #define CONFIG_SYS_PCIE_IO_BUS 0x00000000
394 #define CONFIG_SYS_PCIE_IO_PHYS_OFF 0x00010000
395 #define CONFIG_SYS_PCIE_IO_SIZE 0x00010000 /* 64k */
397 #define CONFIG_SYS_PCIE_MEM_BUS 0x08000000
398 #define CONFIG_SYS_PCIE_MEM_PHYS_OFF 0x04000000
399 #define CONFIG_SYS_PCIE_MEM_SIZE 0x08000000 /* 128M */
402 #define CONFIG_PCI_PNP
403 #define CONFIG_PCI_SCAN_SHOW
404 #define CONFIG_CMD_PCI
407 #define CONFIG_CMD_PING
408 #define CONFIG_CMD_DHCP
409 #define CONFIG_CMD_MII
411 #define CONFIG_CMDLINE_TAG
412 #define CONFIG_CMDLINE_EDITING
414 #define CONFIG_ARMV7_NONSEC
415 #define CONFIG_ARMV7_VIRT
416 #define CONFIG_PEN_ADDR_BIG_ENDIAN
417 #define CONFIG_LS102XA_NS_ACCESS
418 #define CONFIG_SMP_PEN_ADDR 0x01ee0200
419 #define CONFIG_TIMER_CLK_FREQ 12500000
421 #define CONFIG_HWCONFIG
422 #define HWCONFIG_BUFFER_SIZE 256
424 #define CONFIG_FSL_DEVICE_DISABLE
426 #define CONFIG_BOOTDELAY 3
429 #define CONFIG_EXTRA_ENV_SETTINGS \
430 "bootargs=root=/dev/ram0 rw console=ttyLP0,115200\0" \
431 "initrd_high=0xcfffffff\0" \
432 "fdt_high=0xcfffffff\0"
434 #define CONFIG_EXTRA_ENV_SETTINGS \
435 "bootargs=root=/dev/ram0 rw console=ttyS0,115200\0" \
436 "initrd_high=0xcfffffff\0" \
437 "fdt_high=0xcfffffff\0"
441 * Miscellaneous configurable options
443 #define CONFIG_SYS_LONGHELP /* undef to save memory */
444 #define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
445 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
446 #define CONFIG_AUTO_COMPLETE
447 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
448 #define CONFIG_SYS_PBSIZE \
449 (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
450 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
451 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
453 #define CONFIG_CMD_GREPENV
454 #define CONFIG_CMD_MEMINFO
455 #define CONFIG_CMD_MEMTEST
456 #define CONFIG_SYS_MEMTEST_START 0x80000000
457 #define CONFIG_SYS_MEMTEST_END 0x9fffffff
459 #define CONFIG_SYS_LOAD_ADDR 0x82000000
461 #define CONFIG_LS102XA_STREAM_ID
465 * The stack sizes are set up in start.S using the settings below
467 #define CONFIG_STACKSIZE (30 * 1024)
469 #define CONFIG_SYS_INIT_SP_OFFSET \
470 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
471 #define CONFIG_SYS_INIT_SP_ADDR \
472 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
474 #ifdef CONFIG_SPL_BUILD
475 #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
477 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
480 #define CONFIG_SYS_QE_FW_ADDR 0x67f40000
485 #define CONFIG_ENV_OVERWRITE
487 #if defined(CONFIG_SD_BOOT)
488 #define CONFIG_ENV_OFFSET 0x100000
489 #define CONFIG_ENV_IS_IN_MMC
490 #define CONFIG_SYS_MMC_ENV_DEV 0
491 #define CONFIG_ENV_SIZE 0x20000
492 #elif defined(CONFIG_QSPI_BOOT)
493 #define CONFIG_ENV_IS_IN_SPI_FLASH
494 #define CONFIG_ENV_SIZE 0x2000
495 #define CONFIG_ENV_OFFSET 0x100000
496 #define CONFIG_ENV_SECT_SIZE 0x10000
498 #define CONFIG_ENV_IS_IN_FLASH
499 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
500 #define CONFIG_ENV_SIZE 0x20000
501 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
504 #define CONFIG_OF_LIBFDT
505 #define CONFIG_OF_BOARD_SETUP
506 #define CONFIG_CMD_BOOTZ
508 #define CONFIG_MISC_INIT_R
510 /* Hash command with SHA acceleration supported in hardware */
511 #define CONFIG_CMD_HASH
512 #define CONFIG_SHA_HW_ACCEL
514 #ifdef CONFIG_SECURE_BOOT
515 #define CONFIG_CMD_BLOB
516 #include <asm/fsl_secure_boot.h>