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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/ls1043a_common.h
2 * Copyright (C) 2015 Freescale Semiconductor
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __LS1043A_COMMON_H
8 #define __LS1043A_COMMON_H
10 #define CONFIG_REMAKE_ELF
11 #define CONFIG_FSL_LAYERSCAPE
12 #define CONFIG_LS1043A
16 #include <asm/arch/config.h>
18 /* Link Definitions */
19 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
21 #define CONFIG_SUPPORT_RAW_INITRD
23 #define CONFIG_SKIP_LOWLEVEL_INIT
24 #define CONFIG_BOARD_EARLY_INIT_F 1
26 #define CONFIG_VERY_BIG_RAM
27 #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000
28 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0
29 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
30 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
32 #define CPU_RELEASE_ADDR secondary_boot_func
34 /* Generic Timer Definitions */
35 #define COUNTER_FREQUENCY 25000000 /* 25MHz */
37 /* Size of malloc() pool */
38 #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 1024 * 1024)
41 #define CONFIG_CONS_INDEX 1
42 #define CONFIG_SYS_NS16550_SERIAL
43 #define CONFIG_SYS_NS16550_REG_SIZE 1
44 #define CONFIG_SYS_NS16550_CLK (get_serial_clock())
46 #define CONFIG_BAUDRATE 115200
47 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
51 #define CONFIG_SPL_FRAMEWORK
52 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
53 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
55 #define CONFIG_SPL_TEXT_BASE 0x10000000
56 #define CONFIG_SPL_MAX_SIZE 0x1d000
57 #define CONFIG_SPL_STACK 0x1001e000
58 #define CONFIG_SPL_PAD_TO 0x1d000
60 #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_TEXT_BASE + \
61 CONFIG_SYS_MONITOR_LEN)
62 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
63 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
64 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
65 #define CONFIG_SYS_MONITOR_LEN 0xa0000
69 #ifdef CONFIG_NAND_BOOT
70 #define CONFIG_SPL_PBL_PAD
71 #define CONFIG_SPL_FRAMEWORK
72 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
73 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
74 #define CONFIG_SPL_TEXT_BASE 0x10000000
75 #define CONFIG_SPL_MAX_SIZE 0x1a000
76 #define CONFIG_SPL_STACK 0x1001d000
77 #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
78 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
79 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000
80 #define CONFIG_SPL_BSS_START_ADDR 0x80100000
81 #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
82 #define CONFIG_SPL_BSS_MAX_SIZE 0x80000
83 #define CONFIG_SYS_MONITOR_LEN 0xa0000
87 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
88 #define CONFIG_FSL_IFC
90 * CONFIG_SYS_FLASH_BASE has the final address (core view)
91 * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
92 * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
93 * CONFIG_SYS_TEXT_BASE is linked to 0x60000000 for booting
95 #define CONFIG_SYS_FLASH_BASE 0x60000000
96 #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
97 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY 0x00000000
99 #ifndef CONFIG_SYS_NO_FLASH
100 #define CONFIG_FLASH_CFI_DRIVER
101 #define CONFIG_SYS_FLASH_CFI
102 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
103 #define CONFIG_SYS_FLASH_QUIET_TEST
104 #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
109 #define CONFIG_SYS_I2C
110 #define CONFIG_SYS_I2C_MXC
111 #define CONFIG_SYS_I2C_MXC_I2C1
112 #define CONFIG_SYS_I2C_MXC_I2C2
113 #define CONFIG_SYS_I2C_MXC_I2C3
114 #define CONFIG_SYS_I2C_MXC_I2C4
117 #define CONFIG_PCIE1 /* PCIE controller 1 */
118 #define CONFIG_PCIE2 /* PCIE controller 2 */
119 #define CONFIG_PCIE3 /* PCIE controller 3 */
122 #define CONFIG_NET_MULTI
123 #define CONFIG_PCI_SCAN_SHOW
124 #define CONFIG_CMD_PCI
127 /* Command line configuration */
128 #define CONFIG_CMD_ENV
132 #define CONFIG_FSL_ESDHC
133 #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33
134 #define CONFIG_GENERIC_MMC
135 #define CONFIG_DOS_PARTITION
139 #define CONFIG_FSL_DSPI
140 #ifdef CONFIG_FSL_DSPI
141 #define CONFIG_DM_SPI_FLASH
142 #define CONFIG_SPI_FLASH_STMICRO /* cs0 */
143 #define CONFIG_SPI_FLASH_SST /* cs1 */
144 #define CONFIG_SPI_FLASH_EON /* cs2 */
145 #if !defined(CONFIG_QSPI_BOOT) && !defined(CONFIG_SD_BOOT_QSPI)
146 #define CONFIG_SF_DEFAULT_BUS 1
147 #define CONFIG_SF_DEFAULT_CS 0
151 #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
154 #define CONFIG_SYS_DPAA_FMAN
155 #ifdef CONFIG_SYS_DPAA_FMAN
156 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000
158 #ifdef CONFIG_NAND_BOOT
159 /* Store Fman ucode at offeset 0x160000(11 blocks). */
160 #define CONFIG_SYS_QE_FMAN_FW_IN_NAND
161 #define CONFIG_SYS_FMAN_FW_ADDR (11 * CONFIG_SYS_NAND_BLOCK_SIZE)
162 #elif defined(CONFIG_SD_BOOT)
164 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
165 * about 1MB (2040 blocks), Env is stored after the image, and the env size is
166 * 0x2000 (16 blocks), 8 + 2040 + 16 = 2064, enlarge it to 2080(0x820).
168 #define CONFIG_SYS_QE_FMAN_FW_IN_MMC
169 #define CONFIG_SYS_FMAN_FW_ADDR (512 * 0x820)
170 #elif defined(CONFIG_QSPI_BOOT)
171 #define CONFIG_SYS_QE_FW_IN_SPIFLASH
172 #define CONFIG_SYS_FMAN_FW_ADDR 0x400d0000
173 #define CONFIG_ENV_SPI_BUS 0
174 #define CONFIG_ENV_SPI_CS 0
175 #define CONFIG_ENV_SPI_MAX_HZ 1000000
176 #define CONFIG_ENV_SPI_MODE 0x03
178 #define CONFIG_SYS_QE_FMAN_FW_IN_NOR
179 /* FMan fireware Pre-load address */
180 #define CONFIG_SYS_FMAN_FW_ADDR 0x60300000
182 #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
183 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
186 /* Miscellaneous configurable options */
187 #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
189 #define CONFIG_HWCONFIG
190 #define HWCONFIG_BUFFER_SIZE 128
192 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
193 #define MTDPARTS_DEFAULT "mtdparts=spi0.0:1m(uboot)," \
194 "5m(kernel),1m(dtb),9m(file_system)"
196 #define MTDPARTS_DEFAULT "mtdparts=60000000.nor:1m(nor_bank0_rcw)," \
197 "1m(nor_bank0_uboot),1m(nor_bank0_uboot_env)," \
198 "1m(nor_bank0_fman_uconde),40m(nor_bank0_fit)," \
199 "1m(nor_bank4_rcw),1m(nor_bank4_uboot)," \
200 "1m(nor_bank4_uboot_env),1m(nor_bank4_fman_ucode)," \
201 "40m(nor_bank4_fit);7e800000.flash:" \
202 "1m(nand_uboot),1m(nand_uboot_env)," \
203 "20m(nand_fit);spi0.0:1m(uboot)," \
204 "5m(kernel),1m(dtb),9m(file_system)"
207 /* Initial environment variables */
208 #define CONFIG_EXTRA_ENV_SETTINGS \
209 "hwconfig=fsl_ddr:bank_intlv=auto\0" \
210 "loadaddr=0x80100000\0" \
211 "fdt_high=0xffffffffffffffff\0" \
212 "initrd_high=0xffffffffffffffff\0" \
213 "kernel_start=0x61100000\0" \
214 "kernel_load=0xa0000000\0" \
215 "kernel_size=0x2800000\0" \
216 "console=ttyS0,115200\0" \
217 "mtdparts=" MTDPARTS_DEFAULT "\0"
219 #define CONFIG_BOOTARGS "console=ttyS0,115200 root=/dev/ram0 " \
220 "earlycon=uart8250,mmio,0x21c0500 " \
223 #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
224 #define CONFIG_BOOTCOMMAND "sf probe && sf read $kernel_load " \
225 "e0000 f00000 && bootm $kernel_load"
227 #define CONFIG_BOOTCOMMAND "cp.b $kernel_start $kernel_load " \
228 "$kernel_size && bootm $kernel_load"
231 /* Monitor Command Prompt */
232 #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
233 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
234 sizeof(CONFIG_SYS_PROMPT) + 16)
235 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */
236 #define CONFIG_SYS_LONGHELP
237 #define CONFIG_CMDLINE_EDITING 1
238 #define CONFIG_AUTO_COMPLETE
239 #define CONFIG_SYS_MAXARGS 64 /* max command args */
241 #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
243 /* Hash command with SHA acceleration supported in hardware */
244 #ifdef CONFIG_FSL_CAAM
245 #define CONFIG_CMD_HASH
246 #define CONFIG_SHA_HW_ACCEL
249 #endif /* __LS1043A_COMMON_H */