include/configs/ls2080a_common.h

   1 /*
   2  * Copyright 2017 NXP
   3  * Copyright (C) 2014 Freescale Semiconductor
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __LS2_COMMON_H
   9 #define __LS2_COMMON_H
  10
  11 #define CONFIG_REMAKE_ELF
  12 #define CONFIG_FSL_LAYERSCAPE
  13 #define CONFIG_MP
  14 #define CONFIG_GICV3
  15 #define CONFIG_FSL_TZPC_BP147
  16
  17 #include <asm/arch/stream_id_lsch3.h>
  18 #include <asm/arch/config.h>
  19
  20 /* Link Definitions */
  21 #define CONFIG_SYS_INIT_SP_ADDR         (CONFIG_SYS_FSL_OCRAM_BASE + 0xfff0)
  22
  23 /* We need architecture specific misc initializations */
  24
  25 /* Link Definitions */
  26 #ifndef CONFIG_QSPI_BOOT
  27 #ifdef CONFIG_SPL
  28 #define CONFIG_SYS_TEXT_BASE            0x80400000
  29 #else
  30 #define CONFIG_SYS_TEXT_BASE            0x30100000
  31 #endif
  32 #else
  33 #define CONFIG_SYS_TEXT_BASE            0x20100000
  34 #define CONFIG_ENV_IS_IN_SPI_FLASH
  35 #define CONFIG_ENV_SIZE                 0x2000          /* 8KB */
  36 #define CONFIG_ENV_OFFSET               0x300000        /* 3MB */
  37 #define CONFIG_ENV_SECT_SIZE            0x10000
  38 #endif
  39
  40 #define CONFIG_SUPPORT_RAW_INITRD
  41
  42 #define CONFIG_SKIP_LOWLEVEL_INIT
  43
  44 #ifndef CONFIG_SPL
  45 #define CONFIG_FSL_DDR_INTERACTIVE      /* Interactive debugging */
  46 #endif
  47 #ifndef CONFIG_SYS_FSL_DDR4
  48 #define CONFIG_SYS_DDR_RAW_TIMING
  49 #endif
  50
  51 #define CONFIG_SYS_FSL_DDR_INTLV_256B   /* force 256 byte interleaving */
  52
  53 #define CONFIG_VERY_BIG_RAM
  54 #define CONFIG_SYS_DDR_SDRAM_BASE       0x80000000UL
  55 #define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY       0
  56 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  57 #define CONFIG_SYS_DDR_BLOCK2_BASE      0x8080000000ULL
  58 #define CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS       2
  59
  60 /*
  61  * SMP Definitinos
  62  */
  63 #define CPU_RELEASE_ADDR                secondary_boot_func
  64
  65 #define CONFIG_SYS_FSL_OTHER_DDR_NUM_CTRLS
  66 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
  67 #define CONFIG_SYS_DP_DDR_BASE          0x6000000000ULL
  68 /*
  69  * DDR controller use 0 as the base address for binding.
  70  * It is mapped to CONFIG_SYS_DP_DDR_BASE for core to access.
  71  */
  72 #define CONFIG_SYS_DP_DDR_BASE_PHY      0
  73 #define CONFIG_DP_DDR_CTRL              2
  74 #define CONFIG_DP_DDR_NUM_CTRLS         1
  75 #endif
  76
  77 /* Generic Timer Definitions */
  78 /*
  79  * This is not an accurate number. It is used in start.S. The frequency
  80  * will be udpated later when get_bus_freq(0) is available.
  81  */
  82 #define COUNTER_FREQUENCY               25000000        /* 25MHz */
  83
  84 /* Size of malloc() pool */
  85 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 2048 * 1024)
  86
  87 /* I2C */
  88 #define CONFIG_SYS_I2C
  89 #define CONFIG_SYS_I2C_MXC
  90 #define CONFIG_SYS_I2C_MXC_I2C1         /* enable I2C bus 1 */
  91 #define CONFIG_SYS_I2C_MXC_I2C2         /* enable I2C bus 2 */
  92 #define CONFIG_SYS_I2C_MXC_I2C3         /* enable I2C bus 3 */
  93 #define CONFIG_SYS_I2C_MXC_I2C4         /* enable I2C bus 4 */
  94
  95 /* Serial Port */
  96 #define CONFIG_CONS_INDEX       1
  97 #define CONFIG_SYS_NS16550_SERIAL
  98 #define CONFIG_SYS_NS16550_REG_SIZE     1
  99 #define CONFIG_SYS_NS16550_CLK          (get_serial_clock())
 100
 101 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
 102
 103 /* IFC */
 104 #define CONFIG_FSL_IFC
 105
 106 /*
 107  * During booting, IFC is mapped at the region of 0x30000000.
 108  * But this region is limited to 256MB. To accommodate NOR, promjet
 109  * and FPGA. This region is divided as below:
 110  * 0x30000000 - 0x37ffffff : 128MB : NOR flash
 111  * 0x38000000 - 0x3BFFFFFF : 64MB  : Promjet
 112  * 0x3C000000 - 0x40000000 : 64MB  : FPGA etc
 113  *
 114  * To accommodate bigger NOR flash and other devices, we will map IFC
 115  * chip selects to as below:
 116  * 0x5_1000_0000..0x5_1fff_ffff Memory Hole
 117  * 0x5_2000_0000..0x5_3fff_ffff IFC CSx (FPGA, NAND and others 512MB)
 118  * 0x5_4000_0000..0x5_7fff_ffff ASIC or others 1GB
 119  * 0x5_8000_0000..0x5_bfff_ffff IFC CS0 1GB (NOR/Promjet)
 120  * 0x5_C000_0000..0x5_ffff_ffff IFC CS1 1GB (NOR/Promjet)
 121  *
 122  * For e.g. NOR flash at CS0 will be mapped to 0x580000000 after relocation.
 123  * CONFIG_SYS_FLASH_BASE has the final address (core view)
 124  * CONFIG_SYS_FLASH_BASE_PHYS has the final address (IFC view)
 125  * CONFIG_SYS_FLASH_BASE_PHYS_EARLY has the temporary IFC address
 126  * CONFIG_SYS_TEXT_BASE is linked to 0x30000000 for booting
 127  */
 128
 129 #define CONFIG_SYS_FLASH_BASE                   0x580000000ULL
 130 #define CONFIG_SYS_FLASH_BASE_PHYS              0x80000000
 131 #define CONFIG_SYS_FLASH_BASE_PHYS_EARLY        0x00000000
 132
 133 #define CONFIG_SYS_FLASH1_BASE_PHYS             0xC0000000
 134 #define CONFIG_SYS_FLASH1_BASE_PHYS_EARLY       0x8000000
 135
 136 #ifndef __ASSEMBLY__
 137 unsigned long long get_qixis_addr(void);
 138 #endif
 139 #define QIXIS_BASE                              get_qixis_addr()
 140 #define QIXIS_BASE_PHYS                         0x20000000
 141 #define QIXIS_BASE_PHYS_EARLY                   0xC000000
 142 #define QIXIS_STAT_PRES1                        0xb
 143 #define QIXIS_SDID_MASK                         0x07
 144 #define QIXIS_ESDHC_NO_ADAPTER                  0x7
 145
 146 #define CONFIG_SYS_NAND_BASE                    0x530000000ULL
 147 #define CONFIG_SYS_NAND_BASE_PHYS               0x30000000
 148
 149 /* MC firmware */
 150 /* TODO Actual DPL max length needs to be confirmed with the MC FW team */
 151 #define CONFIG_SYS_LS_MC_DPC_MAX_LENGTH     0x20000
 152 #define CONFIG_SYS_LS_MC_DRAM_DPC_OFFSET    0x00F00000
 153 #define CONFIG_SYS_LS_MC_DPL_MAX_LENGTH     0x20000
 154 #define CONFIG_SYS_LS_MC_DRAM_DPL_OFFSET    0x00F20000
 155 /* For LS2085A */
 156 #define CONFIG_SYS_LS_MC_AIOP_IMG_MAX_LENGTH    0x200000
 157 #define CONFIG_SYS_LS_MC_DRAM_AIOP_IMG_OFFSET   0x07000000
 158
 159 /* Define phy_reset function to boot the MC based on mcinitcmd.
 160  * This happens late enough to properly fixup u-boot env MAC addresses.
 161  */
 162 #define CONFIG_RESET_PHY_R
 163
 164 /*
 165  * Carve out a DDR region which will not be used by u-boot/Linux
 166  *
 167  * It will be used by MC and Debug Server. The MC region must be
 168  * 512MB aligned, so the min size to hide is 512MB.
 169  */
 170 #ifdef CONFIG_FSL_MC_ENET
 171 #define CONFIG_SYS_LS_MC_DRAM_BLOCK_MIN_SIZE            (512UL * 1024 * 1024)
 172 #endif
 173
 174 /* Command line configuration */
 175
 176 /* Miscellaneous configurable options */
 177 #define CONFIG_SYS_LOAD_ADDR    (CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000)
 178
 179 /* Physical Memory Map */
 180 /* fixme: these need to be checked against the board */
 181 #define CONFIG_CHIP_SELECTS_PER_CTRL    4
 182
 183 #define CONFIG_NR_DRAM_BANKS            3
 184
 185 #define CONFIG_HWCONFIG
 186 #define HWCONFIG_BUFFER_SIZE            128
 187
 188 /* Allow to overwrite serial and ethaddr */
 189 #define CONFIG_ENV_OVERWRITE
 190
 191 /* Initial environment variables */
 192 #define CONFIG_EXTRA_ENV_SETTINGS               \
 193         "hwconfig=fsl_ddr:bank_intlv=auto\0"    \
 194         "loadaddr=0x80100000\0"                 \
 195         "kernel_addr=0x100000\0"                \
 196         "ramdisk_addr=0x800000\0"               \
 197         "ramdisk_size=0x2000000\0"              \
 198         "fdt_high=0xa0000000\0"                 \
 199         "initrd_high=0xffffffffffffffff\0"      \
 200         "kernel_start=0x581000000\0"            \
 201         "kernel_load=0xa0000000\0"              \
 202         "kernel_size=0x2800000\0"               \
 203         "console=ttyAMA0,38400n8\0"             \
 204         "mcinitcmd=fsl_mc start mc 0x580a00000" \
 205         " 0x580e00000 \0"
 206
 207 #define CONFIG_BOOTARGS         "console=ttyS0,115200 root=/dev/ram0 " \
 208                                 "earlycon=uart8250,mmio,0x21c0500 " \
 209                                 "ramdisk_size=0x2000000 default_hugepagesz=2m" \
 210                                 " hugepagesz=2m hugepages=256"
 211 #define CONFIG_BOOTCOMMAND      "fsl_mc apply dpl 0x580d00000 &&" \
 212                                 " cp.b $kernel_start $kernel_load" \
 213                                 " $kernel_size && bootm $kernel_load"
 214
 215 /* Monitor Command Prompt */
 216 #define CONFIG_SYS_CBSIZE               512     /* Console I/O Buffer Size */
 217 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE + \
 218                                         sizeof(CONFIG_SYS_PROMPT) + 16)
 219 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE /* Boot args buffer */
 220 #define CONFIG_SYS_LONGHELP
 221 #define CONFIG_CMDLINE_EDITING          1
 222 #define CONFIG_AUTO_COMPLETE
 223 #define CONFIG_SYS_MAXARGS              64      /* max command args */
 224
 225 #define CONFIG_PANIC_HANG       /* do not reset board on panic */
 226
 227 #define CONFIG_SPL_BSS_START_ADDR       0x80100000
 228 #define CONFIG_SPL_BSS_MAX_SIZE         0x00100000
 229 #define CONFIG_SPL_FRAMEWORK
 230 #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds"
 231 #define CONFIG_SPL_MAX_SIZE             0x16000
 232 #define CONFIG_SPL_STACK                (CONFIG_SYS_FSL_OCRAM_BASE + 0x9ff0)
 233 #define CONFIG_SPL_TARGET               "u-boot-with-spl.bin"
 234 #define CONFIG_SPL_TEXT_BASE            0x1800a000
 235
 236 #ifdef CONFIG_NAND_BOOT
 237 #define CONFIG_SYS_NAND_U_BOOT_DST      0x80400000
 238 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 239 #endif
 240 #define CONFIG_SYS_SPL_MALLOC_SIZE      0x00100000
 241 #define CONFIG_SYS_SPL_MALLOC_START     0x80200000
 242 #define CONFIG_SYS_MONITOR_LEN          (640 * 1024)
 243
 244 #define CONFIG_SYS_BOOTM_LEN   (64 << 20)      /* Increase max gunzip size */
 245
 246 #endif /* __LS2_COMMON_H */