include/configs/lwmon5.h

   1 /*
   2  * (C) Copyright 2007
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * This program is free software; you can redistribute it and/or
   6  * modify it under the terms of the GNU General Public License as
   7  * published by the Free Software Foundation; either version 2 of
   8  * the License, or (at your option) any later version.
   9  *
  10  * This program is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  13  * GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this program; if not, write to the Free Software
  17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  18  * MA 02111-1307 USA
  19  */
  20
  21 /************************************************************************
  22  * lwmon5.h - configuration for lwmon5 board
  23  ***********************************************************************/
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*-----------------------------------------------------------------------
  28  * High Level Configuration Options
  29  *----------------------------------------------------------------------*/
  30 #define CONFIG_LWMON5           1               /* Board is lwmon5      */
  31 #define CONFIG_440EPX           1               /* Specific PPC440EPx   */
  32 #define CONFIG_440              1               /* ... PPC440 family    */
  33 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  34 #define CONFIG_SYS_CLK_FREQ     33300000        /* external freq to pll */
  35
  36 #define CONFIG_BOARD_EARLY_INIT_F 1     /* Call board_early_init_f      */
  37 #define CONFIG_BOARD_POSTCLK_INIT 1     /* Call board_postclk_init      */
  38 #define CONFIG_MISC_INIT_R      1       /* Call misc_init_r             */
  39
  40 /*-----------------------------------------------------------------------
  41  * Base addresses -- Note these are effective addresses where the
  42  * actual resources get mapped (not physical addresses)
  43  *----------------------------------------------------------------------*/
  44 #define CFG_MONITOR_LEN         (512 * 1024)    /* Reserve 512 kB for Monitor   */
  45 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserve 512 kB for malloc()  */
  46
  47 #define CFG_BOOT_BASE_ADDR      0xf0000000
  48 #define CFG_SDRAM_BASE          0x00000000      /* _must_ be 0          */
  49 #define CFG_FLASH_BASE          0xf8000000      /* start of FLASH       */
  50 #define CFG_MONITOR_BASE        TEXT_BASE
  51 #define CFG_LIME_BASE_0         0xc0000000
  52 #define CFG_LIME_BASE_1         0xc1000000
  53 #define CFG_LIME_BASE_2         0xc2000000
  54 #define CFG_LIME_BASE_3         0xc3000000
  55 #define CFG_FPGA_BASE_0         0xc4000000
  56 #define CFG_FPGA_BASE_1         0xc4200000
  57 #define CFG_OCM_BASE            0xe0010000      /* ocm                  */
  58 #define CFG_PCI_BASE            0xe0000000      /* Internal PCI regs    */
  59 #define CFG_PCI_MEMBASE         0x80000000      /* mapped pci memory    */
  60 #define CFG_PCI_MEMBASE1        CFG_PCI_MEMBASE  + 0x10000000
  61 #define CFG_PCI_MEMBASE2        CFG_PCI_MEMBASE1 + 0x10000000
  62 #define CFG_PCI_MEMBASE3        CFG_PCI_MEMBASE2 + 0x10000000
  63
  64 /* Don't change either of these */
  65 #define CFG_PERIPHERAL_BASE     0xef600000      /* internal peripherals */
  66
  67 #define CFG_USB2D0_BASE         0xe0000100
  68 #define CFG_USB_DEVICE          0xe0000000
  69 #define CFG_USB_HOST            0xe0000400
  70
  71 /*-----------------------------------------------------------------------
  72  * Initial RAM & stack pointer
  73  *----------------------------------------------------------------------*/
  74 /* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache     */
  75 #define CFG_INIT_RAM_ADDR       CFG_OCM_BASE    /* OCM                  */
  76 #define CFG_OCM_DATA_ADDR       CFG_OCM_BASE
  77
  78 #define CFG_INIT_RAM_END        (4 << 10)
  79 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data */
  80 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  81 #define CFG_POST_WORD_ADDR      (CFG_GBL_DATA_OFFSET - 0x4)
  82 #define CFG_INIT_SP_OFFSET      CFG_POST_WORD_ADDR
  83
  84 /*-----------------------------------------------------------------------
  85  * Serial Port
  86  *----------------------------------------------------------------------*/
  87 #undef CFG_EXT_SERIAL_CLOCK             /* no external clock provided   */
  88 #define CONFIG_BAUDRATE         115200
  89 #define CONFIG_SERIAL_MULTI     1
  90 /* define this if you want console on UART1 */
  91 #define CONFIG_UART1_CONSOLE    1       /* use UART1 as console         */
  92
  93 #define CFG_BAUDRATE_TABLE                                              \
  94         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
  95
  96 /*-----------------------------------------------------------------------
  97  * Environment
  98  *----------------------------------------------------------------------*/
  99 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 100
 101 /*-----------------------------------------------------------------------
 102  * FLASH related
 103  *----------------------------------------------------------------------*/
 104 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 105 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 106
 107 #define CFG_FLASH0              0xFC000000
 108 #define CFG_FLASH1              0xF8000000
 109 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH1, CFG_FLASH0 }
 110
 111 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 112 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 113
 114 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 115 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 116
 117 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 118 #define CFG_FLASH_PROTECTION    1       /* use hardware flash protection        */
 119
 120 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 121 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
 122
 123 #define CFG_ENV_SECT_SIZE       0x40000 /* size of one complete sector          */
 124 #define CFG_ENV_ADDR            ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE)
 125 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 126
 127 /* Address and size of Redundant Environment Sector     */
 128 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 129 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 130
 131 /*-----------------------------------------------------------------------
 132  * DDR SDRAM
 133  *----------------------------------------------------------------------*/
 134 #define CFG_MBYTES_SDRAM        (256)           /* 256MB                        */
 135 #define CFG_DDR_CACHED_ADDR     0x40000000      /* setup 2nd TLB cached here    */
 136 #define CONFIG_DDR_DATA_EYE     1               /* use DDR2 optimization        */
 137 #if 0 /* test-only: disable ECC for now */
 138 #define CONFIG_DDR_ECC          1               /* enable ECC                   */
 139 #define CFG_POST_ECC_ON         CFG_POST_ECC
 140 #else
 141 #define CFG_POST_ECC_ON         0
 142 #endif
 143
 144 /* POST support */
 145 #define CONFIG_POST             (CFG_POST_CACHE    | \
 146                                  CFG_POST_CPU      | \
 147                                  CFG_POST_ECC_ON   | \
 148                                  CFG_POST_ETHER    | \
 149                                  CFG_POST_FPU      | \
 150                                  CFG_POST_I2C      | \
 151                                  CFG_POST_MEMORY   | \
 152                                  CFG_POST_RTC      | \
 153                                  CFG_POST_SPR      | \
 154                                  CFG_POST_UART)
 155
 156 #define CFG_POST_CACHE_ADDR     0x7fff0000 /* free virtual address      */
 157 #define CONFIG_LOGBUFFER
 158 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 159
 160 /*-----------------------------------------------------------------------
 161  * I2C
 162  *----------------------------------------------------------------------*/
 163 #define CONFIG_HARD_I2C         1               /* I2C with hardware support    */
 164 #undef  CONFIG_SOFT_I2C                         /* I2C bit-banged               */
 165 #define CFG_I2C_SPEED           100000          /* I2C speed and slave address  */
 166 #define CFG_I2C_SLAVE           0x7F
 167
 168 #define CFG_I2C_EEPROM_ADDR     0x53    /* EEPROM AT24C128              */
 169 #define CFG_I2C_EEPROM_ADDR_LEN 2       /* Bytes of address             */
 170 #define CFG_EEPROM_PAGE_WRITE_BITS 6    /* The Atmel AT24C128 has       */
 171                                         /* 64 byte page write mode using*/
 172                                         /* last 6 bits of the address   */
 173 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  10   /* and takes up to 10 msec */
 174 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 175
 176 #define CONFIG_RTC_PCF8563      1               /* enable Philips PCF8563 RTC   */
 177 #define CFG_I2C_RTC_ADDR        0x51            /* Philips PCF8563 RTC address  */
 178 #define CFG_I2C_KEYBD_ADDR      0x56            /* PIC LWE keyboard             */
 179
 180 #define CONFIG_POST_KEY_MAGIC   "3C+3E" /* press F3 + F5 keys to force POST */
 181 #if 0
 182 #define CONFIG_AUTOBOOT_KEYED           /* Enable "password" protection */
 183 #define CONFIG_AUTOBOOT_PROMPT  "\nEnter password - autoboot in %d sec...\n"
 184 #define CONFIG_AUTOBOOT_DELAY_STR       "  "    /* "password"   */
 185 #endif
 186
 187 #define CONFIG_PREBOOT          "setenv bootdelay 15"
 188
 189 #undef  CONFIG_BOOTARGS
 190
 191 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 192         "hostname=lwmon5\0"                                             \
 193         "netdev=eth0\0"                                                 \
 194         "unlock=yes\0"                                                  \
 195         "logversion=2\0"                                                \
 196         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 197                 "nfsroot=${serverip}:${rootpath}\0"                     \
 198         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 199         "addip=setenv bootargs ${bootargs} "                            \
 200                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 201                 ":${hostname}:${netdev}:off panic=1\0"                  \
 202         "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
 203         "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
 204         "flash_nfs=run nfsargs addip addtty addmisc;"                   \
 205                 "bootm ${kernel_addr}\0"                                \
 206         "flash_self=run ramargs addip addtty addmisc;"                  \
 207                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 208         "net_nfs=tftp 200000 ${bootfile};"                              \
 209                 "run nfsargs addip addtty addmisc;bootm\0"              \
 210         "rootpath=/opt/eldk/ppc_4xxFP\0"                                \
 211         "bootfile=/tftpboot/lwmon5/uImage\0"                            \
 212         "kernel_addr=FC000000\0"                                        \
 213         "ramdisk_addr=FC180000\0"                                       \
 214         "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0"           \
 215         "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;"   \
 216                 "cp.b 200000 FFF80000 80000\0"                          \
 217         "upd=run load;run update\0"                                     \
 218         "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;"       \
 219                 "autoscr 200000\0"                                      \
 220         ""
 221 #define CONFIG_BOOTCOMMAND      "run flash_self"
 222
 223 #if 0
 224 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
 225 #else
 226 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 227 #endif
 228
 229 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 230 #define CFG_LOADS_BAUD_CHANGE   1       /* allow baudrate change        */
 231
 232 #define CONFIG_IBM_EMAC4_V4     1
 233 #define CONFIG_MII              1       /* MII PHY management           */
 234 #define CONFIG_PHY_ADDR         3       /* PHY address, See schematics  */
 235
 236 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 237 #define CONFIG_PHY_RESET_DELAY  300
 238
 239 #define CONFIG_HAS_ETH0
 240 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 241
 242 #define CONFIG_NET_MULTI        1
 243 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 244 #define CONFIG_PHY1_ADDR        1
 245
 246 /* USB */
 247 #ifdef CONFIG_440EPX
 248 #define CONFIG_USB_OHCI
 249 #define CONFIG_USB_STORAGE
 250
 251 /* Comment this out to enable USB 1.1 device */
 252 #define USB_2_0_DEVICE
 253
 254 #endif /* CONFIG_440EPX */
 255
 256 /* Partitions */
 257 #define CONFIG_MAC_PARTITION
 258 #define CONFIG_DOS_PARTITION
 259 #define CONFIG_ISO_PARTITION
 260
 261 /*
 262  * BOOTP options
 263  */
 264 #define CONFIG_BOOTP_BOOTFILESIZE
 265 #define CONFIG_BOOTP_BOOTPATH
 266 #define CONFIG_BOOTP_GATEWAY
 267 #define CONFIG_BOOTP_HOSTNAME
 268
 269 /*
 270  * Command line configuration.
 271  */
 272 #include <config_cmd_default.h>
 273
 274 #define CONFIG_CMD_ASKENV
 275 #define CONFIG_CMD_DATE
 276 #define CONFIG_CMD_DHCP
 277 #define CONFIG_CMD_DIAG
 278 #define CONFIG_CMD_EEPROM
 279 #define CONFIG_CMD_ELF
 280 #define CONFIG_CMD_FAT
 281 #define CONFIG_CMD_I2C
 282 #define CONFIG_CMD_IRQ
 283 #define CONFIG_CMD_LOG
 284 #define CONFIG_CMD_MII
 285 #define CONFIG_CMD_NET
 286 #define CONFIG_CMD_NFS
 287 #define CONFIG_CMD_PCI
 288 #define CONFIG_CMD_PING
 289 #define CONFIG_CMD_REGINFO
 290 #define CONFIG_CMD_SDRAM
 291
 292 #ifdef CONFIG_440EPX
 293 #define CONFIG_CMD_USB
 294 #endif
 295
 296 /*-----------------------------------------------------------------------
 297  * Miscellaneous configurable options
 298  *----------------------------------------------------------------------*/
 299 #define CONFIG_SUPPORT_VFAT
 300
 301 #define CFG_LONGHELP                    /* undef to save memory         */
 302 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 303 #if defined(CONFIG_CMD_KGDB)
 304 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 305 #else
 306 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 307 #endif
 308 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 309 #define CFG_MAXARGS             16      /* max number of command args   */
 310 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 311
 312 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 313 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 314
 315 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 316 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 317
 318 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 319
 320 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 321 #define CONFIG_LOOPW            1       /* enable loopw command         */
 322 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 323 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 324 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 325
 326 /*-----------------------------------------------------------------------
 327  * PCI stuff
 328  *----------------------------------------------------------------------*/
 329 /* General PCI */
 330 #define CONFIG_PCI                      /* include pci support          */
 331 #undef CONFIG_PCI_PNP                   /* do (not) pci plug-and-play   */
 332 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 333 #define CFG_PCI_TARGBASE        0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/
 334
 335 /* Board-specific PCI */
 336 #define CFG_PCI_TARGET_INIT
 337 #define CFG_PCI_MASTER_INIT
 338
 339 #define CFG_PCI_SUBSYS_VENDORID 0x10e8  /* AMCC                         */
 340 #define CFG_PCI_SUBSYS_ID       0xcafe  /* Whatever                     */
 341
 342 #if 0
 343 /*
 344  * ToDo: Watchdog is not test fully, so exclude it for now
 345  */
 346 #define CONFIG_HW_WATCHDOG      1       /* Use external HW-Watchdog     */
 347 #endif
 348
 349 /*
 350  * For booting Linux, the board info and command line data
 351  * have to be in the first 8 MB of memory, since this is
 352  * the maximum mapped by the Linux kernel during initialization.
 353  */
 354 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 355
 356 /*-----------------------------------------------------------------------
 357  * External Bus Controller (EBC) Setup
 358  *----------------------------------------------------------------------*/
 359 #define CFG_FLASH               CFG_FLASH_BASE
 360
 361 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 362 #define CFG_EBC_PB0AP           0x03050200
 363 #define CFG_EBC_PB0CR           (CFG_FLASH | 0xfc000)
 364
 365 /* Memory Bank 1 (Lime) initialization                                          */
 366 #define CFG_EBC_PB1AP           0x01004380
 367 #define CFG_EBC_PB1CR           (CFG_LIME_BASE_0 | 0xdc000)
 368
 369 /* Memory Bank 2 (FPGA) initialization                                          */
 370 #define CFG_EBC_PB2AP           0x01004400
 371 #define CFG_EBC_PB2CR           (CFG_FPGA_BASE_0 | 0x1c000)
 372
 373 /* Memory Bank 3 (FPGA2) initialization                                         */
 374 #define CFG_EBC_PB3AP           0x01004400
 375 #define CFG_EBC_PB3CR           (CFG_FPGA_BASE_1 | 0x1c000)
 376
 377 #define CFG_EBC_CFG             0xb8400000
 378
 379 /*-----------------------------------------------------------------------
 380  * Graphics (Fujitsu Lime)
 381  *----------------------------------------------------------------------*/
 382 /* SDRAM Clock frequency adjustment register */
 383 #define CFG_LIME_SDRAM_CLOCK    0xC1FC0038
 384 /* Lime Clock frequency is to set 100MHz */
 385 #define CFG_LIME_CLOCK_100MHZ   0x00000
 386 #if 0
 387 /* Lime Clock frequency for 133MHz */
 388 #define CFG_LIME_CLOCK_133MHZ   0x10000
 389 #endif
 390
 391 /* SDRAM Parameter register */
 392 #define CFG_LIME_MMR            0xC1FCFFFC
 393 /* SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
 394    and pixel flare on display when 133MHz was configured. According to
 395    SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed Grade */
 396 #ifdef CFG_LIME_CLOCK_133MHZ
 397 #define CFG_LIME_MMR_VALUE      0x414FB7F3
 398 #else
 399 #define CFG_LIME_MMR_VALUE      0x414FB7F2
 400 #endif
 401
 402 /*-----------------------------------------------------------------------
 403  * GPIO Setup
 404  *----------------------------------------------------------------------*/
 405 #define CFG_GPIO_PHY1_RST       12
 406 #define CFG_GPIO_FLASH_WP       14
 407 #define CFG_GPIO_PHY0_RST       22
 408 #define CFG_GPIO_EEPROM_EXT_WP  55
 409 #define CFG_GPIO_EEPROM_INT_WP  57
 410 #define CFG_GPIO_LIME_S         59
 411 #define CFG_GPIO_LIME_RST       60
 412 #define CFG_GPIO_WATCHDOG       63
 413
 414 /*-----------------------------------------------------------------------
 415  * PPC440 GPIO Configuration
 416  */
 417 #define CFG_4xx_GPIO_TABLE { /*   Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 418 {                                                                                       \
 419 /* GPIO Core 0 */                                                                       \
 420 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7)     DMA_REQ(2)      */      \
 421 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6)     DMA_ACK(2)      */      \
 422 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5)     DMA_EOT/TC(2)   */      \
 423 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4)     DMA_REQ(3)      */      \
 424 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3)     DMA_ACK(3)      */      \
 425 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2)     DMA_EOT/TC(3)   */      \
 426 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1)                     */      \
 427 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2)                     */      \
 428 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3)                     */      \
 429 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4)                     */      \
 430 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5)                    */      \
 431 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR                    */      \
 432 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12                                */      \
 433 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13                                */      \
 434 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14                                */      \
 435 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15                                */      \
 436 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4)                      */      \
 437 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5)                      */      \
 438 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6)                      */      \
 439 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7)                      */      \
 440 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0                     */      \
 441 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1                     */      \
 442 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22                                */      \
 443 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0                          */      \
 444 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2)                      */      \
 445 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3)                      */      \
 446 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26                                */      \
 447 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ    USB2D_RXERROR   */      \
 448 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28                USB2D_TXVALID   */      \
 449 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA   USB2D_PAD_SUSPNDM */    \
 450 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK    USB2D_XCVRSELECT*/      \
 451 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/      \
 452 },                                                                                      \
 453 {                                                                                       \
 454 /* GPIO Core 1 */                                                                       \
 455 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0  EBC_DATA(2)     */      \
 456 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1  EBC_DATA(3)     */      \
 457 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N    UART1_DSR_CTS_N UART2_SOUT*/ \
 458 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
 459 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0)   UART3_SIN*/ \
 460 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N    EBC_DATA(1)     UART3_SOUT*/ \
 461 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N    UART1_SOUT      */      \
 462 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N     UART1_SIN       */      \
 463 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0)                     */      \
 464 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1)                     */      \
 465 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2)                     */      \
 466 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3)                     */      \
 467 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4)     DMA_ACK(1)      */      \
 468 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6)     DMA_EOT/TC(1)   */      \
 469 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7)     DMA_REQ(0)      */      \
 470 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8)     DMA_ACK(0)      */      \
 471 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9)     DMA_EOT/TC(0)   */      \
 472 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49  Unselect via TraceSelect Bit  */      \
 473 {GPIO1_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO50  Unselect via TraceSelect Bit  */      \
 474 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51  Unselect via TraceSelect Bit  */      \
 475 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52  Unselect via TraceSelect Bit  */      \
 476 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53  Unselect via TraceSelect Bit  */      \
 477 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54  Unselect via TraceSelect Bit  */      \
 478 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55  Unselect via TraceSelect Bit  */      \
 479 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56  Unselect via TraceSelect Bit  */      \
 480 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57  Unselect via TraceSelect Bit  */      \
 481 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58  Unselect via TraceSelect Bit  */      \
 482 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59  Unselect via TraceSelect Bit  */      \
 483 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60  Unselect via TraceSelect Bit  */      \
 484 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61  Unselect via TraceSelect Bit  */      \
 485 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62  Unselect via TraceSelect Bit  */      \
 486 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63  Unselect via TraceSelect Bit  */      \
 487 }                                                                                       \
 488 }
 489
 490 /*
 491  * Internal Definitions
 492  *
 493  * Boot Flags
 494  */
 495 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 496 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 497
 498 #if defined(CONFIG_CMD_KGDB)
 499 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 500 #define CONFIG_KGDB_SER_INDEX   2           /* which serial port to use */
 501 #endif
 502 #endif  /* __CONFIG_H */