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Rename TEXT_BASE into CONFIG_SYS_TEXT_BASE
[thirdparty/u-boot.git] / include / configs / lwmon5.h
1 /*
2 * (C) Copyright 2007-2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 /*
22 * lwmon5.h - configuration for lwmon5 board
23 */
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28 * Liebherr extra version info
29 */
30 #define CONFIG_IDENT_STRING " - v2.0"
31
32 /*
33 * High Level Configuration Options
34 */
35 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
36 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
37 #define CONFIG_440 1 /* ... PPC440 family */
38 #define CONFIG_4xx 1 /* ... PPC4xx family */
39 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
40
41 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
42 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
43 #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
44 #define CONFIG_MISC_INIT_R /* Call misc_init_r */
45 #define CONFIG_BOARD_RESET /* Call board_reset */
46
47 /*
48 * Base addresses -- Note these are effective addresses where the
49 * actual resources get mapped (not physical addresses)
50 */
51 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
52 #define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
53 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
54
55 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
56 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
57 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
58 #define CONFIG_SYS_LIME_BASE_0 0xc0000000
59 #define CONFIG_SYS_LIME_BASE_1 0xc1000000
60 #define CONFIG_SYS_LIME_BASE_2 0xc2000000
61 #define CONFIG_SYS_LIME_BASE_3 0xc3000000
62 #define CONFIG_SYS_FPGA_BASE_0 0xc4000000
63 #define CONFIG_SYS_FPGA_BASE_1 0xc4200000
64 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
65 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
66 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
67 #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
68 #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
69 #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
70
71 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
72 #define CONFIG_SYS_USB_DEVICE 0xe0000000
73 #define CONFIG_SYS_USB_HOST 0xe0000400
74
75 /*
76 * Initial RAM & stack pointer
77 *
78 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
79 * the POST_WORD from OCM to a 440EPx register that preserves it's
80 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
81 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
82 */
83 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
84 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
85 #define CONFIG_SYS_INIT_RAM_END (4 << 10)
86 #define CONFIG_SYS_GBL_DATA_SIZE 256 /* num bytes initial data*/
87 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - \
88 CONFIG_SYS_GBL_DATA_SIZE)
89 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
90 /* unused GPT0 COMP reg */
91 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
92 #define CONFIG_SYS_OCM_SIZE (16 << 10)
93 /* 440EPx errata CHIP 11: don't use last 4kbytes */
94 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
95
96 /* Additional registers for watchdog timer post test */
97 #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
98 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
99 #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
100 #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
101 #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
102 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
103 #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
104 #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
105 #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
106 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
107
108 /*
109 * Serial Port
110 */
111 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
112 #define CONFIG_SYS_NS16550
113 #define CONFIG_SYS_NS16550_SERIAL
114 #define CONFIG_SYS_NS16550_REG_SIZE 1
115 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
116 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
117 #define CONFIG_BAUDRATE 115200
118 #define CONFIG_SERIAL_MULTI
119
120 #define CONFIG_SYS_BAUDRATE_TABLE \
121 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
122
123 /*
124 * Environment
125 */
126 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
127
128 /*
129 * FLASH related
130 */
131 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
132 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
133
134 #define CONFIG_SYS_FLASH0 0xFC000000
135 #define CONFIG_SYS_FLASH1 0xF8000000
136 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
137
138 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
139 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
140
141 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
142 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
143
144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
145 #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
146
147 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
148 #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
149
150 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
151 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
152 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
153
154 /* Address and size of Redundant Environment Sector */
155 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
156 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
157
158 /*
159 * DDR SDRAM
160 */
161 #define CONFIG_SYS_MBYTES_SDRAM 256
162 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
163 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
164 #define CONFIG_DDR_ECC /* enable ECC */
165
166 /* POST support */
167 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
168 CONFIG_SYS_POST_CPU | \
169 CONFIG_SYS_POST_ECC | \
170 CONFIG_SYS_POST_ETHER | \
171 CONFIG_SYS_POST_FPU | \
172 CONFIG_SYS_POST_I2C | \
173 CONFIG_SYS_POST_MEMORY | \
174 CONFIG_SYS_POST_OCM | \
175 CONFIG_SYS_POST_RTC | \
176 CONFIG_SYS_POST_SPR | \
177 CONFIG_SYS_POST_UART | \
178 CONFIG_SYS_POST_SYSMON | \
179 CONFIG_SYS_POST_WATCHDOG | \
180 CONFIG_SYS_POST_DSP | \
181 CONFIG_SYS_POST_BSPEC1 | \
182 CONFIG_SYS_POST_BSPEC2 | \
183 CONFIG_SYS_POST_BSPEC3 | \
184 CONFIG_SYS_POST_BSPEC4 | \
185 CONFIG_SYS_POST_BSPEC5)
186
187 /* Define here the base-addresses of the UARTs to test in POST */
188 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
189 CONFIG_SYS_NS16550_COM2 }
190
191 #define CONFIG_POST_WATCHDOG { \
192 "Watchdog timer test", \
193 "watchdog", \
194 "This test checks the watchdog timer.", \
195 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
196 &lwmon5_watchdog_post_test, \
197 NULL, \
198 NULL, \
199 CONFIG_SYS_POST_WATCHDOG \
200 }
201
202 #define CONFIG_POST_BSPEC1 { \
203 "dsPIC init test", \
204 "dspic_init", \
205 "This test returns result of dsPIC READY test run earlier.", \
206 POST_RAM | POST_ALWAYS, \
207 &dspic_init_post_test, \
208 NULL, \
209 NULL, \
210 CONFIG_SYS_POST_BSPEC1 \
211 }
212
213 #define CONFIG_POST_BSPEC2 { \
214 "dsPIC test", \
215 "dspic", \
216 "This test gets result of dsPIC POST and dsPIC version.", \
217 POST_RAM | POST_ALWAYS, \
218 &dspic_post_test, \
219 NULL, \
220 NULL, \
221 CONFIG_SYS_POST_BSPEC2 \
222 }
223
224 #define CONFIG_POST_BSPEC3 { \
225 "FPGA test", \
226 "fpga", \
227 "This test checks FPGA registers and memory.", \
228 POST_RAM | POST_ALWAYS | POST_MANUAL, \
229 &fpga_post_test, \
230 NULL, \
231 NULL, \
232 CONFIG_SYS_POST_BSPEC3 \
233 }
234
235 #define CONFIG_POST_BSPEC4 { \
236 "GDC test", \
237 "gdc", \
238 "This test checks GDC registers and memory.", \
239 POST_RAM | POST_ALWAYS | POST_MANUAL,\
240 &gdc_post_test, \
241 NULL, \
242 NULL, \
243 CONFIG_SYS_POST_BSPEC4 \
244 }
245
246 #define CONFIG_POST_BSPEC5 { \
247 "SYSMON1 test", \
248 "sysmon1", \
249 "This test checks GPIO_62_EPX pin indicating power failure.", \
250 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
251 &sysmon1_post_test, \
252 NULL, \
253 NULL, \
254 CONFIG_SYS_POST_BSPEC5 \
255 }
256
257 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
258 #define CONFIG_LOGBUFFER
259 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
260 #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
261 #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
262 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
263
264 /*
265 * I2C
266 */
267 #define CONFIG_HARD_I2C /* I2C with hardware support */
268 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
269 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
270 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
271 #define CONFIG_SYS_I2C_SLAVE 0x7F
272
273 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
274 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
275 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
276 #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
277 #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
278 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
279 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
280
281 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
282 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
283 /* 64 byte page write mode using*/
284 /* last 6 bits of the address */
285 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
286 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
287
288 #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
289 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
290 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
291 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
292
293 #define I2C_ADDR_LIST { \
294 CONFIG_SYS_I2C_RTC_ADDR, \
295 CONFIG_SYS_I2C_EEPROM_CPU_ADDR, \
296 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
297 CONFIG_SYS_I2C_DSPIC_ADDR, \
298 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
299 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR, \
300 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
301
302 /*
303 * Pass open firmware flat tree
304 */
305 #define CONFIG_OF_LIBFDT
306 #define CONFIG_OF_BOARD_SETUP
307 /* Update size in "reg" property of NOR FLASH device tree nodes */
308 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
309
310 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
311
312 #define CONFIG_PREBOOT "setenv bootdelay 15"
313
314 #undef CONFIG_BOOTARGS
315
316 #define CONFIG_EXTRA_ENV_SETTINGS \
317 "hostname=lwmon5\0" \
318 "netdev=eth0\0" \
319 "unlock=yes\0" \
320 "logversion=2\0" \
321 "nfsargs=setenv bootargs root=/dev/nfs rw " \
322 "nfsroot=${serverip}:${rootpath}\0" \
323 "ramargs=setenv bootargs root=/dev/ram rw\0" \
324 "addip=setenv bootargs ${bootargs} " \
325 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
326 ":${hostname}:${netdev}:off panic=1\0" \
327 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
328 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
329 "flash_nfs=run nfsargs addip addtty addmisc;" \
330 "bootm ${kernel_addr}\0" \
331 "flash_self=run ramargs addip addtty addmisc;" \
332 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
333 "net_nfs=tftp 200000 ${bootfile};" \
334 "run nfsargs addip addtty addmisc;bootm\0" \
335 "rootpath=/opt/eldk/ppc_4xxFP\0" \
336 "bootfile=/tftpboot/lwmon5/uImage\0" \
337 "kernel_addr=FC000000\0" \
338 "ramdisk_addr=FC180000\0" \
339 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
340 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
341 "cp.b 200000 FFF80000 80000\0" \
342 "upd=run load update\0" \
343 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
344 "autoscr 200000\0" \
345 ""
346 #define CONFIG_BOOTCOMMAND "run flash_self"
347
348 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
349
350 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
351 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
352
353 #define CONFIG_PPC4xx_EMAC
354 #define CONFIG_IBM_EMAC4_V4 1
355 #define CONFIG_MII 1 /* MII PHY management */
356 #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
357
358 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
359 #define CONFIG_PHY_RESET_DELAY 300
360
361 #define CONFIG_HAS_ETH0
362 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
363
364 #define CONFIG_NET_MULTI 1
365 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
366 #define CONFIG_PHY1_ADDR 1
367
368 /* Video console */
369 #define CONFIG_VIDEO
370 #define CONFIG_VIDEO_MB862xx
371 #define CONFIG_VIDEO_MB862xx_ACCEL
372 #define CONFIG_CFB_CONSOLE
373 #define CONFIG_VIDEO_LOGO
374 #define CONFIG_CONSOLE_EXTRA_INFO
375 #define VIDEO_FB_16BPP_PIXEL_SWAP
376 #define VIDEO_FB_16BPP_WORD_SWAP
377
378 #define CONFIG_VGA_AS_SINGLE_DEVICE
379 #define CONFIG_VIDEO_SW_CURSOR
380 #define CONFIG_SPLASH_SCREEN
381
382 /* USB */
383 #ifdef CONFIG_440EPX
384 #define CONFIG_USB_OHCI
385 #define CONFIG_USB_STORAGE
386
387 /* Comment this out to enable USB 1.1 device */
388 #define USB_2_0_DEVICE
389
390 #endif /* CONFIG_440EPX */
391
392 /* Partitions */
393 #define CONFIG_MAC_PARTITION
394 #define CONFIG_DOS_PARTITION
395 #define CONFIG_ISO_PARTITION
396
397 /*
398 * BOOTP options
399 */
400 #define CONFIG_BOOTP_BOOTFILESIZE
401 #define CONFIG_BOOTP_BOOTPATH
402 #define CONFIG_BOOTP_GATEWAY
403 #define CONFIG_BOOTP_HOSTNAME
404
405 /*
406 * Command line configuration.
407 */
408 #include <config_cmd_default.h>
409
410 #define CONFIG_CMD_ASKENV
411 #define CONFIG_CMD_DATE
412 #define CONFIG_CMD_DHCP
413 #define CONFIG_CMD_DIAG
414 #define CONFIG_CMD_EEPROM
415 #define CONFIG_CMD_ELF
416 #define CONFIG_CMD_FAT
417 #define CONFIG_CMD_I2C
418 #define CONFIG_CMD_IRQ
419 #define CONFIG_CMD_LOG
420 #define CONFIG_CMD_MII
421 #define CONFIG_CMD_NET
422 #define CONFIG_CMD_NFS
423 #define CONFIG_CMD_PCI
424 #define CONFIG_CMD_PING
425 #define CONFIG_CMD_REGINFO
426 #define CONFIG_CMD_SDRAM
427
428 #ifdef CONFIG_VIDEO
429 #define CONFIG_CMD_BMP
430 #endif
431
432 #ifdef CONFIG_440EPX
433 #define CONFIG_CMD_USB
434 #endif
435
436 /*
437 * Miscellaneous configurable options
438 */
439 #define CONFIG_SUPPORT_VFAT
440
441 #define CONFIG_SYS_LONGHELP /* undef to save memory */
442 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
443
444 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
445 #ifdef CONFIG_SYS_HUSH_PARSER
446 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
447 #endif
448
449 #if defined(CONFIG_CMD_KGDB)
450 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
451 #else
452 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
453 #endif
454 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
455 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
456 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
457
458 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
459 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
460
461 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
462 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
463
464 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
465
466 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
467 #define CONFIG_LOOPW 1 /* enable loopw command */
468 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
469 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
470
471 /*
472 * PCI stuff
473 */
474 /* General PCI */
475 #define CONFIG_PCI /* include pci support */
476 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
477 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
478 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
479
480 /* Board-specific PCI */
481 #define CONFIG_SYS_PCI_TARGET_INIT
482 #define CONFIG_SYS_PCI_MASTER_INIT
483
484 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
485 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
486
487 #ifndef DEBUG
488 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
489 #endif
490 #define CONFIG_WD_PERIOD 40000 /* in usec */
491 #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
492
493 /*
494 * For booting Linux, the board info and command line data
495 * have to be in the first 16 MB of memory, since this is
496 * the maximum mapped by the 40x Linux kernel during initialization.
497 */
498 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
499 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
500
501 /*
502 * External Bus Controller (EBC) Setup
503 */
504 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
505
506 /* Memory Bank 0 (NOR-FLASH) initialization */
507 #define CONFIG_SYS_EBC_PB0AP 0x03000280
508 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
509
510 /* Memory Bank 1 (Lime) initialization */
511 #define CONFIG_SYS_EBC_PB1AP 0x01004380
512 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
513
514 /* Memory Bank 2 (FPGA) initialization */
515 #define CONFIG_SYS_EBC_PB2AP 0x01004400
516 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
517
518 /* Memory Bank 3 (FPGA2) initialization */
519 #define CONFIG_SYS_EBC_PB3AP 0x01004400
520 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
521
522 #define CONFIG_SYS_EBC_CFG 0xb8400000
523
524 /*
525 * Graphics (Fujitsu Lime)
526 */
527 /* SDRAM Clock frequency adjustment register */
528 #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
529 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
530 /* Lime Clock frequency is to set 100MHz */
531 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
532 #else
533 /* Lime Clock frequency for 133MHz */
534 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
535 #endif
536
537 /* SDRAM Parameter register */
538 #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
539 /*
540 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
541 * and pixel flare on display when 133MHz was configured. According to
542 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
543 * Grade
544 */
545 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
546 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
547 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
548 #else
549 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
550 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
551 #endif
552
553 /*
554 * GPIO Setup
555 */
556 #define CONFIG_SYS_GPIO_PHY1_RST 12
557 #define CONFIG_SYS_GPIO_FLASH_WP 14
558 #define CONFIG_SYS_GPIO_PHY0_RST 22
559 #define CONFIG_SYS_GPIO_DSPIC_READY 51
560 #define CONFIG_SYS_GPIO_CAN_ENABLE 53
561 #define CONFIG_SYS_GPIO_LSB_ENABLE 54
562 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
563 #define CONFIG_SYS_GPIO_HIGHSIDE 56
564 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
565 #define CONFIG_SYS_GPIO_BOARD_RESET 58
566 #define CONFIG_SYS_GPIO_LIME_S 59
567 #define CONFIG_SYS_GPIO_LIME_RST 60
568 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
569 #define CONFIG_SYS_GPIO_WATCHDOG 63
570
571 /*
572 * PPC440 GPIO Configuration
573 */
574 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
575 { \
576 /* GPIO Core 0 */ \
577 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
578 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
579 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
580 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
581 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
582 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
583 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
584 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
585 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
586 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
587 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
588 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
589 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
590 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
591 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
592 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
593 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
594 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
595 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
596 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
597 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
598 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
599 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
600 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
601 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
602 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
603 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
604 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
605 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
606 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
607 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
608 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
609 }, \
610 { \
611 /* GPIO Core 1 */ \
612 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
613 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
614 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
615 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
616 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
617 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
618 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
619 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
620 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
621 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
622 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
623 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
624 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
625 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
626 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
627 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
628 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
629 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
630 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
631 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
632 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
633 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
634 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
635 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
636 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
637 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
638 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
639 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
640 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
641 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
642 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
643 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
644 } \
645 }
646
647 /*
648 * Internal Definitions
649 *
650 * Boot Flags
651 */
652 #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
653 #define BOOTFLAG_WARM 0x02 /* Software reboot */
654
655 #if defined(CONFIG_CMD_KGDB)
656 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
657 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
658 #endif
659 #endif /* __CONFIG_H */
"Das U-Boot" Source Tree