]> git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/lwmon5.h
projects / people / ms / u-boot.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
blame | history | raw | HEAD
Merge branch 'master' of git://git.denx.de/u-boot-marvell
[people/ms/u-boot.git] / include / configs / lwmon5.h
1 /*
2 * (C) Copyright 2007-2010
3 * Stefan Roese, DENX Software Engineering, sr@denx.de.
4 *
5 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License as
7 * published by the Free Software Foundation; either version 2 of
8 * the License, or (at your option) any later version.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
18 * MA 02111-1307 USA
19 */
20
21 /*
22 * lwmon5.h - configuration for lwmon5 board
23 */
24 #ifndef __CONFIG_H
25 #define __CONFIG_H
26
27 /*
28 * Liebherr extra version info
29 */
30 #define CONFIG_IDENT_STRING " - v2.0"
31
32 /*
33 * High Level Configuration Options
34 */
35 #define CONFIG_LWMON5 1 /* Board is lwmon5 */
36 #define CONFIG_440EPX 1 /* Specific PPC440EPx */
37 #define CONFIG_440 1 /* ... PPC440 family */
38 #define CONFIG_4xx 1 /* ... PPC4xx family */
39
40 #ifndef CONFIG_SYS_TEXT_BASE
41 #define CONFIG_SYS_TEXT_BASE 0xFFF80000
42 #endif
43
44 #define CONFIG_SYS_CLK_FREQ 33300000 /* external freq to pll */
45
46 #define CONFIG_BOARD_EARLY_INIT_F /* Call board_early_init_f */
47 #define CONFIG_BOARD_EARLY_INIT_R /* Call board_early_init_r */
48 #define CONFIG_BOARD_POSTCLK_INIT /* Call board_postclk_init */
49 #define CONFIG_MISC_INIT_R /* Call misc_init_r */
50 #define CONFIG_BOARD_RESET /* Call board_reset */
51
52 /*
53 * Base addresses -- Note these are effective addresses where the
54 * actual resources get mapped (not physical addresses)
55 */
56 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* Start of U-Boot */
57 #define CONFIG_SYS_MONITOR_LEN (0xFFFFFFFF - CONFIG_SYS_MONITOR_BASE + 1)
58 #define CONFIG_SYS_MALLOC_LEN (1 << 20) /* Reserved for malloc */
59
60 #define CONFIG_SYS_BOOT_BASE_ADDR 0xf0000000
61 #define CONFIG_SYS_SDRAM_BASE 0x00000000 /* _must_ be 0 */
62 #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH */
63 #define CONFIG_SYS_LIME_BASE_0 0xc0000000
64 #define CONFIG_SYS_LIME_BASE_1 0xc1000000
65 #define CONFIG_SYS_LIME_BASE_2 0xc2000000
66 #define CONFIG_SYS_LIME_BASE_3 0xc3000000
67 #define CONFIG_SYS_FPGA_BASE_0 0xc4000000
68 #define CONFIG_SYS_FPGA_BASE_1 0xc4200000
69 #define CONFIG_SYS_OCM_BASE 0xe0010000 /* ocm */
70 #define CONFIG_SYS_PCI_BASE 0xe0000000 /* Internal PCI regs */
71 #define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
72 #define CONFIG_SYS_PCI_MEMBASE1 (CONFIG_SYS_PCI_MEMBASE + 0x10000000)
73 #define CONFIG_SYS_PCI_MEMBASE2 (CONFIG_SYS_PCI_MEMBASE1 + 0x10000000)
74 #define CONFIG_SYS_PCI_MEMBASE3 (CONFIG_SYS_PCI_MEMBASE2 + 0x10000000)
75
76 #define CONFIG_SYS_USB2D0_BASE 0xe0000100
77 #define CONFIG_SYS_USB_DEVICE 0xe0000000
78 #define CONFIG_SYS_USB_HOST 0xe0000400
79
80 /*
81 * Initial RAM & stack pointer
82 *
83 * On LWMON5 we use D-cache as init-ram and stack pointer. We also move
84 * the POST_WORD from OCM to a 440EPx register that preserves it's
85 * content during reset (GPT0_COMP6). This way we reserve the OCM (16k)
86 * for logbuffer only. (GPT0_COMP1-COMP5 are reserved for logbuffer header.)
87 */
88 #define CONFIG_SYS_INIT_RAM_DCACHE 1 /* d-cache as init ram */
89 #define CONFIG_SYS_INIT_RAM_ADDR 0x70000000 /* DCache */
90 #define CONFIG_SYS_INIT_RAM_SIZE (4 << 10)
91 #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
92 GENERATED_GBL_DATA_SIZE)
93 #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
94 /* unused GPT0 COMP reg */
95 #define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP6)
96 #define CONFIG_SYS_OCM_SIZE (16 << 10)
97 /* 440EPx errata CHIP 11: don't use last 4kbytes */
98 #define CONFIG_SYS_MEM_TOP_HIDE (4 << 10)
99
100 /* Additional registers for watchdog timer post test */
101 #define CONFIG_SYS_WATCHDOG_TIME_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK2)
102 #define CONFIG_SYS_WATCHDOG_FLAGS_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_MASK1)
103 #define CONFIG_SYS_DSPIC_TEST_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
104 #define CONFIG_SYS_OCM_STATUS_ADDR CONFIG_SYS_WATCHDOG_FLAGS_ADDR
105 #define CONFIG_SYS_WATCHDOG_MAGIC 0x12480000
106 #define CONFIG_SYS_WATCHDOG_MAGIC_MASK 0xFFFF0000
107 #define CONFIG_SYS_DSPIC_TEST_MASK 0x00000001
108 #define CONFIG_SYS_OCM_STATUS_OK 0x00009A00
109 #define CONFIG_SYS_OCM_STATUS_FAIL 0x0000A300
110 #define CONFIG_SYS_OCM_STATUS_MASK 0x0000FF00
111
112 /*
113 * Serial Port
114 */
115 #define CONFIG_CONS_INDEX 2 /* Use UART1 */
116 #define CONFIG_SYS_NS16550
117 #define CONFIG_SYS_NS16550_SERIAL
118 #define CONFIG_SYS_NS16550_REG_SIZE 1
119 #define CONFIG_SYS_NS16550_CLK get_serial_clock()
120 #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external clock provided */
121 #define CONFIG_BAUDRATE 115200
122 #define CONFIG_SERIAL_MULTI
123
124 #define CONFIG_SYS_BAUDRATE_TABLE \
125 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
126
127 /*
128 * Environment
129 */
130 #define CONFIG_ENV_IS_IN_FLASH /* use FLASH for environment vars */
131
132 /*
133 * FLASH related
134 */
135 #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
136 #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
137
138 #define CONFIG_SYS_FLASH0 0xFC000000
139 #define CONFIG_SYS_FLASH1 0xF8000000
140 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 }
141
142 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2 /* max number of memory banks */
143 #define CONFIG_SYS_MAX_FLASH_SECT 512 /* max number of sectors on one chip */
144
145 #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
146 #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
147
148 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
149 #define CONFIG_SYS_FLASH_PROTECTION /* use hardware flash protection */
150
151 #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
152 #define CONFIG_SYS_FLASH_QUIET_TEST /* don't warn upon unknown flash */
153
154 #define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
155 #define CONFIG_ENV_ADDR ((-CONFIG_SYS_MONITOR_LEN) - CONFIG_ENV_SECT_SIZE)
156 #define CONFIG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */
157
158 /* Address and size of Redundant Environment Sector */
159 #define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
160 #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
161
162 /*
163 * DDR SDRAM
164 */
165 #define CONFIG_SYS_MBYTES_SDRAM 256
166 #define CONFIG_SYS_DDR_CACHED_ADDR 0x40000000 /* setup 2nd TLB cached here */
167 #define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */
168 #define CONFIG_DDR_ECC /* enable ECC */
169
170 /* POST support */
171 #define CONFIG_POST (CONFIG_SYS_POST_CACHE | \
172 CONFIG_SYS_POST_CPU | \
173 CONFIG_SYS_POST_ECC | \
174 CONFIG_SYS_POST_ETHER | \
175 CONFIG_SYS_POST_FPU | \
176 CONFIG_SYS_POST_I2C | \
177 CONFIG_SYS_POST_MEMORY | \
178 CONFIG_SYS_POST_OCM | \
179 CONFIG_SYS_POST_RTC | \
180 CONFIG_SYS_POST_SPR | \
181 CONFIG_SYS_POST_UART | \
182 CONFIG_SYS_POST_SYSMON | \
183 CONFIG_SYS_POST_WATCHDOG | \
184 CONFIG_SYS_POST_DSP | \
185 CONFIG_SYS_POST_BSPEC1 | \
186 CONFIG_SYS_POST_BSPEC2 | \
187 CONFIG_SYS_POST_BSPEC3 | \
188 CONFIG_SYS_POST_BSPEC4 | \
189 CONFIG_SYS_POST_BSPEC5)
190
191 /* Define here the base-addresses of the UARTs to test in POST */
192 #define CONFIG_SYS_POST_UART_TABLE { CONFIG_SYS_NS16550_COM1, \
193 CONFIG_SYS_NS16550_COM2 }
194
195 #define CONFIG_POST_UART { \
196 "UART test", \
197 "uart", \
198 "This test verifies the UART operation.", \
199 POST_RAM | POST_SLOWTEST | POST_ALWAYS | POST_MANUAL, \
200 &uart_post_test, \
201 NULL, \
202 NULL, \
203 CONFIG_SYS_POST_UART \
204 }
205
206 #define CONFIG_POST_WATCHDOG { \
207 "Watchdog timer test", \
208 "watchdog", \
209 "This test checks the watchdog timer.", \
210 POST_RAM | POST_POWERON | POST_SLOWTEST | POST_MANUAL | POST_REBOOT, \
211 &lwmon5_watchdog_post_test, \
212 NULL, \
213 NULL, \
214 CONFIG_SYS_POST_WATCHDOG \
215 }
216
217 #define CONFIG_POST_BSPEC1 { \
218 "dsPIC init test", \
219 "dspic_init", \
220 "This test returns result of dsPIC READY test run earlier.", \
221 POST_RAM | POST_ALWAYS, \
222 &dspic_init_post_test, \
223 NULL, \
224 NULL, \
225 CONFIG_SYS_POST_BSPEC1 \
226 }
227
228 #define CONFIG_POST_BSPEC2 { \
229 "dsPIC test", \
230 "dspic", \
231 "This test gets result of dsPIC POST and dsPIC version.", \
232 POST_RAM | POST_ALWAYS, \
233 &dspic_post_test, \
234 NULL, \
235 NULL, \
236 CONFIG_SYS_POST_BSPEC2 \
237 }
238
239 #define CONFIG_POST_BSPEC3 { \
240 "FPGA test", \
241 "fpga", \
242 "This test checks FPGA registers and memory.", \
243 POST_RAM | POST_ALWAYS | POST_MANUAL, \
244 &fpga_post_test, \
245 NULL, \
246 NULL, \
247 CONFIG_SYS_POST_BSPEC3 \
248 }
249
250 #define CONFIG_POST_BSPEC4 { \
251 "GDC test", \
252 "gdc", \
253 "This test checks GDC registers and memory.", \
254 POST_RAM | POST_ALWAYS | POST_MANUAL,\
255 &gdc_post_test, \
256 NULL, \
257 NULL, \
258 CONFIG_SYS_POST_BSPEC4 \
259 }
260
261 #define CONFIG_POST_BSPEC5 { \
262 "SYSMON1 test", \
263 "sysmon1", \
264 "This test checks GPIO_62_EPX pin indicating power failure.", \
265 POST_RAM | POST_MANUAL | POST_NORMAL | POST_SLOWTEST, \
266 &sysmon1_post_test, \
267 NULL, \
268 NULL, \
269 CONFIG_SYS_POST_BSPEC5 \
270 }
271
272 #define CONFIG_SYS_POST_CACHE_ADDR 0x7fff0000 /* free virtual address */
273 #define CONFIG_LOGBUFFER
274 /* Reserve GPT0_COMP1-COMP5 for logbuffer header */
275 #define CONFIG_ALT_LH_ADDR (CONFIG_SYS_PERIPHERAL_BASE + GPT0_COMP1)
276 #define CONFIG_ALT_LB_ADDR (CONFIG_SYS_OCM_BASE)
277 #define CONFIG_SYS_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
278
279 /*
280 * I2C
281 */
282 #define CONFIG_HARD_I2C /* I2C with hardware support */
283 #undef CONFIG_SOFT_I2C /* I2C bit-banged */
284 #define CONFIG_PPC4XX_I2C /* use PPC4xx driver */
285 #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */
286 #define CONFIG_SYS_I2C_SLAVE 0x7F
287
288 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* RTC */
289 #define CONFIG_SYS_I2C_EEPROM_CPU_ADDR 0x52 /* EEPROM (CPU Modul) */
290 #define CONFIG_SYS_I2C_EEPROM_MB_ADDR 0x53 /* EEPROM AT24C128 (MainBoard) */
291 #define CONFIG_SYS_I2C_DSPIC_ADDR 0x54 /* dsPIC */
292 #define CONFIG_SYS_I2C_DSPIC_2_ADDR 0x55 /* dsPIC */
293 #define CONFIG_SYS_I2C_DSPIC_KEYB_ADDR 0x56 /* dsPIC */
294 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* dsPIC */
295
296 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */
297 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel AT24C128 has */
298 /* 64 byte page write mode using*/
299 /* last 6 bits of the address */
300 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
301 #define CONFIG_SYS_EEPROM_PAGE_WRITE_ENABLE
302
303 #define CONFIG_RTC_PCF8563 /* enable Philips PCF8563 RTC */
304 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Philips PCF8563 RTC address */
305 #define CONFIG_SYS_I2C_KEYBD_ADDR 0x56 /* PIC LWE keyboard */
306 #define CONFIG_SYS_I2C_DSPIC_IO_ADDR 0x57 /* PIC I/O addr */
307
308 #define CONFIG_SYS_POST_I2C_ADDRS {CONFIG_SYS_I2C_RTC_ADDR, \
309 CONFIG_SYS_I2C_EEPROM_CPU_ADDR,\
310 CONFIG_SYS_I2C_EEPROM_MB_ADDR, \
311 CONFIG_SYS_I2C_DSPIC_ADDR, \
312 CONFIG_SYS_I2C_DSPIC_2_ADDR, \
313 CONFIG_SYS_I2C_DSPIC_KEYB_ADDR,\
314 CONFIG_SYS_I2C_DSPIC_IO_ADDR }
315
316 /*
317 * Pass open firmware flat tree
318 */
319 #define CONFIG_OF_LIBFDT
320 #define CONFIG_OF_BOARD_SETUP
321 /* Update size in "reg" property of NOR FLASH device tree nodes */
322 #define CONFIG_FDT_FIXUP_NOR_FLASH_SIZE
323
324 #define CONFIG_POST_KEY_MAGIC "3C+3E" /* press F3 + F5 keys to force POST */
325
326 #define CONFIG_PREBOOT "setenv bootdelay 15"
327
328 #undef CONFIG_BOOTARGS
329
330 #define CONFIG_EXTRA_ENV_SETTINGS \
331 "hostname=lwmon5\0" \
332 "netdev=eth0\0" \
333 "unlock=yes\0" \
334 "logversion=2\0" \
335 "nfsargs=setenv bootargs root=/dev/nfs rw " \
336 "nfsroot=${serverip}:${rootpath}\0" \
337 "ramargs=setenv bootargs root=/dev/ram rw\0" \
338 "addip=setenv bootargs ${bootargs} " \
339 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
340 ":${hostname}:${netdev}:off panic=1\0" \
341 "addtty=setenv bootargs ${bootargs} console=ttyS1,${baudrate}\0"\
342 "addmisc=setenv bootargs ${bootargs} rtc-pcf8563.probe=0,0x51\0"\
343 "flash_nfs=run nfsargs addip addtty addmisc;" \
344 "bootm ${kernel_addr}\0" \
345 "flash_self=run ramargs addip addtty addmisc;" \
346 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
347 "net_nfs=tftp 200000 ${bootfile};" \
348 "run nfsargs addip addtty addmisc;bootm\0" \
349 "rootpath=/opt/eldk/ppc_4xxFP\0" \
350 "bootfile=/tftpboot/lwmon5/uImage\0" \
351 "kernel_addr=FC000000\0" \
352 "ramdisk_addr=FC180000\0" \
353 "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \
354 "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \
355 "cp.b 200000 FFF80000 80000\0" \
356 "upd=run load update\0" \
357 "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \
358 "autoscr 200000\0" \
359 ""
360 #define CONFIG_BOOTCOMMAND "run flash_self"
361
362 #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
363
364 #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
365 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
366
367 #define CONFIG_PPC4xx_EMAC
368 #define CONFIG_IBM_EMAC4_V4 1
369 #define CONFIG_MII 1 /* MII PHY management */
370 #define CONFIG_PHY_ADDR 3 /* PHY address, See schematics */
371
372 #define CONFIG_PHY_RESET 1 /* reset phy upon startup */
373 #define CONFIG_PHY_RESET_DELAY 300
374
375 #define CONFIG_HAS_ETH0
376 #define CONFIG_SYS_RX_ETH_BUFFER 32 /* Number of ethernet rx buffers & descriptors */
377
378 #define CONFIG_NET_MULTI 1
379 #define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */
380 #define CONFIG_PHY1_ADDR 1
381
382 /* Video console */
383 #define CONFIG_VIDEO
384 #define CONFIG_VIDEO_MB862xx
385 #define CONFIG_VIDEO_MB862xx_ACCEL
386 #define CONFIG_CFB_CONSOLE
387 #define CONFIG_VIDEO_LOGO
388 #define CONFIG_CONSOLE_EXTRA_INFO
389 #define VIDEO_FB_16BPP_PIXEL_SWAP
390 #define VIDEO_FB_16BPP_WORD_SWAP
391
392 #define CONFIG_VGA_AS_SINGLE_DEVICE
393 #define CONFIG_VIDEO_SW_CURSOR
394 #define CONFIG_SPLASH_SCREEN
395
396 /* USB */
397 #ifdef CONFIG_440EPX
398 #define CONFIG_USB_OHCI
399 #define CONFIG_USB_STORAGE
400
401 /* Comment this out to enable USB 1.1 device */
402 #define USB_2_0_DEVICE
403
404 #endif /* CONFIG_440EPX */
405
406 /* Partitions */
407 #define CONFIG_MAC_PARTITION
408 #define CONFIG_DOS_PARTITION
409 #define CONFIG_ISO_PARTITION
410
411 /*
412 * BOOTP options
413 */
414 #define CONFIG_BOOTP_BOOTFILESIZE
415 #define CONFIG_BOOTP_BOOTPATH
416 #define CONFIG_BOOTP_GATEWAY
417 #define CONFIG_BOOTP_HOSTNAME
418
419 /*
420 * Command line configuration.
421 */
422 #include <config_cmd_default.h>
423
424 #define CONFIG_CMD_ASKENV
425 #define CONFIG_CMD_DATE
426 #define CONFIG_CMD_DHCP
427 #define CONFIG_CMD_DIAG
428 #define CONFIG_CMD_EEPROM
429 #define CONFIG_CMD_ELF
430 #define CONFIG_CMD_FAT
431 #define CONFIG_CMD_I2C
432 #define CONFIG_CMD_IRQ
433 #define CONFIG_CMD_LOG
434 #define CONFIG_CMD_MII
435 #define CONFIG_CMD_NET
436 #define CONFIG_CMD_NFS
437 #define CONFIG_CMD_PCI
438 #define CONFIG_CMD_PING
439 #define CONFIG_CMD_REGINFO
440 #define CONFIG_CMD_SDRAM
441
442 #ifdef CONFIG_VIDEO
443 #define CONFIG_CMD_BMP
444 #endif
445
446 #ifdef CONFIG_440EPX
447 #define CONFIG_CMD_USB
448 #endif
449
450 /*
451 * Miscellaneous configurable options
452 */
453 #define CONFIG_SUPPORT_VFAT
454
455 #define CONFIG_SYS_LONGHELP /* undef to save memory */
456 #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
457
458 #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
459 #ifdef CONFIG_SYS_HUSH_PARSER
460 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
461 #endif
462
463 #if defined(CONFIG_CMD_KGDB)
464 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
465 #else
466 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
467 #endif
468 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
469 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
470 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
471
472 #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
473 #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
474
475 #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
476 #define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */
477
478 #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
479
480 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
481 #define CONFIG_LOOPW 1 /* enable loopw command */
482 #define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */
483 #define CONFIG_VERSION_VARIABLE 1 /* include version env variable */
484
485 /*
486 * PCI stuff
487 */
488 /* General PCI */
489 #define CONFIG_PCI /* include pci support */
490 #undef CONFIG_PCI_PNP /* do (not) pci plug-and-play */
491 #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
492 #define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE*/
493
494 /* Board-specific PCI */
495 #define CONFIG_SYS_PCI_TARGET_INIT
496 #define CONFIG_SYS_PCI_MASTER_INIT
497
498 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
499 #define CONFIG_SYS_PCI_SUBSYS_ID 0xcafe /* Whatever */
500
501 #ifndef DEBUG
502 #define CONFIG_HW_WATCHDOG 1 /* Use external HW-Watchdog */
503 #endif
504 #define CONFIG_WD_PERIOD 40000 /* in usec */
505 #define CONFIG_WD_MAX_RATE 66600 /* in ticks */
506
507 /*
508 * For booting Linux, the board info and command line data
509 * have to be in the first 16 MB of memory, since this is
510 * the maximum mapped by the 40x Linux kernel during initialization.
511 */
512 #define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux */
513 #define CONFIG_SYS_BOOTM_LEN (16 << 20) /* Increase max gunzip size */
514
515 /*
516 * External Bus Controller (EBC) Setup
517 */
518 #define CONFIG_SYS_FLASH CONFIG_SYS_FLASH_BASE
519
520 /* Memory Bank 0 (NOR-FLASH) initialization */
521 #define CONFIG_SYS_EBC_PB0AP 0x03000280
522 #define CONFIG_SYS_EBC_PB0CR (CONFIG_SYS_FLASH | 0xfc000)
523
524 /* Memory Bank 1 (Lime) initialization */
525 #define CONFIG_SYS_EBC_PB1AP 0x01004380
526 #define CONFIG_SYS_EBC_PB1CR (CONFIG_SYS_LIME_BASE_0 | 0xbc000)
527
528 /* Memory Bank 2 (FPGA) initialization */
529 #define CONFIG_SYS_EBC_PB2AP 0x01004400
530 #define CONFIG_SYS_EBC_PB2CR (CONFIG_SYS_FPGA_BASE_0 | 0x1c000)
531
532 /* Memory Bank 3 (FPGA2) initialization */
533 #define CONFIG_SYS_EBC_PB3AP 0x01004400
534 #define CONFIG_SYS_EBC_PB3CR (CONFIG_SYS_FPGA_BASE_1 | 0x1c000)
535
536 #define CONFIG_SYS_EBC_CFG 0xb8400000
537
538 /*
539 * Graphics (Fujitsu Lime)
540 */
541 /* SDRAM Clock frequency adjustment register */
542 #define CONFIG_SYS_LIME_SDRAM_CLOCK 0xC1FC0038
543 #if 1 /* 133MHz is not tested enough, use 100MHz for now */
544 /* Lime Clock frequency is to set 100MHz */
545 #define CONFIG_SYS_LIME_CLOCK_100MHZ 0x00000
546 #else
547 /* Lime Clock frequency for 133MHz */
548 #define CONFIG_SYS_LIME_CLOCK_133MHZ 0x10000
549 #endif
550
551 /* SDRAM Parameter register */
552 #define CONFIG_SYS_LIME_MMR 0xC1FCFFFC
553 /*
554 * SDRAM parameter value; was 0x414FB7F2, caused several vertical bars
555 * and pixel flare on display when 133MHz was configured. According to
556 * SDRAM chip datasheet CAS Latency is 3 for 133MHz and -75 Speed
557 * Grade
558 */
559 #ifdef CONFIG_SYS_LIME_CLOCK_133MHZ
560 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F3
561 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_133MHZ
562 #else
563 #define CONFIG_SYS_MB862xx_MMR 0x414FB7F2
564 #define CONFIG_SYS_MB862xx_CCF CONFIG_SYS_LIME_CLOCK_100MHZ
565 #endif
566
567 /*
568 * GPIO Setup
569 */
570 #define CONFIG_SYS_GPIO_PHY1_RST 12
571 #define CONFIG_SYS_GPIO_FLASH_WP 14
572 #define CONFIG_SYS_GPIO_PHY0_RST 22
573 #define CONFIG_SYS_GPIO_DSPIC_READY 51
574 #define CONFIG_SYS_GPIO_CAN_ENABLE 53
575 #define CONFIG_SYS_GPIO_LSB_ENABLE 54
576 #define CONFIG_SYS_GPIO_EEPROM_EXT_WP 55
577 #define CONFIG_SYS_GPIO_HIGHSIDE 56
578 #define CONFIG_SYS_GPIO_EEPROM_INT_WP 57
579 #define CONFIG_SYS_GPIO_BOARD_RESET 58
580 #define CONFIG_SYS_GPIO_LIME_S 59
581 #define CONFIG_SYS_GPIO_LIME_RST 60
582 #define CONFIG_SYS_GPIO_SYSMON_STATUS 62
583 #define CONFIG_SYS_GPIO_WATCHDOG 63
584
585 /*
586 * PPC440 GPIO Configuration
587 */
588 #define CONFIG_SYS_4xx_GPIO_TABLE { /* Out GPIO Alternate1 Alternate2 Alternate3 */ \
589 { \
590 /* GPIO Core 0 */ \
591 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO0 EBC_ADDR(7) DMA_REQ(2) */ \
592 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO1 EBC_ADDR(6) DMA_ACK(2) */ \
593 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO2 EBC_ADDR(5) DMA_EOT/TC(2) */ \
594 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO3 EBC_ADDR(4) DMA_REQ(3) */ \
595 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO4 EBC_ADDR(3) DMA_ACK(3) */ \
596 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO5 EBC_ADDR(2) DMA_EOT/TC(3) */ \
597 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO6 EBC_CS_N(1) */ \
598 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO7 EBC_CS_N(2) */ \
599 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 EBC_CS_N(3) */ \
600 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 EBC_CS_N(4) */ \
601 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 EBC_CS_N(5) */ \
602 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 EBC_BUS_ERR */ \
603 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO12 */ \
604 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO13 */ \
605 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO14 */ \
606 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO15 */ \
607 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 GMCTxD(4) */ \
608 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 GMCTxD(5) */ \
609 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 GMCTxD(6) */ \
610 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 GMCTxD(7) */ \
611 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO20 RejectPkt0 */ \
612 {GPIO0_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO21 RejectPkt1 */ \
613 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO22 */ \
614 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO23 SCPD0 */ \
615 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO24 GMCTxD(2) */ \
616 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO25 GMCTxD(3) */ \
617 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO26 */ \
618 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EXT_EBC_REQ USB2D_RXERROR */ \
619 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO28 USB2D_TXVALID */ \
620 {GPIO0_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO29 EBC_EXT_HDLA USB2D_PAD_SUSPNDM */ \
621 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO30 EBC_EXT_ACK USB2D_XCVRSELECT*/ \
622 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO31 EBC_EXR_BUSREQ USB2D_TERMSELECT*/ \
623 }, \
624 { \
625 /* GPIO Core 1 */ \
626 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO32 USB2D_OPMODE0 EBC_DATA(2) */ \
627 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO33 USB2D_OPMODE1 EBC_DATA(3) */ \
628 {GPIO1_BASE, GPIO_OUT, GPIO_ALT3, GPIO_OUT_0}, /* GPIO34 UART0_DCD_N UART1_DSR_CTS_N UART2_SOUT*/ \
629 {GPIO1_BASE, GPIO_IN , GPIO_ALT3, GPIO_OUT_0}, /* GPIO35 UART0_8PIN_DSR_N UART1_RTS_DTR_N UART2_SIN*/ \
630 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO36 UART0_8PIN_CTS_N EBC_DATA(0) UART3_SIN*/ \
631 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO37 UART0_RTS_N EBC_DATA(1) UART3_SOUT*/ \
632 {GPIO1_BASE, GPIO_OUT, GPIO_ALT2, GPIO_OUT_0}, /* GPIO38 UART0_DTR_N UART1_SOUT */ \
633 {GPIO1_BASE, GPIO_IN , GPIO_ALT2, GPIO_OUT_0}, /* GPIO39 UART0_RI_N UART1_SIN */ \
634 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO40 UIC_IRQ(0) */ \
635 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO41 UIC_IRQ(1) */ \
636 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO42 UIC_IRQ(2) */ \
637 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO43 UIC_IRQ(3) */ \
638 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO44 UIC_IRQ(4) DMA_ACK(1) */ \
639 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO45 UIC_IRQ(6) DMA_EOT/TC(1) */ \
640 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO46 UIC_IRQ(7) DMA_REQ(0) */ \
641 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO47 UIC_IRQ(8) DMA_ACK(0) */ \
642 {GPIO1_BASE, GPIO_IN , GPIO_ALT1, GPIO_OUT_0}, /* GPIO48 UIC_IRQ(9) DMA_EOT/TC(0) */ \
643 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO49 Unselect via TraceSelect Bit */ \
644 {GPIO1_BASE, GPIO_IN, GPIO_SEL , GPIO_OUT_0}, /* GPIO50 Unselect via TraceSelect Bit */ \
645 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO51 Unselect via TraceSelect Bit */ \
646 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO52 Unselect via TraceSelect Bit */ \
647 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO53 Unselect via TraceSelect Bit */ \
648 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO54 Unselect via TraceSelect Bit */ \
649 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO55 Unselect via TraceSelect Bit */ \
650 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO56 Unselect via TraceSelect Bit */ \
651 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_1}, /* GPIO57 Unselect via TraceSelect Bit */ \
652 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO58 Unselect via TraceSelect Bit */ \
653 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO59 Unselect via TraceSelect Bit */ \
654 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO60 Unselect via TraceSelect Bit */ \
655 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO61 Unselect via TraceSelect Bit */ \
656 {GPIO1_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO62 Unselect via TraceSelect Bit */ \
657 {GPIO1_BASE, GPIO_OUT, GPIO_SEL , GPIO_OUT_0}, /* GPIO63 Unselect via TraceSelect Bit */ \
658 } \
659 }
660
661 #if defined(CONFIG_CMD_KGDB)
662 #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
663 #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
664 #endif
665 #endif /* __CONFIG_H */
"Das U-Boot" Source Tree