include/configs/m501sk.h

   1 /*
   2  * Based on Modifications by Alan Lu / Artila and
   3  * Rick Bronson <rick@efn.org>
   4  *
   5  * Configuration settings for the Artila M-501 starter kit,
   6  * with V02 processor card.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_AT91_LEGACY
  31
  32 /* ARM asynchronous clock */
  33 /* from 18.432 MHz crystal (18432000 / 4 * 39) */
  34 #define AT91C_MAIN_CLOCK        179712000
  35 /* Perip clock (AT91C_MASTER_CLOCK / 3) */
  36 #define AT91C_MASTER_CLOCK      59904000
  37 #define AT91_SLOW_CLOCK 32768 /* slow clock */
  38
  39 #define CONFIG_AT91RM9200       1       /* It's an Atmel AT91RM9200 SoC */
  40 #define CONFIG_AT91RM9200DK     1 /* on an AT91RM9200DK Board    */
  41 #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
  42 #define CONFIG_CMDLINE_TAG      1 /* enable passing of ATAGs    */
  43 #define CONFIG_SETUP_MEMORY_TAGS        1
  44 #define CONFIG_INITRD_TAG               1
  45
  46 #define CONFIG_MENUPROMPT               "."
  47 /*
  48  * LowLevel Init
  49  */
  50 #define CONFIG_SYS_USE_MAIN_OSCILLATOR          1
  51 /* flash */
  52 #define CONFIG_SYS_EBI_CFGR_VAL 0x00000000
  53 #define CONFIG_SYS_SMC_CSR0_VAL 0x00003284 /* 16bit, 2 TDF, 4 WS */
  54
  55 /* clocks */
  56 #define CONFIG_SYS_PLLAR_VAL    0x20263E04 /* 179.712000 MHz for PCK */
  57 #define CONFIG_SYS_PLLBR_VAL    0x10483E0E /* 48.054857 MHz (divider by 2 for USB) */
  58 /* PCK/3 = MCK Master Clock = 59.904000MHz from PLLA */
  59 #define CONFIG_SYS_MCKR_VAL     0x00000202
  60
  61 /* sdram */
  62 #define CONFIG_SYS_PIOC_ASR_VAL 0xFFFF0000 /* Configure PIOC as peripheral (D16/D31) */
  63 #define CONFIG_SYS_PIOC_BSR_VAL 0x00000000
  64 #define CONFIG_SYS_PIOC_PDR_VAL 0xFFFF0000
  65 #define CONFIG_SYS_EBI_CSA_VAL  0x00000002 /* CS1=CONFIG_SYS_SDRAM */
  66 #define CONFIG_SYS_SDRC_CR_VAL  0x2188c155 /* set up the CONFIG_SYS_SDRAM */
  67 #define CONFIG_SYS_SDRAM        0x20000000 /* address of the CONFIG_SYS_SDRAM */
  68 #define CONFIG_SYS_SDRAM1       0x20000080 /* address of the CONFIG_SYS_SDRAM */
  69 #define CONFIG_SYS_SDRAM_VAL    0x00000000 /* value written to CONFIG_SYS_SDRAM */
  70 #define CONFIG_SYS_SDRC_MR_VAL  0x00000002 /* Precharge All */
  71 #define CONFIG_SYS_SDRC_MR_VAL1 0x00000004 /* refresh */
  72 #define CONFIG_SYS_SDRC_MR_VAL2 0x00000003 /* Load Mode Register */
  73 #define CONFIG_SYS_SDRC_MR_VAL3 0x00000000 /* Normal Mode */
  74 #define CONFIG_SYS_SDRC_TR_VAL  0x000002E0 /* Write refresh rate */
  75
  76 /*
  77  * Size of malloc() pool
  78  */
  79 #define CONFIG_SYS_MALLOC_LEN           (CONFIG_ENV_SIZE + 128*1024)
  80
  81 #define CONFIG_BAUDRATE                 115200
  82
  83 /* Hardcode so no __divsi3 : AT91C_MASTER_CLOCK / baudrate / 16 */
  84 #define CONFIG_SYS_AT91C_BRGR_DIVISOR   33
  85
  86 /*
  87  * Hardware drivers
  88  */
  89 #define CONFIG_SYS_FLASH_CFI            1
  90 #define CONFIG_FLASH_CFI_DRIVER 1
  91 #define CONFIG_ENV_SECT_SIZE    0x20000
  92 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
  93 #define CONFIG_SYS_FLASH_PROTECTION     /*for Intel P30 Flash*/
  94 #define CONFIG_HARD_I2C
  95 #define CONFIG_SYS_I2C_SPEED            100
  96 #define CONFIG_SYS_I2C_SLAVE            0
  97 #define CONFIG_SYS_CONSOLE_INFO_QUIET
  98 #undef CONFIG_ENV_IS_IN_EEPROM
  99 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x50
 100 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 101 #define CONFIG_SYS_EEPROM_AT24C16
 102 #define CONFIG_SYS_I2C_RTC_ADDR         0x32
 103 #undef CONFIG_RTC_DS1338
 104 #define CONFIG_RTC_RS5C372A
 105 #undef CONFIG_POST
 106 #define CONFIG_M501SK
 107 #define CONFIG_CMC_PU2
 108
 109 /* define one of these to choose the DBGU, USART0  or USART1 as console */
 110 #define CONFIG_AT91RM9200_USART
 111 #define CONFIG_DBGU
 112 #undef CONFIG_USART0
 113 #undef CONFIG_USART1
 114
 115 #undef CONFIG_HWFLOW            /* don't include RTS/CTS flow control support */
 116 #undef CONFIG_MODEM_SUPPORT     /* disable modem initialization stuff */
 117
 118 #define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200 " \
 119                         "initrd=0x20800000,8192000 ramdisk_size=15360 " \
 120                         "root=/dev/ram0 rw mtdparts=phys_mapped_flash:" \
 121                         "128k(loader)ro,128k(reserved)ro,1408k(linux)"  \
 122                         "ro,2560k(ramdisk)ro,-(userdisk)"
 123 #define CONFIG_BOOTCOMMAND      "bootm 10040000 101a0000"
 124 #define CONFIG_BOOTDELAY        1
 125 #define CONFIG_BAUDRATE 115200
 126 #define CONFIG_IPADDR           192.168.1.100
 127 #define CONFIG_SERVERIP 192.168.1.1
 128 #define CONFIG_GATEWAYIP        192.168.1.254
 129 #define CONFIG_NETMASK          255.255.255.0
 130 #define CONFIG_BOOTFILE uImage
 131 #define CONFIG_ETHADDR          00:13:48:aa:bb:cc
 132 #define CONFIG_ENV_OVERWRITE    1
 133 #define BOARD_LATE_INIT
 134
 135 #define CONFIG_EXTRA_ENV_SETTINGS \
 136                 "unlock=yes\0"
 137
 138 #define CONFIG_CMD_JFFS2
 139 #undef CONFIG_CMD_EEPROM
 140 #define CONFIG_CMD_NET
 141 #define CONFIG_CMD_RUN
 142 #define CONFIG_CMD_DHCP
 143 #define CONFIG_CMD_MEMORY
 144 #define CONFIG_CMD_PING
 145 #define CONFIG_CMD_SDRAM
 146 #define CONFIG_CMD_DIAG
 147 #define CONFIG_CMD_I2C
 148 #define CONFIG_CMD_DATE
 149 #define CONFIG_CMD_POST
 150 #define CONFIG_CMD_MISC
 151 #define CONFIG_CMD_LOADS
 152 #define CONFIG_CMD_IMI
 153 #define CONFIG_CMD_NFS
 154 #define CONFIG_CMD_FLASH
 155 #define CONFIG_CMD_SAVEENV
 156
 157 #define CONFIG_SYS_HUSH_PARSER
 158 #define CONFIG_AUTO_COMPLETE
 159 #define CONFIG_SYS_PROMPT_HUSH_PS2          ">>"
 160
 161 #define CONFIG_SYS_MAX_NAND_DEVICE      0 /* Max number of NAND devices */
 162
 163 #define CONFIG_NR_DRAM_BANKS    1
 164 #define PHYS_SDRAM              0x20000000
 165 #define PHYS_SDRAM_SIZE 0x2000000 /* 32 megs */
 166
 167 #define CONFIG_SYS_MEMTEST_START        0x21000000 /* PHYS_SDRAM */
 168 /* CONFIG_SYS_MEMTEST_START + PHYS_SDRAM_SIZE - 262144 */
 169 #define CONFIG_SYS_MEMTEST_END  0x00100000
 170
 171 #define CONFIG_NET_MULTI                1
 172 #ifdef CONFIG_NET_MULTI
 173 #define CONFIG_DRIVER_AT91EMAC          1
 174 #define CONFIG_SYS_RX_ETH_BUFFER        8
 175 #else
 176 #define CONFIG_DRIVER_ETHER             1
 177 #endif
 178 #define CONFIG_NET_RETRY_COUNT  20
 179 #define CONFIG_AT91C_USE_RMII
 180
 181 #define PHYS_FLASH_1            0x10000000
 182 #define PHYS_FLASH_SIZE 0x800000 /* 8 megs main flash */
 183 #define CONFIG_SYS_FLASH_BASE           PHYS_FLASH_1
 184 #define CONFIG_SYS_MAX_FLASH_BANKS      1
 185 #define CONFIG_SYS_MAX_FLASH_SECT       256
 186 #define CONFIG_SYS_FLASH_ERASE_TOUT     (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
 187 #define CONFIG_SYS_FLASH_WRITE_TOUT     (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
 188
 189 #ifdef CONFIG_ENV_IS_IN_DATAFLASH
 190 #define CONFIG_ENV_OFFSET               0x20000
 191 #define CONFIG_ENV_ADDR         (CONFIG_SYS_DATAFLASH_LOGIC_ADDR_CS0 + CONFIG_ENV_OFFSET)
 192 #define CONFIG_ENV_SIZE         0x2000
 193 #else
 194 #define CONFIG_ENV_IS_IN_FLASH
 195 #define CONFIG_ENV_ADDR         (PHYS_FLASH_1 + 0x00020000)
 196 #define CONFIG_ENV_SIZE         2048
 197 #endif
 198
 199 #ifdef CONFIG_ENV_IS_IN_EEPROM
 200 #define CONFIG_ENV_OFFSET               1024
 201 #define CONFIG_ENV_SIZE         1024
 202 #endif
 203
 204 #define CONFIG_SYS_LOAD_ADDR            0x21000000 /* default load address */
 205
 206 /* use for protect flash sectors */
 207 #define CONFIG_SYS_BOOT_SIZE            0x6000 /* 24 KBytes */
 208 #define CONFIG_SYS_U_BOOT_BASE  (PHYS_FLASH_1 + 0x10000)
 209 #define CONFIG_SYS_U_BOOT_SIZE  0x10000 /* 64 KBytes */
 210
 211 #define CONFIG_SYS_BAUDRATE_TABLE       { 115200 , 19200, 38400, 57600, 9600 }
 212
 213 #define CONFIG_SYS_PROMPT               "U-Boot> " /* Monitor Command Prompt */
 214 #define CONFIG_SYS_CBSIZE               512 /* Console I/O Buffer Size */
 215 #define CONFIG_SYS_MAXARGS              16 /* max number of command args */
 216 /* Print Buffer Size */
 217 #define CONFIG_SYS_PBSIZE               (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 218
 219 #define CONFIG_SYS_HZ 1000
 220 #define CONFIG_SYS_HZ_CLOCK             AT91C_MASTER_CLOCK/2
 221
 222 #define CONFIG_STACKSIZE        (32*1024) /* regular stack */
 223
 224 #ifdef CONFIG_USE_IRQ
 225 #error CONFIG_USE_IRQ not supported
 226 #endif
 227
 228 #endif