include/configs/makalu.h

   1 /*
   2  * Copyright (c) 2008 Nuovation System Designs, LLC
   3  *   Grant Erickson <gerickson@nuovations.com>
   4  *
   5  * (C) Copyright 2007-2008
   6  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   7  *
   8  * See file CREDITS for list of people who contributed to this
   9  * project.
  10  *
  11  * This program is free software; you can redistribute it and/or
  12  * modify it under the terms of the GNU General Public License as
  13  * published by the Free Software Foundation; either version 2 of
  14  * the License, or (at your option) any later version.
  15  *
  16  * This program is distributed in the hope that it will be useful,
  17  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  * GNU General Public License for more details.
  20  *
  21  * You should have received a copy of the GNU General Public License
  22  * along with this program; if not, write to the Free Software
  23  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24  * MA 02111-1307 USA
  25  */
  26
  27 /************************************************************************
  28  * makalu.h - configuration for AMCC Makalu (405EX)
  29  ***********************************************************************/
  30
  31 #ifndef __CONFIG_H
  32 #define __CONFIG_H
  33
  34 /*-----------------------------------------------------------------------
  35  * High Level Configuration Options
  36  *----------------------------------------------------------------------*/
  37 #define CONFIG_MAKALU           1               /* Board is Makalu      */
  38 #define CONFIG_4xx              1               /* ... PPC4xx family    */
  39 #define CONFIG_405EX            1               /* Specifc 405EX support*/
  40 #define CONFIG_SYS_CLK_FREQ     33330000        /* ext frequency to pll */
  41
  42 #define CONFIG_BOARD_EARLY_INIT_F 1             /* Call board_early_init_f */
  43 #define CONFIG_MISC_INIT_R      1               /* Call misc_init_r     */
  44
  45 /*-----------------------------------------------------------------------
  46  * Base addresses -- Note these are effective addresses where the
  47  * actual resources get mapped (not physical addresses)
  48  *----------------------------------------------------------------------*/
  49 #define CFG_SDRAM_BASE          0x00000000
  50 #define CFG_FLASH_BASE          0xFC000000
  51 #define CFG_FPGA_BASE           0xF0000000
  52 #define CFG_PERIPHERAL_BASE     0xEF600000      /* internal peripherals*/
  53 #define CFG_MONITOR_LEN         (384 * 1024)    /* Reserve 384 kB for Monitor   */
  54 #define CFG_MALLOC_LEN          (512 * 1024)    /* Reserve 512 kB for malloc()  */
  55 #define CFG_MONITOR_BASE        (TEXT_BASE)
  56
  57 /*-----------------------------------------------------------------------
  58  * Initial RAM & Stack Pointer Configuration Options
  59  *
  60  *   There are traditionally three options for the primordial
  61  *   (i.e. initial) stack usage on the 405-series:
  62  *
  63  *      1) On-chip Memory (OCM) (i.e. SRAM)
  64  *      2) Data cache
  65  *      3) SDRAM
  66  *
  67  *   For the 405EX(r), there is no OCM, so we are left with (2) or (3)
  68  *   the latter of which is less than desireable since it requires
  69  *   setting up the SDRAM and ECC in assembly code.
  70  *
  71  *   To use (2), define 'CFG_INIT_DCACHE_CS' to be an unused chip
  72  *   select on the External Bus Controller (EBC) and then select a
  73  *   value for 'CFG_INIT_RAM_ADDR' outside of the range of valid,
  74  *   physical SDRAM. Otherwise, undefine 'CFG_INIT_DCACHE_CS' and
  75  *   select a value for 'CFG_INIT_RAM_ADDR' within the range of valid,
  76  *   physical SDRAM to use (3).
  77  *-----------------------------------------------------------------------*/
  78
  79 #define CFG_INIT_DCACHE_CS      4
  80
  81 #if defined(CFG_INIT_DCACHE_CS)
  82 #define CFG_INIT_RAM_ADDR       (CFG_SDRAM_BASE + ( 1 << 30))   /*  1 GiB */
  83 #else
  84 #define CFG_INIT_RAM_ADDR       (CFG_SDRAM_BASE + (32 << 20))   /* 32 MiB */
  85 #endif /* defined(CFG_INIT_DCACHE_CS) */
  86
  87 #define CFG_INIT_RAM_END        (4 << 10)                       /*  4 KiB */
  88 #define CFG_GBL_DATA_SIZE       256             /* num bytes initial data */
  89 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
  90
  91 /*
  92  * If the data cache is being used for the primordial stack and global
  93  * data area, the POST word must be placed somewhere else. The General
  94  * Purpose Timer (GPT) is unused by u-boot and the kernel and preserves
  95  * its compare and mask register contents across reset, so it is used
  96  * for the POST word.
  97  */
  98
  99 #if defined(CFG_INIT_DCACHE_CS)
 100 # define CFG_INIT_SP_OFFSET     CFG_GBL_DATA_OFFSET
 101 # define CFG_POST_ALT_WORD_ADDR (CFG_PERIPHERAL_BASE + GPT0_COMP6)
 102 #else
 103 # define CFG_INIT_EXTRA_SIZE    16
 104 # define CFG_INIT_SP_OFFSET     (CFG_GBL_DATA_OFFSET - CFG_INIT_EXTRA_SIZE)
 105 # define CFG_POST_WORD_ADDR     (CFG_GBL_DATA_OFFSET - 4)
 106 # define CFG_OCM_DATA_ADDR      CFG_INIT_RAM_ADDR
 107 #endif /* defined(CFG_INIT_DCACHE_CS) */
 108
 109 /*-----------------------------------------------------------------------
 110  * Serial Port
 111  *----------------------------------------------------------------------*/
 112 #undef CFG_EXT_SERIAL_CLOCK                     /* no ext. clk          */
 113 #define CONFIG_BAUDRATE         115200
 114 #define CONFIG_SERIAL_MULTI     1
 115 /* define this if you want console on UART1 */
 116 #undef CONFIG_UART1_CONSOLE
 117
 118 #define CFG_BAUDRATE_TABLE                                              \
 119         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 120
 121 /*-----------------------------------------------------------------------
 122  * Environment
 123  *----------------------------------------------------------------------*/
 124 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 125
 126 /*-----------------------------------------------------------------------
 127  * FLASH related
 128  *----------------------------------------------------------------------*/
 129 #define CFG_FLASH_CFI                   /* The flash is CFI compatible  */
 130 #define CFG_FLASH_CFI_DRIVER            /* Use common CFI driver        */
 131
 132 #define CFG_FLASH_BANKS_LIST    {CFG_FLASH_BASE}
 133 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 134 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 135
 136 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 137 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 138
 139 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 140 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 141
 142 #ifdef CFG_ENV_IS_IN_FLASH
 143 #define CFG_ENV_SECT_SIZE       0x20000 /* size of one complete sector  */
 144 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE-CFG_ENV_SECT_SIZE)
 145 #define CFG_ENV_SIZE            0x4000  /* Total Size of Environment Sector     */
 146
 147 /* Address and size of Redundant Environment Sector     */
 148 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE)
 149 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 150 #endif /* CFG_ENV_IS_IN_FLASH */
 151
 152 /*-----------------------------------------------------------------------
 153  * DDR SDRAM
 154  *----------------------------------------------------------------------*/
 155 #define CFG_MBYTES_SDRAM        (256)           /* 256MB                        */
 156
 157 #define CFG_SDRAM0_MB0CF_BASE   ((  0 << 20) + CFG_SDRAM_BASE)
 158 #define CFG_SDRAM0_MB1CF_BASE   ((128 << 20) + CFG_SDRAM_BASE)
 159
 160 /* DDR1/2 SDRAM Device Control Register Data Values */
 161 #define CFG_SDRAM0_MB0CF        ((CFG_SDRAM0_MB0CF_BASE >> 3)   | \
 162                                  SDRAM_RXBAS_SDSZ_128MB         | \
 163                                  SDRAM_RXBAS_SDAM_MODE2         | \
 164                                  SDRAM_RXBAS_SDBE_ENABLE)
 165 #define CFG_SDRAM0_MB1CF        ((CFG_SDRAM0_MB1CF_BASE >> 3)   | \
 166                                  SDRAM_RXBAS_SDSZ_128MB         | \
 167                                  SDRAM_RXBAS_SDAM_MODE2         | \
 168                                  SDRAM_RXBAS_SDBE_ENABLE)
 169 #define CFG_SDRAM0_MB2CF        SDRAM_RXBAS_SDBE_DISABLE
 170 #define CFG_SDRAM0_MB3CF        SDRAM_RXBAS_SDBE_DISABLE
 171 #define CFG_SDRAM0_MCOPT1       0x04322000
 172 #define CFG_SDRAM0_MCOPT2       0x00000000
 173 #define CFG_SDRAM0_MODT0        0x01800000
 174 #define CFG_SDRAM0_MODT1        0x00000000
 175 #define CFG_SDRAM0_CODT         0x0080f837
 176 #define CFG_SDRAM0_RTR          0x06180000
 177 #define CFG_SDRAM0_INITPLR0     0xa8380000
 178 #define CFG_SDRAM0_INITPLR1     0x81900400
 179 #define CFG_SDRAM0_INITPLR2     0x81020000
 180 #define CFG_SDRAM0_INITPLR3     0x81030000
 181 #define CFG_SDRAM0_INITPLR4     0x81010404
 182 #define CFG_SDRAM0_INITPLR5     0x81000542
 183 #define CFG_SDRAM0_INITPLR6     0x81900400
 184 #define CFG_SDRAM0_INITPLR7     0x8D080000
 185 #define CFG_SDRAM0_INITPLR8     0x8D080000
 186 #define CFG_SDRAM0_INITPLR9     0x8D080000
 187 #define CFG_SDRAM0_INITPLR10    0x8D080000
 188 #define CFG_SDRAM0_INITPLR11    0x81000442
 189 #define CFG_SDRAM0_INITPLR12    0x81010780
 190 #define CFG_SDRAM0_INITPLR13    0x81010400
 191 #define CFG_SDRAM0_INITPLR14    0x00000000
 192 #define CFG_SDRAM0_INITPLR15    0x00000000
 193 #define CFG_SDRAM0_RQDC         0x80000038
 194 #define CFG_SDRAM0_RFDC         0x00000209
 195 #define CFG_SDRAM0_RDCC         0x40000000
 196 #define CFG_SDRAM0_DLCR         0x030000a5
 197 #define CFG_SDRAM0_CLKTR        0x80000000
 198 #define CFG_SDRAM0_WRDTR        0x00000000
 199 #define CFG_SDRAM0_SDTR1        0x80201000
 200 #define CFG_SDRAM0_SDTR2        0x32204232
 201 #define CFG_SDRAM0_SDTR3        0x080b0d1a
 202 #define CFG_SDRAM0_MMODE        0x00000442
 203 #define CFG_SDRAM0_MEMODE       0x00000404
 204
 205 /*-----------------------------------------------------------------------
 206  * I2C
 207  *----------------------------------------------------------------------*/
 208 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
 209 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
 210 #define CFG_I2C_SLAVE           0x7F
 211
 212 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS  6       /* 24C02 requires 5ms delay */
 213 #define CFG_I2C_EEPROM_ADDR     0x52    /* I2C boot EEPROM (24C02BN)    */
 214 #define CFG_I2C_EEPROM_ADDR_LEN 1       /* Bytes of address             */
 215
 216 /* Standard DTT sensor configuration */
 217 #define CONFIG_DTT_DS1775       1
 218 #define CONFIG_DTT_SENSORS      { 0 }
 219 #define CFG_I2C_DTT_ADDR        0x48
 220
 221 /* RTC configuration */
 222 #define CONFIG_RTC_X1205        1
 223 #define CFG_I2C_RTC_ADDR        0x6f
 224
 225 /*-----------------------------------------------------------------------
 226  * Ethernet
 227  *----------------------------------------------------------------------*/
 228 #define CONFIG_M88E1111_PHY     1
 229 #define CONFIG_IBM_EMAC4_V4     1
 230 #define CONFIG_MII              1       /* MII PHY management           */
 231 #define CONFIG_PHY_ADDR         6       /* PHY address, See schematics  */
 232
 233 #define CONFIG_PHY_RESET        1       /* reset phy upon startup       */
 234 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 235
 236 #define CONFIG_HAS_ETH0         1
 237
 238 #define CONFIG_NET_MULTI        1
 239 #define CONFIG_HAS_ETH1         1       /* add support for "eth1addr"   */
 240 #define CONFIG_PHY1_ADDR        0
 241
 242 #define CFG_RX_ETH_BUFFER       32      /* Number of ethernet rx buffers & descriptors */
 243
 244 #define CONFIG_PREBOOT  "echo;" \
 245         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 246         "echo"
 247
 248 #undef  CONFIG_BOOTARGS
 249
 250 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 251         "logversion=2\0"                                                \
 252         "netdev=eth0\0"                                                 \
 253         "hostname=makalu\0"                                             \
 254         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 255                 "nfsroot=${serverip}:${rootpath}\0"                     \
 256         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 257         "addip=setenv bootargs ${bootargs} "                            \
 258                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 259                 ":${hostname}:${netdev}:off panic=1\0"                  \
 260         "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\
 261         "addmisc=setenv bootargs ${bootargs} rtc-x1205.probe=0,0x6f\0"  \
 262         "flash_self_old=run ramargs addip addtty addmisc;"              \
 263                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 264         "flash_self=run ramargs addip addtty addmisc;"                  \
 265                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 266         "flash_nfs_old=run nfsargs addip addtty addmisc;"               \
 267                 "bootm ${kernel_addr}\0"                                \
 268         "flash_nfs=run nfsargs addip addtty addmisc;"                   \
 269                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 270         "net_nfs_old=tftp ${kernel_addr_r} ${bootfile};"                \
 271                 "run nfsargs addip addtty addmisc;"                     \
 272                 "bootm ${kernel_addr_r}\0"                              \
 273         "net_nfs=tftp ${kernel_addr_r} ${bootfile}; "                   \
 274                 "tftp ${fdt_addr_r} ${fdt_file}; "                      \
 275                 "run nfsargs addip addtty addmisc;"                     \
 276                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 277         "rootpath=/opt/eldk/ppc_4xx\0"                                  \
 278         "bootfile=makalu/uImage\0"                                      \
 279         "fdt_file=makalu/makalu.dtb\0"                                  \
 280         "kernel_addr_r=400000\0"                                        \
 281         "fdt_addr_r=800000\0"                                           \
 282         "kernel_addr=fc000000\0"                                        \
 283         "fdt_addr=fc1e0000\0"                                           \
 284         "ramdisk_addr=fc200000\0"                                       \
 285         "initrd_high=30000000\0"                                        \
 286         "load=tftp 200000 makalu/u-boot.bin\0"                          \
 287         "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;"   \
 288                 "cp.b ${fileaddr} fffa0000 ${filesize};"                \
 289                 "setenv filesize;saveenv\0"                             \
 290         "upd=run load update\0"                                         \
 291         "pciconfighost=1\0"                                             \
 292         "pcie_mode=RP:RP\0"                                             \
 293         ""
 294 #define CONFIG_BOOTCOMMAND      "run flash_self"
 295
 296 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
 297
 298 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
 299 #define CFG_LOADS_BAUD_CHANGE           /* allow baudrate change        */
 300
 301 /*
 302  * BOOTP options
 303  */
 304 #define CONFIG_BOOTP_BOOTFILESIZE
 305 #define CONFIG_BOOTP_BOOTPATH
 306 #define CONFIG_BOOTP_GATEWAY
 307 #define CONFIG_BOOTP_HOSTNAME
 308 #define CONFIG_BOOTP_SUBNETMASK
 309
 310 /*
 311  * Command line configuration.
 312  */
 313 #include <config_cmd_default.h>
 314
 315 #define CONFIG_CMD_ASKENV
 316 #define CONFIG_CMD_DATE
 317 #define CONFIG_CMD_DHCP
 318 #define CONFIG_CMD_DIAG
 319 #define CONFIG_CMD_DTT
 320 #define CONFIG_CMD_EEPROM
 321 #define CONFIG_CMD_ELF
 322 #define CONFIG_CMD_I2C
 323 #define CONFIG_CMD_IRQ
 324 #define CONFIG_CMD_LOG
 325 #define CONFIG_CMD_MII
 326 #define CONFIG_CMD_NET
 327 #define CONFIG_CMD_NFS
 328 #define CONFIG_CMD_PCI
 329 #define CONFIG_CMD_PING
 330 #define CONFIG_CMD_REGINFO
 331 #define CONFIG_CMD_SNTP
 332
 333 /* POST support */
 334 #define CONFIG_POST             (CFG_POST_CACHE         | \
 335                                  CFG_POST_CPU           | \
 336                                  CFG_POST_ETHER         | \
 337                                  CFG_POST_I2C           | \
 338                                  CFG_POST_MEMORY        | \
 339                                  CFG_POST_UART)
 340
 341 /* Define here the base-addresses of the UARTs to test in POST */
 342 #define CFG_POST_UART_TABLE     {UART0_BASE, UART1_BASE}
 343
 344 #define CONFIG_LOGBUFFER
 345 #define CFG_POST_CACHE_ADDR     0x00800000 /* free virtual address      */
 346
 347 #define CFG_CONSOLE_IS_IN_ENV /* Otherwise it catches logbuffer as output */
 348
 349 #undef CONFIG_WATCHDOG                  /* watchdog disabled            */
 350
 351 /*-----------------------------------------------------------------------
 352  * Miscellaneous configurable options
 353  *----------------------------------------------------------------------*/
 354 #define CFG_LONGHELP                    /* undef to save memory         */
 355 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt       */
 356 #if defined(CONFIG_CMD_KGDB)
 357 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size      */
 358 #else
 359 #define CFG_CBSIZE              256     /* Console I/O Buffer Size      */
 360 #endif
 361 #define CFG_PBSIZE              (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 362 #define CFG_MAXARGS             16      /* max number of command args   */
 363 #define CFG_BARGSIZE            CFG_CBSIZE /* Boot Argument Buffer Size */
 364
 365 #define CFG_MEMTEST_START       0x0400000 /* memtest works on           */
 366 #define CFG_MEMTEST_END         0x0C00000 /* 4 ... 12 MB in DRAM        */
 367
 368 #define CFG_LOAD_ADDR           0x100000  /* default load address       */
 369 #define CFG_EXTBDINFO           1       /* To use extended board_into (bd_t) */
 370
 371 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 372
 373 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 374 #define CONFIG_LOOPW            1       /* enable loopw command         */
 375 #define CONFIG_MX_CYCLIC        1       /* enable mdc/mwc commands      */
 376 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* check for keypress on bootdelay==0 */
 377 #define CONFIG_VERSION_VARIABLE 1       /* include version env variable */
 378 #define CFG_CONSOLE_INFO_QUIET  1       /* don't print console @ startup*/
 379
 380 /*-----------------------------------------------------------------------
 381  * PCI stuff
 382  *----------------------------------------------------------------------*/
 383 #define CONFIG_PCI                      /* include pci support          */
 384 #define CONFIG_PCI_PNP          1       /* do pci plug-and-play         */
 385 #define CONFIG_PCI_SCAN_SHOW    1       /* show pci devices on startup  */
 386 #define CONFIG_PCI_CONFIG_HOST_BRIDGE
 387
 388 /*-----------------------------------------------------------------------
 389  * PCIe stuff
 390  *----------------------------------------------------------------------*/
 391 #define CFG_PCIE_MEMBASE        0x90000000      /* mapped PCIe memory   */
 392 #define CFG_PCIE_MEMSIZE        0x08000000      /* 128 Meg, smallest incr per port */
 393
 394 #define CFG_PCIE0_CFGBASE       0xa0000000      /* remote access */
 395 #define CFG_PCIE0_XCFGBASE      0xb0000000      /* local access */
 396 #define CFG_PCIE0_CFGMASK       0xe0000001      /* 512 Meg */
 397
 398 #define CFG_PCIE1_CFGBASE       0xc0000000      /* remote access */
 399 #define CFG_PCIE1_XCFGBASE      0xd0000000      /* local access */
 400 #define CFG_PCIE1_CFGMASK       0xe0000001      /* 512 Meg */
 401
 402 #define CFG_PCIE0_UTLBASE       0xef502000
 403 #define CFG_PCIE1_UTLBASE       0xef503000
 404
 405 /* base address of inbound PCIe window */
 406 #define CFG_PCIE_INBOUND_BASE   0x0000000000000000ULL
 407
 408 /*
 409  * For booting Linux, the board info and command line data
 410  * have to be in the first 8 MB of memory, since this is
 411  * the maximum mapped by the Linux kernel during initialization.
 412  */
 413 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 414
 415 /*-----------------------------------------------------------------------
 416  * External Bus Controller (EBC) Setup
 417  *----------------------------------------------------------------------*/
 418 /* Memory Bank 0 (NOR-FLASH) initialization                                     */
 419 #define CFG_EBC_PB0AP           0x08033700
 420 #define CFG_EBC_PB0CR           (CFG_FLASH_BASE | 0xda000)
 421
 422 /* Memory Bank 2 (CPLD) initialization                                          */
 423 #define CFG_EBC_PB2AP           0x9400C800
 424 #define CFG_EBC_PB2CR           0xF0018000 /*  BAS=0x800,BS=1MB,BU=R/W,BW=8bit  */
 425
 426 #define CFG_EBC_CFG             0x7FC00000 /*  EBC0_CFG */
 427
 428 /*-----------------------------------------------------------------------
 429  * GPIO Setup
 430  *----------------------------------------------------------------------*/
 431 #define CFG_4xx_GPIO_TABLE { /*   Out             GPIO  Alternate1      Alternate2      Alternate3 */ \
 432 {                                                                                       \
 433 /* GPIO Core 0 */                                                                       \
 434 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO0 EBC_DATA_PAR(0)                 */      \
 435 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO1 EBC_DATA_PAR(1)                 */      \
 436 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO2 EBC_DATA_PAR(2)                 */      \
 437 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO3 EBC_DATA_PAR(3)                 */      \
 438 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO4 EBC_DATA(20)    USB2_DATA(4)    */      \
 439 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO5 EBC_DATA(21)    USB2_DATA(5)    */      \
 440 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO6 EBC_DATA(22)    USB2_DATA(6)    */      \
 441 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO7 EBC_DATA(23)    USB2_DATA(7)    */      \
 442 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO8 CS(1)/NFCE(1)   IRQ(7)          */      \
 443 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO9 CS(2)/NFCE(2)   IRQ(8)          */      \
 444 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO10 CS(3)/NFCE(3)  IRQ(9)          */      \
 445 {GPIO0_BASE, GPIO_IN , GPIO_SEL , GPIO_OUT_0}, /* GPIO11 IRQ(6)                         */      \
 446 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO12 EBC_DATA(16)   USB2_DATA(0)    */      \
 447 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO13 EBC_DATA(17)   USB2_DATA(1)    */      \
 448 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO14 EBC_DATA(18)   USB2_DATA(2)    */      \
 449 {GPIO0_BASE, GPIO_BI,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO15 EBC_DATA(19)   USB2_DATA(3)    */      \
 450 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO16 UART0_DCD      UART1_CTS       */      \
 451 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO17 UART0_DSR      UART1_RTS       */      \
 452 {GPIO0_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_0}, /* GPIO18 UART0_CTS                      */      \
 453 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO19 UART0_RTS                      */      \
 454 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO20 UART0_DTR      UART1_TX        */      \
 455 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO21 UART0_RI       UART1_RX        */      \
 456 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO22 EBC_HOLD_REQ   DMA_ACK2        */      \
 457 {GPIO0_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_0}, /* GPIO23 EBC_HOLD_ACK   DMA_REQ2        */      \
 458 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO24 EBC_EXT_REQ    DMA_EOT2        IRQ(4) */ \
 459 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO25 EBC_EXT_ACK    DMA_ACK3        IRQ(3) */ \
 460 {GPIO0_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_0}, /* GPIO26 EBC_ADDR(5)    DMA_EOT0        TS(3) */ \
 461 {GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO27 EBC_BUS_REQ    DMA_EOT3        IRQ(5) */ \
 462 {GPIO0_BASE, GPIO_IN,  GPIO_SEL , GPIO_OUT_0}, /* GPIO28                                */      \
 463 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO29 DMA_EOT1       IRQ(2)          */      \
 464 {GPIO0_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_0}, /* GPIO30 DMA_REQ1       IRQ(1)          */      \
 465 {GPIO0_BASE, GPIO_IN,  GPIO_ALT2, GPIO_OUT_0}, /* GPIO31 DMA_ACK1       IRQ(0)          */      \
 466 }                                                                                               \
 467 }
 468
 469 #define CFG_GPIO_PCIE_RST       23
 470 #define CFG_GPIO_PCIE_CLKREQ    27
 471 #define CFG_GPIO_PCIE_WAKE      28
 472
 473 /*
 474  * Internal Definitions
 475  *
 476  * Boot Flags
 477  */
 478 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 479 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 480
 481 #if defined(CONFIG_CMD_KGDB)
 482 #define CONFIG_KGDB_BAUDRATE    230400  /* speed to run kgdb serial port */
 483 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 484 #endif
 485
 486 /* pass open firmware flat tree */
 487 #define CONFIG_OF_LIBFDT        1
 488 #define CONFIG_OF_BOARD_SETUP   1
 489
 490 #endif  /* __CONFIG_H */