include/configs/manroland/mpc5200-common.h

   1 /*
   2  * (C) Copyright 2009
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef __MANROLAND_MPC52XX__COMMON_H
   9 #define __MANROLAND_MPC52XX__COMMON_H
  10
  11 /*
  12  * High Level Configuration Options
  13  * (easy to change)
  14  */
  15 #define CONFIG_MPC5200          1       /* MPC5200 CPU */
  16
  17 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33.000000MHz */
  18
  19 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  20
  21 /*
  22  * Serial console configuration
  23  */
  24 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1   */
  25 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200,\
  26                                          230400 }
  27
  28 #if (CONFIG_SYS_TEXT_BASE == 0xFFF00000) /* Boot low */
  29 #   define CONFIG_SYS_LOWBOOT           1
  30 #endif
  31
  32 /*
  33  * IPB Bus clocking configuration.
  34  */
  35 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
  36
  37 /*
  38  * I2C configuration
  39  */
  40 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
  41 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
  42
  43 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
  44 #define CONFIG_SYS_I2C_SLAVE            0x7F
  45
  46 /*
  47  * EEPROM configuration
  48  */
  49 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x58
  50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          1
  51 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       4
  52 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10
  53
  54 /*
  55  * RTC configuration
  56  */
  57 #define CONFIG_RTC_PCF8563
  58 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
  59
  60 /* I2C SYSMON (LM75) */
  61 #define CONFIG_DTT_LM81                 1       /* ON Semi's LM75       */
  62 #define CONFIG_DTT_SENSORS              {0}     /* Sensor addresses     */
  63 #define CONFIG_SYS_DTT_MAX_TEMP         70
  64 #define CONFIG_SYS_DTT_LOW_TEMP         -30
  65 #define CONFIG_SYS_DTT_HYSTERESIS               3
  66
  67 /*
  68  * Flash configuration
  69  */
  70 #define CONFIG_SYS_FLASH_BASE           0xFF800000
  71
  72 #define CONFIG_SYS_FLASH_SIZE           0x00800000 /* 8 MByte */
  73
  74 #define CONFIG_ENV_ADDR         (CONFIG_SYS_TEXT_BASE+0x40000) /* second sector */
  75 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max num of flash banks
  76                                            (= chip selects) */
  77 #define CONFIG_SYS_FLASH_ERASE_TOUT     240000  /* Flash Erase Timeout [ms]*/
  78 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout [ms]*/
  79
  80 #define CONFIG_FLASH_CFI_DRIVER
  81 #define CONFIG_SYS_FLASH_CFI
  82 #define CONFIG_SYS_FLASH_EMPTY_INFO
  83 #define CONFIG_SYS_FLASH_CFI_AMD_RESET
  84
  85 /*
  86  * Environment settings
  87  */
  88 #define CONFIG_ENV_IS_IN_FLASH  1
  89 #define CONFIG_ENV_SIZE         0x4000
  90 #define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SECT_SIZE)
  91 #define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)
  92
  93 /*
  94  * Memory map
  95  */
  96 #define CONFIG_SYS_MBAR         0xF0000000
  97 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
  98
  99 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE -\
 100                                          GENERATED_GBL_DATA_SIZE)
 101 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 102
 103 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 104 #define CONFIG_SYS_SRAM_BASE    0x80100000      /* CS 1 */
 105 #define CONFIG_SYS_DISPLAY_BASE 0x80600000      /* CS 3 */
 106
 107 /* Settings for XLB = 132 MHz */
 108 #define SDRAM_DDR        1
 109 #define SDRAM_MODE      0x018D0000
 110 #define SDRAM_EMODE     0x40090000
 111 #define SDRAM_CONTROL   0x714f0f00
 112 #define SDRAM_CONFIG1   0x73722930
 113 #define SDRAM_CONFIG2   0x47770000
 114 #define SDRAM_TAPDELAY  0x10000000
 115
 116 /* Use ON-Chip SRAM until RAM will be available */
 117 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 118 #ifdef CONFIG_POST
 119 /* preserve space for the post_word at end of on-chip SRAM */
 120 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_POST_SIZE
 121 #else
 122 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE
 123 #endif
 124
 125 #define CONFIG_SYS_MONITOR_BASE    CONFIG_SYS_TEXT_BASE
 126 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 127 #   define CONFIG_SYS_RAMBOOT           1
 128 #endif
 129
 130 #define CONFIG_SYS_MONITOR_LEN          (192 << 10)
 131 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)
 132 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)
 133
 134 /*
 135  * Ethernet configuration
 136  */
 137 #define CONFIG_MPC5xxx_FEC      1
 138 #define CONFIG_MPC5xxx_FEC_MII100
 139 #define CONFIG_PHY_ADDR         0x00
 140 #define CONFIG_MII              1
 141
 142 /*use  Hardware WDT */
 143 #define CONFIG_HW_WATCHDOG
 144
 145 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs             */
 146 #if defined(CONFIG_CMD_KGDB)
 147 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value*/
 148 #endif
 149
 150 /*
 151  * Various low-level settings
 152  */
 153 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 154 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 155
 156 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 157 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 158 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 159 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 160
 161 /* 8Mbit SRAM @0x80100000 */
 162 #define CONFIG_SYS_CS1_START            CONFIG_SYS_SRAM_BASE
 163
 164 #define CONFIG_SYS_CS_BURST             0x00000000
 165 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 166
 167 /*-----------------------------------------------------------------------
 168  * IDE/ATA stuff Supports IDE harddisk
 169  *-----------------------------------------------------------------------
 170  */
 171
 172 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 173
 174 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 175 #undef  CONFIG_IDE_LED                  /* LED   for ide not supported  */
 176
 177 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus       */
 178
 179 #define CONFIG_IDE_PREINIT      1
 180
 181 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 182
 183 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 184
 185 /* Offset for data I/O                  */
 186 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 187
 188 /* Offset for normal register accesses  */
 189 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 190
 191 /* Offset for alternate registers       */
 192 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 193
 194 /* Interval between registers   */
 195 #define CONFIG_SYS_ATA_STRIDE          4
 196
 197 #define CONFIG_ATAPI            1
 198
 199 #define OF_CPU                  "PowerPC,5200@0"
 200 #define OF_SOC                  "soc5200@f0000000"
 201 #define OF_TBCLK                (bd->bi_busfreq / 4)
 202 #define OF_STDOUT_PATH          "/soc5200@f0000000/serial@2000"
 203 #define CONFIG_OF_IDE_FIXUP
 204
 205 #endif /* __MANROLAND_MPC52XX__COMMON_H */