include/configs/maxbcm.h

   1 /*
   2  * Copyright (C) 2014 Stefan Roese <sr@denx.de>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _CONFIG_DB_MV7846MP_GP_H
   8 #define _CONFIG_DB_MV7846MP_GP_H
   9
  10 /*
  11  * High Level Configuration Options (easy to change)
  12  */
  13 #define CONFIG_ARMADA_XP                /* SOC Family Name */
  14 #define CONFIG_SKIP_LOWLEVEL_INIT       /* disable board lowlevel_init */
  15 #define CONFIG_SYS_GENERIC_BOARD
  16 #define CONFIG_DISPLAY_BOARDINFO_LATE
  17
  18 /*
  19  * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
  20  * for DDR ECC byte filling in the SPL before loading the main
  21  * U-Boot into it.
  22  */
  23 #define CONFIG_SYS_TEXT_BASE    0x00800000
  24 #define CONFIG_SYS_TCLK         250000000       /* 250MHz */
  25
  26 /*
  27  * Commands configuration
  28  */
  29 #define CONFIG_SYS_NO_FLASH             /* Declare no flash (NOR/SPI) */
  30 #define CONFIG_CMD_DHCP
  31 #define CONFIG_CMD_ENV
  32 #define CONFIG_CMD_I2C
  33 #define CONFIG_CMD_PING
  34 #define CONFIG_CMD_SF
  35 #define CONFIG_CMD_SPI
  36 #define CONFIG_CMD_TFTPPUT
  37 #define CONFIG_CMD_TIME
  38
  39 /* I2C */
  40 #define CONFIG_SYS_I2C
  41 #define CONFIG_SYS_I2C_MVTWSI
  42 #define CONFIG_I2C_MVTWSI_BASE0         MVEBU_TWSI_BASE
  43 #define CONFIG_SYS_I2C_SLAVE            0x0
  44 #define CONFIG_SYS_I2C_SPEED            100000
  45
  46 /* SPI NOR flash default params, used by sf commands */
  47 #define CONFIG_SF_DEFAULT_SPEED         1000000
  48 #define CONFIG_SF_DEFAULT_MODE          SPI_MODE_3
  49 #define CONFIG_SPI_FLASH_STMICRO
  50 #define CONFIG_SPI_FLASH_SPANSION
  51
  52 /* Environment in SPI NOR flash */
  53 #define CONFIG_ENV_IS_IN_SPI_FLASH
  54 #define CONFIG_ENV_OFFSET               (1 << 20) /* 1MiB in */
  55 #define CONFIG_ENV_SIZE                 (64 << 10) /* 64KiB */
  56 #define CONFIG_ENV_SECT_SIZE            (64 << 10) /* 64KiB sectors */
  57
  58 #define CONFIG_PHY_MARVELL              /* there is a marvell phy */
  59 #define CONFIG_PHY_ADDR                 { 0x0, 0x1, 0x2, 0x3 }
  60 #define CONFIG_SYS_NETA_INTERFACE_TYPE  PHY_INTERFACE_MODE_SGMII
  61 #define PHY_ANEG_TIMEOUT        8000    /* PHY needs a longer aneg time */
  62 #define CONFIG_RESET_PHY_R
  63
  64 #define CONFIG_SYS_CONSOLE_INFO_QUIET   /* don't print console @ startup */
  65 #define CONFIG_SYS_ALT_MEMTEST
  66
  67 /*
  68  * mv-common.h should be defined after CMD configs since it used them
  69  * to enable certain macros
  70  */
  71 #include "mv-common.h"
  72
  73 /*
  74  * Memory layout while starting into the bin_hdr via the
  75  * BootROM:
  76  *
  77  * 0x4000.4000 - 0x4003.4000    headers space (192KiB)
  78  * 0x4000.4030                  bin_hdr start address
  79  * 0x4003.4000 - 0x4004.7c00    BootROM memory allocations (15KiB)
  80  * 0x4007.fffc                  BootROM stack top
  81  *
  82  * The address space between 0x4007.fffc and 0x400f.fff is not locked in
  83  * L2 cache thus cannot be used.
  84  */
  85
  86 /* SPL */
  87 /* Defines for SPL */
  88 #define CONFIG_SPL_FRAMEWORK
  89 #define CONFIG_SPL_TEXT_BASE            0x40004030
  90 #define CONFIG_SPL_MAX_SIZE             ((128 << 10) - 0x4030)
  91
  92 #define CONFIG_SPL_BSS_START_ADDR       (0x40000000 + (128 << 10))
  93 #define CONFIG_SPL_BSS_MAX_SIZE         (16 << 10)
  94
  95 #define CONFIG_SYS_SPL_MALLOC_START     (CONFIG_SPL_BSS_START_ADDR + \
  96                                          CONFIG_SPL_BSS_MAX_SIZE)
  97 #define CONFIG_SYS_SPL_MALLOC_SIZE      (16 << 10)
  98
  99 #define CONFIG_SPL_STACK                (0x40000000 + ((192 - 16) << 10))
 100 #define CONFIG_SPL_BOOTROM_SAVE         (CONFIG_SPL_STACK + 4)
 101
 102 #define CONFIG_SPL_LIBCOMMON_SUPPORT
 103 #define CONFIG_SPL_LIBGENERIC_SUPPORT
 104 #define CONFIG_SPL_SERIAL_SUPPORT
 105 #define CONFIG_SPL_I2C_SUPPORT
 106
 107 /* SPL related SPI defines */
 108 #define CONFIG_SPL_SPI_SUPPORT
 109 #define CONFIG_SPL_SPI_FLASH_SUPPORT
 110 #define CONFIG_SPL_SPI_LOAD
 111 #define CONFIG_SPL_SPI_BUS              0
 112 #define CONFIG_SPL_SPI_CS               0
 113 #define CONFIG_SYS_SPI_U_BOOT_OFFS      0x20000
 114
 115 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
 116 #define CONFIG_SYS_MVEBU_DDR_AXP
 117 #define CONFIG_DDR_FIXED_SIZE           (1 << 20)       /* 1GiB */
 118
 119 #endif /* _CONFIG_DB_MV7846MP_GP_H */