]>
git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/maxbcm.h
2 * Copyright (C) 2014 Stefan Roese <sr@denx.de>
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef _CONFIG_DB_MV7846MP_GP_H
8 #define _CONFIG_DB_MV7846MP_GP_H
11 * High Level Configuration Options (easy to change)
13 #define CONFIG_ARMADA_XP /* SOC Family Name */
14 #ifdef CONFIG_SPL_BUILD
15 #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */
17 #define CONFIG_DISPLAY_BOARDINFO_LATE
20 * TEXT_BASE needs to be below 16MiB, since this area is scrubbed
21 * for DDR ECC byte filling in the SPL before loading the main
24 #define CONFIG_SYS_TEXT_BASE 0x00800000
25 #define CONFIG_SYS_TCLK 250000000 /* 250MHz */
28 * Commands configuration
30 #define CONFIG_SYS_NO_FLASH /* Declare no flash (NOR/SPI) */
31 #define CONFIG_CMD_DHCP
32 #define CONFIG_CMD_ENV
33 #define CONFIG_CMD_I2C
34 #define CONFIG_CMD_PING
36 #define CONFIG_CMD_SPI
37 #define CONFIG_CMD_TFTPPUT
38 #define CONFIG_CMD_TIME
41 #define CONFIG_SYS_I2C
42 #define CONFIG_SYS_I2C_MVTWSI
43 #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE
44 #define CONFIG_SYS_I2C_SLAVE 0x0
45 #define CONFIG_SYS_I2C_SPEED 100000
47 /* SPI NOR flash default params, used by sf commands */
48 #define CONFIG_SF_DEFAULT_SPEED 1000000
49 #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3
51 /* Environment in SPI NOR flash */
52 #define CONFIG_ENV_IS_IN_SPI_FLASH
53 #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */
54 #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */
55 #define CONFIG_ENV_SECT_SIZE (64 << 10) /* 64KiB sectors */
57 #define CONFIG_PHY_MARVELL /* there is a marvell phy */
58 #define CONFIG_PHY_ADDR { 0x0, 0x1, 0x2, 0x3 }
59 #define CONFIG_SYS_NETA_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII
60 #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */
61 #define CONFIG_RESET_PHY_R
63 #define CONFIG_SYS_CONSOLE_INFO_QUIET /* don't print console @ startup */
64 #define CONFIG_SYS_ALT_MEMTEST
67 * mv-common.h should be defined after CMD configs since it used them
68 * to enable certain macros
70 #include "mv-common.h"
73 * Memory layout while starting into the bin_hdr via the
76 * 0x4000.4000 - 0x4003.4000 headers space (192KiB)
77 * 0x4000.4030 bin_hdr start address
78 * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB)
79 * 0x4007.fffc BootROM stack top
81 * The address space between 0x4007.fffc and 0x400f.fff is not locked in
82 * L2 cache thus cannot be used.
87 #define CONFIG_SPL_FRAMEWORK
88 #define CONFIG_SPL_TEXT_BASE 0x40004030
89 #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030)
91 #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10))
92 #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10)
94 #ifdef CONFIG_SPL_BUILD
95 #define CONFIG_SYS_MALLOC_SIMPLE
98 #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10))
99 #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4)
101 #define CONFIG_SPL_LIBCOMMON_SUPPORT
102 #define CONFIG_SPL_LIBGENERIC_SUPPORT
103 #define CONFIG_SPL_SERIAL_SUPPORT
104 #define CONFIG_SPL_I2C_SUPPORT
106 /* SPL related SPI defines */
107 #define CONFIG_SPL_SPI_SUPPORT
108 #define CONFIG_SPL_SPI_FLASH_SUPPORT
109 #define CONFIG_SPL_SPI_LOAD
110 #define CONFIG_SPL_SPI_BUS 0
111 #define CONFIG_SPL_SPI_CS 0
112 #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x20000
114 /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */
115 #define CONFIG_SYS_MVEBU_DDR_AXP
116 #define CONFIG_DDR_FIXED_SIZE (1 << 20) /* 1GiB */
118 #endif /* _CONFIG_DB_MV7846MP_GP_H */