include/configs/mcc200.h

   1 /*
   2  * (C) Copyright 2006-2008
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5200
  33 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  34 #define CONFIG_MCC200           1       /* ... on MCC200 board                  */
  35
  36 /*
  37  * Valid values for CONFIG_SYS_TEXT_BASE are:
  38  * 0xFC000000   boot low (standard configuration)
  39  * 0xFFF00000   boot high
  40  * 0x00100000   boot from RAM (for testing only)
  41  */
  42 #ifndef CONFIG_SYS_TEXT_BASE
  43 #define CONFIG_SYS_TEXT_BASE    0xFC000000
  44 #endif
  45
  46 #define CONFIG_SYS_MPC5XXX_CLKIN        33000000 /* ... running at 33MHz                */
  47
  48 #define CONFIG_MISC_INIT_R
  49
  50 #define CONFIG_HIGH_BATS        1       /* High BATs supported                  */
  51
  52 /*
  53  * Serial console configuration
  54  *
  55  *  To select console on the one of 8 external UARTs,
  56  * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
  57  * or as 5, 6, 7, or 8 for the second Quad UART.
  58  * COM11, COM12, COM13, COM14 are located on the second Quad UART.
  59  *
  60  *  CONFIG_PSC_CONSOLE must be undefined in this case.
  61  */
  62 #if !defined(CONFIG_PRS200)
  63 /* MCC200 configuration: */
  64 #ifdef CONFIG_CONSOLE_COM12
  65 #define CONFIG_QUART_CONSOLE    6       /* console is on UARTF of QUART2        */
  66 #else
  67 #define CONFIG_QUART_CONSOLE    8       /* console is on UARTH of QUART2        */
  68 #endif
  69 #else
  70 /* PRS200 configuration: */
  71 #undef CONFIG_QUART_CONSOLE
  72 #endif /* CONFIG_PRS200 */
  73 /*
  74  *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
  75  * and undefine CONFIG_QUART_CONSOLE.
  76  */
  77 #if !defined(CONFIG_PRS200)
  78 /* MCC200 configuration: */
  79 #define CONFIG_PSC_CONSOLE      1       /* PSC1 may be COM */
  80 #define CONFIG_PSC_CONSOLE2     2       /* PSC2 is PSoC */
  81 #else
  82 /* PRS200 configuration: */
  83 #define CONFIG_PSC_CONSOLE      1       /* console is on PSC1           */
  84 #endif
  85 #define CONFIG_BAUDRATE         115200
  86 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200, 230400 }
  87
  88 #define CONFIG_MII              1
  89
  90 #define CONFIG_DOS_PARTITION
  91
  92 /* USB */
  93 #define CONFIG_USB_OHCI
  94 #define CONFIG_USB_STORAGE
  95 /* automatic software updates (see board/mcc200/auto_update.c) */
  96 #define CONFIG_AUTO_UPDATE 1
  97
  98
  99 /*
 100  * BOOTP options
 101  */
 102 #define CONFIG_BOOTP_BOOTFILESIZE
 103 #define CONFIG_BOOTP_BOOTPATH
 104 #define CONFIG_BOOTP_GATEWAY
 105 #define CONFIG_BOOTP_HOSTNAME
 106
 107
 108 /*
 109  * Command line configuration.
 110  */
 111 #include <config_cmd_default.h>
 112
 113 #define CONFIG_CMD_BEDBUG
 114 #define CONFIG_CMD_FAT
 115 #define CONFIG_CMD_I2C
 116 #define CONFIG_CMD_USB
 117
 118 #undef  CONFIG_CMD_NET
 119 #undef  CONFIG_CMD_NFS
 120
 121 /*
 122  * Autobooting
 123  */
 124 #define CONFIG_BOOTDELAY        1       /* autoboot after 1 second */
 125
 126 #define CONFIG_PREBOOT  "echo;" \
 127         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 128         "echo"
 129
 130 #undef  CONFIG_BOOTARGS
 131
 132 #ifdef CONFIG_PRS200
 133 # define CONFIG_SYS__BOARDNAME          "prs200"
 134 # define CONFIG_SYS__LINUX_CONSOLE      "ttyS0"
 135 #else
 136 # define CONFIG_SYS__BOARDNAME          "mcc200"
 137 # define CONFIG_SYS__LINUX_CONSOLE      "ttyEU5"
 138 #endif
 139
 140 /* Network */
 141 #define CONFIG_ETHADDR  00:17:17:ff:00:00
 142 #define CONFIG_IPADDR   10.76.9.29
 143 #define CONFIG_SERVERIP 10.76.9.1
 144
 145 #include <version.h> /* For U-Boot version */
 146
 147 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 148         "ubootver=" U_BOOT_VERSION "\0"                                 \
 149         "netdev=eth0\0"                                                 \
 150         "hostname=" CONFIG_SYS__BOARDNAME "\0"                          \
 151         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 152                 "nfsroot=${serverip}:${rootpath}\0"                     \
 153         "ramargs=setenv bootargs root=/dev/mtdblock2 "                  \
 154                 "rootfstype=cramfs\0"                                   \
 155         "addip=setenv bootargs ${bootargs} "                            \
 156                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 157                 ":${hostname}:${netdev}:off panic=1\0"                  \
 158         "addcons=setenv bootargs ${bootargs} "                          \
 159                 "console=${console},${baudrate} "                       \
 160                 "ubootver=${ubootver} board=${board}\0"                 \
 161         "flash_nfs=run nfsargs addip addcons;"                          \
 162                 "bootm ${kernel_addr}\0"                                \
 163         "flash_self=run ramargs addip addcons;"                         \
 164                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 165         "net_nfs=tftp 200000 ${bootfile};"                              \
 166                 "run nfsargs addip addcons;bootm\0"                     \
 167         "console=" CONFIG_SYS__LINUX_CONSOLE "\0"                               \
 168         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 169         "bootfile=/tftpboot/" CONFIG_SYS__BOARDNAME "/uImage\0"         \
 170         "load=tftp 200000 /tftpboot/" CONFIG_SYS__BOARDNAME "/u-boot.bin\0"     \
 171         "text_base=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"             \
 172         "kernel_addr=0xFC0C0000\0"                                      \
 173         "update=protect off ${text_base} +${filesize};"                 \
 174                 "era ${text_base} +${filesize};"                        \
 175                 "cp.b 200000 ${text_base} ${filesize}\0"                \
 176         "unlock=yes\0"                                                  \
 177         ""
 178
 179 #define CONFIG_BOOTCOMMAND      "run flash_self"
 180
 181 #define CONFIG_SYS_HUSH_PARSER          1       /* use "hush" command parser    */
 182
 183 /*
 184  * IPB Bus clocking configuration.
 185  */
 186 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK         /* define for 133MHz speed */
 187
 188 /*
 189  * I2C configuration
 190  */
 191 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 192 #define CONFIG_SYS_I2C_MODULE           2       /* Select I2C module #1 or #2 */
 193
 194 #define CONFIG_SYS_I2C_SPEED            100000 /* 100 kHz */
 195 #define CONFIG_SYS_I2C_SLAVE            0x7F
 196
 197 /*
 198  * Flash configuration (8,16 or 32 MB)
 199  * TEXT base always at 0xFFF00000
 200  * ENV_ADDR always at  0xFFF40000
 201  * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 202  *               0xFE000000 for 32 MB
 203  *               0xFF000000 for 16 MB
 204  *               0xFF800000 for  8 MB
 205  */
 206 #define CONFIG_SYS_FLASH_BASE           0xfc000000
 207 #define CONFIG_SYS_FLASH_SIZE           0x04000000
 208
 209 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 210 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 211
 212 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 213
 214 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 215 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 216
 217 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 218 #define CONFIG_SYS_FLASH_PROTECTION     1       /* hardware flash protection            */
 219
 220 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 221 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 222
 223 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 224 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 225
 226 #define CONFIG_ENV_IS_IN_FLASH  1       /* use FLASH for environment vars       */
 227
 228 #define CONFIG_ENV_SECT_SIZE    0x40000 /* size of one complete sector  */
 229 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 230 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 231
 232 /* Address and size of Redundant Environment Sector     */
 233 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 234 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 235
 236 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 237
 238 #if CONFIG_SYS_TEXT_BASE == CONFIG_SYS_FLASH_BASE
 239 #define CONFIG_SYS_LOWBOOT      1
 240 #endif
 241
 242 /*
 243  * Memory map
 244  */
 245 #define CONFIG_SYS_MBAR         0xf0000000
 246 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 247 #define CONFIG_SYS_DEFAULT_MBAR 0x80000000
 248
 249 /* Use SRAM until RAM will be available */
 250 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 251 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used area in DPRAM */
 252
 253
 254 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 255 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 256
 257 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 258 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 259 #   define CONFIG_SYS_RAMBOOT           1
 260 #endif
 261
 262 #define CONFIG_SYS_MONITOR_LEN          (256 << 10)     /* Reserve 256 kB for Monitor   */
 263 #define CONFIG_SYS_MALLOC_LEN           (512 << 10)     /* Reserve 512 kB for malloc()  */
 264 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 265
 266 /*
 267  * Ethernet configuration
 268  */
 269 /* #define CONFIG_MPC5xxx_FEC   1 */
 270 /* #define CONFIG_MPC5xxx_FEC_MII100 */
 271 /*
 272  * Define CONFIG_MPC5xxx_FEC_MII10 to force FEC at 10Mb
 273  */
 274 /* #define CONFIG_MPC5xxx_FEC_MII10 */
 275 #define CONFIG_PHY_ADDR         1
 276
 277 /*
 278  * LCD Splash Screen
 279  */
 280 #if !defined(CONFIG_PRS200)
 281 #define CONFIG_LCD              1
 282 #define CONFIG_PROGRESSBAR 1
 283 #endif
 284
 285 #if defined(CONFIG_LCD)
 286 #define CONFIG_SPLASH_SCREEN    1
 287 #define CONFIG_SYS_CONSOLE_IS_IN_ENV    1
 288 #define LCD_BPP                 LCD_MONOCHROME
 289 #endif
 290
 291 /*
 292  * GPIO configuration
 293  */
 294 /* 0x10000004 = 32MB SDRAM */
 295 /* 0x90000004 = 64MB SDRAM */
 296 #if defined(CONFIG_LCD)
 297 /* set PSC2 in UART mode */
 298 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00000044
 299 #else
 300 #define CONFIG_SYS_GPS_PORT_CONFIG      0x00000004
 301 #endif
 302
 303 /*
 304  * Miscellaneous configurable options
 305  */
 306 #define CONFIG_SYS_LONGHELP                     /* undef to save memory         */
 307 #define CONFIG_SYS_PROMPT               "=> "   /* Monitor Command Prompt       */
 308 #if defined(CONFIG_CMD_KGDB)
 309 #define CONFIG_SYS_CBSIZE               1024    /* Console I/O Buffer Size      */
 310 #else
 311 #define CONFIG_SYS_CBSIZE               256     /* Console I/O Buffer Size      */
 312 #endif
 313 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)      /* Print Buffer Size    */
 314 #define CONFIG_SYS_MAXARGS              16              /* max number of command args   */
 315 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size    */
 316
 317 #define CONFIG_SYS_MEMTEST_START        0x00100000      /* memtest works on     */
 318 #define CONFIG_SYS_MEMTEST_END          0x00f00000      /* 1 ... 15 MB in DRAM  */
 319
 320 #define CONFIG_SYS_LOAD_ADDR            0x100000        /* default load address */
 321
 322 #define CONFIG_SYS_HZ                   1000    /* decrementer freq: 1 ms ticks */
 323
 324 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC5xxx CPUs                     */
 325 #if defined(CONFIG_CMD_KGDB)
 326 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value        */
 327 #endif
 328
 329 /*
 330  * Various low-level settings
 331  */
 332 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 333 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 334
 335 #define CONFIG_SYS_BOOTCS_START CONFIG_SYS_FLASH_BASE
 336 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 337 #define CONFIG_SYS_BOOTCS_CFG           0x0004fb00
 338 #define CONFIG_SYS_CS0_START            CONFIG_SYS_FLASH_BASE
 339 #define CONFIG_SYS_CS0_SIZE             CONFIG_SYS_FLASH_SIZE
 340
 341 /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 342 #define CONFIG_SYS_CS2_START            0x80000000
 343 #define CONFIG_SYS_CS2_SIZE             0x00001000
 344 #define CONFIG_SYS_CS2_CFG              0x1d300
 345
 346 /* Second Quad UART @0x80010000 */
 347 #define CONFIG_SYS_CS1_START            0x80010000
 348 #define CONFIG_SYS_CS1_SIZE             0x00001000
 349 #define CONFIG_SYS_CS1_CFG              0x1d300
 350
 351 /* Leica - build revision resistors */
 352 /*
 353 #define CONFIG_SYS_CS3_START            0x80020000
 354 #define CONFIG_SYS_CS3_SIZE             0x00000004
 355 #define CONFIG_SYS_CS3_CFG              0x1d300
 356 */
 357
 358 /*
 359  *  Select one of quarts as a default
 360  * console. If undefined - PSC console
 361  * wil be default
 362  */
 363 #define CONFIG_SYS_CS_BURST             0x00000000
 364 #define CONFIG_SYS_CS_DEADCYCLE 0x33333333
 365
 366 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 367
 368 /*
 369  * QUART Expanders support
 370  */
 371 #if defined(CONFIG_QUART_CONSOLE)
 372 /*
 373  * We'll use NS16550 chip routines,
 374  */
 375 #define CONFIG_SYS_NS16550              1
 376 #define CONFIG_SYS_NS16550_SERIAL       1
 377 #define CONFIG_CONS_INDEX       1
 378 /*
 379  *  To achieve necessary offset on SC16C554
 380  * A0-A2 (register select) pins with NS16550
 381  * functions (in struct NS16550), REG_SIZE
 382  * should be 4, because A0-A2 pins are connected
 383  * to DA2-DA4 address bus lines.
 384  */
 385 #define CONFIG_SYS_NS16550_REG_SIZE     4
 386 /*
 387  * LocalPlus Bus already inited in cpu_init_f(),
 388  * so can work with QUART's chip selects.
 389  * One of four SC16C554 UARTs is selected with
 390  * A3-A4 (DA5-DA6) lines.
 391  */
 392 #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5) && !defined(CONFIG_PRS200)
 393 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
 394 #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
 395 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
 396 #else
 397 #error "Wrong QUART expander number."
 398 #endif
 399
 400 /*
 401  * SC16C554 chip's external crystal oscillator frequency
 402  * is 7.3728 MHz
 403  */
 404 #define CONFIG_SYS_NS16550_CLK          7372800
 405 #endif /* CONFIG_QUART_CONSOLE */
 406 /*-----------------------------------------------------------------------
 407  * USB stuff
 408  *-----------------------------------------------------------------------
 409  */
 410 #define CONFIG_USB_CLOCK        0x0001BBBB
 411 #define CONFIG_USB_CONFIG       0x00005000
 412
 413 #define CONFIG_AUTOBOOT_KEYED           /* use key strings to stop autoboot     */
 414 #define CONFIG_AUTOBOOT_STOP_STR        "432"
 415 #define CONFIG_SILENT_CONSOLE   1
 416
 417 #endif /* __CONFIG_H */