include/configs/mcc200.h

   1 /*
   2  * (C) Copyright 2006
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC5200
  33 #define CONFIG_MPC5xxx          1       /* This is an MPC5xxx CPU               */
  34 #define CONFIG_MCC200           1       /* ... on MCC200 board                  */
  35
  36 #define CFG_MPC5XXX_CLKIN       33000000 /* ... running at 33MHz                */
  37
  38 #define CONFIG_MISC_INIT_R
  39
  40 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH     */
  41 #define BOOTFLAG_WARM           0x02    /* Software reboot                      */
  42
  43 #define CFG_CACHELINE_SIZE      32      /* For MPC5xxx CPUs                     */
  44 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
  45 #  define CFG_CACHELINE_SHIFT   5       /* log base 2 of the above value        */
  46 #endif
  47
  48 /*
  49  * Serial console configuration
  50  *
  51  *  To select console on the one of 8 external UARTs,
  52  * define CONFIG_QUART_CONSOLE as 1, 2, 3, or 4 for the first Quad UART,
  53  * or as 5, 6, 7, or 8 for the second Quad UART.
  54  * COM11, COM12, COM13, COM14 are located on the second Quad UART.
  55  *
  56  *  CONFIG_PSC_CONSOLE must be undefined in this case.
  57  */
  58 #ifdef CONFIG_CONSOLE_COM12
  59 #define CONFIG_QUART_CONSOLE    6       /* console is on UARTF of QUART2        */
  60 #else
  61 #define CONFIG_QUART_CONSOLE    8       /* console is on UARTH of QUART2        */
  62 #endif
  63 /*
  64  *  To select console on PSC1, define CONFIG_PSC_CONSOLE as 1
  65  * and undefine CONFIG_QUART_CONSOLE.
  66  */
  67 /*#define CONFIG_PSC_CONSOLE    1       */ /* console is on PSC1                */
  68 #if defined(CONFIG_QUART_CONSOLE) && defined(CONFIG_PSC_CONSOLE)
  69 #error "Select only one console device!"
  70 #endif
  71 #define CONFIG_BAUDRATE         115200
  72 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200, 230400 }
  73
  74 #define CONFIG_MII              1
  75
  76 #define CONFIG_DOS_PARTITION
  77
  78 /* USB */
  79 #define CONFIG_USB_OHCI
  80 #define ADD_USB_CMD             CFG_CMD_USB | CFG_CMD_FAT
  81 #define CONFIG_USB_STORAGE
  82
  83 /*
  84  * Supported commands
  85  */
  86 #define CONFIG_COMMANDS        (CONFIG_CMD_DFL  | \
  87                                 ADD_USB_CMD     | \
  88                                 CFG_CMD_BEDBUG  | \
  89                                 CFG_CMD_FAT     | \
  90                                 CFG_CMD_I2C)
  91
  92 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
  93 #include <cmd_confdefs.h>
  94
  95 /*
  96  * Autobooting
  97  */
  98 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds */
  99
 100 #define CONFIG_PREBOOT  "echo;" \
 101         "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \
 102         "echo"
 103
 104 #undef  CONFIG_BOOTARGS
 105
 106 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 107         "netdev=eth0\0"                                                 \
 108         "hostname=mcc200\0"                                             \
 109         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 110                 "nfsroot=${serverip}:${rootpath}\0"                     \
 111         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 112         "addip=setenv bootargs ${bootargs} "                            \
 113                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 114                 ":${hostname}:${netdev}:off panic=1\0"                  \
 115         "flash_nfs=run nfsargs addip;"                                  \
 116                 "bootm ${kernel_addr}\0"                                \
 117         "flash_self=run ramargs addip;"                                 \
 118                 "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
 119         "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0"     \
 120         "rootpath=/opt/eldk/ppc_6xx\0"                                  \
 121         "bootfile=/tftpboot/mcc200/uImage\0"                            \
 122         "baudrate=115200\0"                                             \
 123         "load=tftp 200000 /tftpboot/mcc200/u-boot.bin\0"                \
 124         "update=protect off FFF00000 +${filesize};"                     \
 125                 "era FFF00000 +${filesize};"                            \
 126                 "cp.b 200000 FFF00000 ${filesize}\0"                    \
 127         "serverip=192.168.1.1\0"                                        \
 128         "ipaddr=192.168.133.144\0"                                      \
 129         "netmask=255.255.0.0\0"                                         \
 130         "unlock=yes\0"                                                  \
 131         "ethaddr=00:02:44:7D:73:3B\0"                                   \
 132         ""
 133
 134 #define CONFIG_BOOTCOMMAND      "run flash_self"
 135
 136 #define CFG_HUSH_PARSER         1       /* use "hush" command parser    */
 137 #define CFG_PROMPT_HUSH_PS2     "> "
 138
 139 /*
 140  * IPB Bus clocking configuration.
 141  */
 142 #define CFG_IPBSPEED_133                /* define for 133MHz speed */
 143
 144 /*
 145  * I2C configuration
 146  */
 147 #define CONFIG_HARD_I2C         1       /* I2C with hardware support */
 148 #define CFG_I2C_MODULE          1       /* Select I2C module #1 or #2 */
 149
 150 #define CFG_I2C_SPEED           100000 /* 100 kHz */
 151 #define CFG_I2C_SLAVE           0x7F
 152
 153 /*
 154  * Flash configuration (8,16 or 32 MB)
 155  * TEXT base always at 0xFFF00000
 156  * ENV_ADDR always at  0xFFF40000
 157  * FLASH_BASE at 0xFC000000 for 64 MB (only 32MB are supported, not enough addr lines!!!)
 158  *               0xFE000000 for 32 MB
 159  *               0xFF000000 for 16 MB
 160  *               0xFF800000 for  8 MB
 161  */
 162 #define CFG_FLASH_BASE          0xfc000000
 163 #define CFG_FLASH_SIZE          0x04000000
 164
 165 #define CFG_FLASH_CFI                           /* The flash is CFI compatible  */
 166 #define CFG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
 167
 168 #define CFG_FLASH_BANKS_LIST    { CFG_FLASH_BASE }
 169
 170 #define CFG_MAX_FLASH_BANKS     1       /* max number of memory banks           */
 171 #define CFG_MAX_FLASH_SECT      512     /* max number of sectors on one chip    */
 172
 173 #define CFG_FLASH_USE_BUFFER_WRITE 1    /* use buffered writes (20x faster)     */
 174 #define CFG_FLASH_PROTECTION    1       /* hardware flash protection            */
 175
 176 #define CFG_FLASH_ERASE_TOUT    120000  /* Timeout for Flash Erase (in ms)      */
 177 #define CFG_FLASH_WRITE_TOUT    500     /* Timeout for Flash Write (in ms)      */
 178
 179 #define CFG_FLASH_EMPTY_INFO            /* print 'E' for empty sector on flinfo */
 180 #define CFG_FLASH_QUIET_TEST    1       /* don't warn upon unknown flash        */
 181
 182 #define CFG_ENV_IS_IN_FLASH     1       /* use FLASH for environment vars       */
 183
 184 #define CFG_ENV_SECT_SIZE       0x40000         /* size of one complete sector  */
 185 #define CFG_ENV_ADDR            (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
 186 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment Sector     */
 187
 188 /* Address and size of Redundant Environment Sector     */
 189 #define CFG_ENV_ADDR_REDUND     (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE)
 190 #define CFG_ENV_SIZE_REDUND     (CFG_ENV_SIZE)
 191
 192 #define CONFIG_ENV_OVERWRITE    1       /* allow modification of vendor params */
 193
 194 #if TEXT_BASE == CFG_FLASH_BASE
 195 #define CFG_LOWBOOT     1
 196 #endif
 197
 198 /*
 199  * Memory map
 200  */
 201 #define CFG_MBAR                0xf0000000
 202 #define CFG_SDRAM_BASE          0x00000000
 203 #define CFG_DEFAULT_MBAR        0x80000000
 204
 205 /* Use SRAM until RAM will be available */
 206 #define CFG_INIT_RAM_ADDR       MPC5XXX_SRAM
 207 #define CFG_INIT_RAM_END        MPC5XXX_SRAM_SIZE       /* End of used area in DPRAM */
 208
 209
 210 #define CFG_GBL_DATA_SIZE       128     /* size in bytes reserved for initial data */
 211 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 212 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 213
 214 #define CFG_MONITOR_BASE    TEXT_BASE
 215 #if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
 216 #   define CFG_RAMBOOT          1
 217 #endif
 218
 219 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 220 #define CFG_MALLOC_LEN          (512 << 10)     /* Reserve 512 kB for malloc()  */
 221 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 222
 223 /*
 224  * Ethernet configuration
 225  */
 226 #define CONFIG_MPC5xxx_FEC      1
 227 /*
 228  * Define CONFIG_FEC_10MBIT to force FEC at 10Mb
 229  */
 230 /* #define CONFIG_FEC_10MBIT 1 */
 231 #define CONFIG_PHY_ADDR         1
 232
 233 /*
 234  * GPIO configuration
 235  */
 236 /* 0x10000004 = 32MB SDRAM */
 237 /* 0x90000004 = 64MB SDRAM */
 238 #define CFG_GPS_PORT_CONFIG     0x00000004
 239
 240 /*
 241  * Miscellaneous configurable options
 242  */
 243 #define CFG_LONGHELP                    /* undef to save memory     */
 244 #define CFG_PROMPT              "=> "   /* Monitor Command Prompt   */
 245 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 246 #define CFG_CBSIZE              1024    /* Console I/O Buffer Size  */
 247 #else
 248 #define CFG_CBSIZE              256     /* Console I/O Buffer Size  */
 249 #endif
 250 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16)   /* Print Buffer Size */
 251 #define CFG_MAXARGS             16              /* max number of command args   */
 252 #define CFG_BARGSIZE            CFG_CBSIZE      /* Boot Argument Buffer Size    */
 253
 254 #define CFG_MEMTEST_START       0x00100000      /* memtest works on */
 255 #define CFG_MEMTEST_END         0x00f00000      /* 1 ... 15 MB in DRAM  */
 256
 257 #define CFG_LOAD_ADDR           0x100000        /* default load address */
 258
 259 #define CFG_HZ                  1000    /* decrementer freq: 1 ms ticks */
 260
 261 /*
 262  * Various low-level settings
 263  */
 264 #define CFG_HID0_INIT           HID0_ICE | HID0_ICFI
 265 #define CFG_HID0_FINAL          HID0_ICE
 266
 267 #define CFG_BOOTCS_START        CFG_FLASH_BASE
 268 #define CFG_BOOTCS_SIZE         CFG_FLASH_SIZE
 269 #define CFG_BOOTCS_CFG          0x0004fb00
 270 #define CFG_CS0_START           CFG_FLASH_BASE
 271 #define CFG_CS0_SIZE            CFG_FLASH_SIZE
 272
 273 /* Quad UART @0x80000000 (MBAR is relocated to 0xF0000000) */
 274 #define CFG_CS2_START           0x80000000
 275 #define CFG_CS2_SIZE            0x00001000
 276 #define CFG_CS2_CFG             0x1d300
 277
 278 /* Second Quad UART @0x80010000 */
 279 #define CFG_CS1_START           0x80010000
 280 #define CFG_CS1_SIZE            0x00001000
 281 #define CFG_CS1_CFG             0x1d300
 282
 283 /*
 284  *  Select one of quarts as a default
 285  * console. If undefined - PSC console
 286  * wil be default
 287  */
 288 #define CFG_CS_BURST            0x00000000
 289 #define CFG_CS_DEADCYCLE        0x33333333
 290
 291 #define CFG_RESET_ADDRESS       0xff000000
 292
 293 /*
 294  * QUART Expanders support
 295  */
 296 #if defined(CONFIG_QUART_CONSOLE)
 297 /*
 298  * We'll use NS16550 chip routines,
 299  */
 300 #define CFG_NS16550             1
 301 #define CFG_NS16550_SERIAL      1
 302 #define CONFIG_CONS_INDEX       1
 303 /*
 304  *  To achieve necessary offset on SC16C554
 305  * A0-A2 (register select) pins with NS16550
 306  * functions (in struct NS16550), REG_SIZE
 307  * should be 4, because A0-A2 pins are connected
 308  * to DA2-DA4 address bus lines.
 309  */
 310 #define CFG_NS16550_REG_SIZE    4
 311 /*
 312  * LocalPlus Bus already inited in cpu_init_f(),
 313  * so can work with QUART's chip selects.
 314  * One of four SC16C554 UARTs is selected with
 315  * A3-A4 (DA5-DA6) lines.
 316  */
 317 #if (CONFIG_QUART_CONSOLE > 0) && (CONFIG_QUART_CONSOLE < 5)
 318 #define CFG_NS16550_COM1        (CFG_CS2_START | (CONFIG_QUART_CONSOLE - 1)<<5)
 319 #elif (CONFIG_QUART_CONSOLE > 4) && (CONFIG_QUART_CONSOLE < 9)
 320 #define CFG_NS16550_COM1        (CFG_CS1_START | (CONFIG_QUART_CONSOLE - 5)<<5)
 321 #elif
 322 #error "Wrong QUART expander number."
 323 #endif
 324
 325 /*
 326  * SC16C554 chip's external crystal oscillator frequency
 327  * is 7.3728 MHz
 328  */
 329 #define CFG_NS16550_CLK         7372800
 330 #endif /* CONFIG_QUART_CONSOLE */
 331 /*-----------------------------------------------------------------------
 332  * USB stuff
 333  *-----------------------------------------------------------------------
 334  */
 335 #define CONFIG_USB_CLOCK        0x0001BBBB
 336 #define CONFIG_USB_CONFIG       0x00005000
 337
 338 #endif /* __CONFIG_H */