include/configs/meesc.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * (C) Copyright 2007-2008
   4  * Stelian Pop <stelian@popies.net>
   5  * Lead Tech Design <www.leadtechdesign.com>
   6  *
   7  * (C) Copyright 2009-2015
   8  * Daniel Gorsulowski <daniel.gorsulowski@esd.eu>
   9  * esd electronic system design gmbh <www.esd.eu>
  10  *
  11  * Configuation settings for the esd MEESC board.
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 /*
  18  * SoC must be defined first, before hardware.h is included.
  19  * In this case SoC is defined in boards.cfg.
  20  */
  21 #include <asm/hardware.h>
  22
  23 /*
  24  * Warning: changing CONFIG_SYS_TEXT_BASE requires
  25  * adapting the initial boot program.
  26  * Since the linker has to swallow that define, we must use a pure
  27  * hex number here!
  28  */
  29
  30 /* ARM asynchronous clock */
  31 #define CONFIG_SYS_AT91_SLOW_CLOCK      32768   /* 32.768 kHz crystal */
  32 #define CONFIG_SYS_AT91_MAIN_CLOCK      16000000/* 16.0 MHz crystal */
  33
  34 /* Misc CPU related */
  35 #define CONFIG_SKIP_LOWLEVEL_INIT
  36 #define CONFIG_SETUP_MEMORY_TAGS
  37 #define CONFIG_INITRD_TAG
  38 #define CONFIG_SERIAL_TAG
  39 #define CONFIG_REVISION_TAG
  40 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
  41
  42 /*
  43  * Hardware drivers
  44  */
  45
  46 /*
  47  * BOOTP options
  48  */
  49 #define CONFIG_BOOTP_BOOTFILESIZE
  50
  51 /*
  52  * SDRAM: 1 bank, min 32, max 128 MB
  53  * Initialized before u-boot gets started.
  54  */
  55 #define PHYS_SDRAM                                      ATMEL_BASE_CS1 /* 0x20000000 */
  56 #define PHYS_SDRAM_SIZE                         0x02000000     /* 32 MByte */
  57
  58 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM
  59 #define CONFIG_SYS_SDRAM_SIZE           PHYS_SDRAM_SIZE
  60
  61 #define CONFIG_SYS_MEMTEST_START        (CONFIG_SYS_SDRAM_BASE + 0x00100000)
  62 #define CONFIG_SYS_MEMTEST_END          (CONFIG_SYS_SDRAM_BASE + 0x01E00000)
  63 #define CONFIG_SYS_LOAD_ADDR            (CONFIG_SYS_SDRAM_BASE + 0x00100000)
  64
  65 /*
  66  * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM,
  67  * leaving the correct space for initial global data structure above
  68  * that address while providing maximum stack area below.
  69  */
  70 #define CONFIG_SYS_INIT_SP_ADDR \
  71         (ATMEL_BASE_SRAM0 + 16 * 1024 - GENERATED_GBL_DATA_SIZE)
  72
  73 /* NAND flash */
  74 #ifdef CONFIG_CMD_NAND
  75 # define CONFIG_SYS_MAX_NAND_DEVICE             1
  76 # define CONFIG_SYS_NAND_BASE                   ATMEL_BASE_CS3 /* 0x40000000 */
  77 # define CONFIG_SYS_NAND_DBW_8
  78 # define CONFIG_SYS_NAND_MASK_ALE               (1 << 21)
  79 # define CONFIG_SYS_NAND_MASK_CLE               (1 << 22)
  80 # define CONFIG_SYS_NAND_ENABLE_PIN             GPIO_PIN_PD(15)
  81 # define CONFIG_SYS_NAND_READY_PIN              GPIO_PIN_PA(22)
  82 #endif
  83
  84 /* Ethernet */
  85 #define CONFIG_MACB
  86 #define CONFIG_RMII
  87 #define CONFIG_NET_RETRY_COUNT                  20
  88 #undef CONFIG_RESET_PHY_R
  89
  90 /* hw-controller addresses */
  91 #define CONFIG_ET1100_BASE              0x70000000
  92
  93 #ifdef CONFIG_SYS_USE_DATAFLASH
  94
  95 /* bootstrap + u-boot + env in dataflash on CS0 */
  96
  97 #elif CONFIG_SYS_USE_NANDFLASH
  98
  99 /* bootstrap + u-boot + env + linux in nandflash */
 100
 101 #endif
 102
 103 #define CONFIG_SYS_CBSIZE               512
 104
 105 /*
 106  * Size of malloc() pool
 107  */
 108 #define CONFIG_SYS_MALLOC_LEN           ROUND(3 * CONFIG_ENV_SIZE + \
 109                                         128*1024, 0x1000)
 110
 111 #endif