include/configs/mgcoge.h

   1 /*
   2  * (C) Copyright 2007
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27 /*
  28  * High Level Configuration Options
  29  * (easy to change)
  30  */
  31
  32 #define CONFIG_MPC8247          1
  33 #define CONFIG_MPC8272_FAMILY   1
  34 #define CONFIG_MGCOGE           1
  35 #define CONFIG_HOSTNAME         mgcoge
  36
  37 #define CONFIG_CPM2             1       /* Has a CPM2 */
  38
  39 /* include common defines/options for all Keymile boards */
  40 #include "keymile-common.h"
  41
  42 /*
  43  * Select serial console configuration
  44  *
  45  * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
  46  * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
  47  * for SCC).
  48  */
  49 #define CONFIG_CONS_ON_SMC              /* Console is on SMC         */
  50 #undef  CONFIG_CONS_ON_SCC              /* It's not on SCC           */
  51 #undef  CONFIG_CONS_NONE                /* It's not on external UART */
  52 #define CONFIG_CONS_INDEX       2       /* SMC2 is used for console  */
  53 #define CONFIG_SYS_SMC_RXBUFLEN 128
  54 #define CONFIG_SYS_MAXIDLE      10
  55
  56 /*
  57  * Select ethernet configuration
  58  *
  59  * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected,
  60  * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for
  61  * SCC, 1-3 for FCC)
  62  *
  63  * If CONFIG_ETHER_NONE is defined, then either the ethernet routines
  64  * must be defined elsewhere (as for the console), or CONFIG_CMD_NET
  65  * must be unset.
  66  */
  67 #define CONFIG_ETHER_ON_SCC             /* Ethernet is on SCC */
  68 #undef  CONFIG_ETHER_ON_FCC             /* Ethernet is not on FCC     */
  69 #undef  CONFIG_ETHER_NONE               /* No external Ethernet   */
  70 #define CONFIG_NET_MULTI        1
  71
  72 #define CONFIG_ETHER_INDEX      4
  73 #define CONFIG_SYS_SCC_TOUT_LOOP        10000000
  74
  75 # define CONFIG_SYS_CMXSCR_VALUE        (CMXSCR_RS4CS_CLK7 | CMXSCR_TS4CS_CLK8)
  76
  77 #ifndef CONFIG_8260_CLKIN
  78 #define CONFIG_8260_CLKIN       66000000        /* in Hz */
  79 #endif
  80
  81 #define BOOTFLASH_START FE000000
  82 #define CONFIG_PRAM     512     /* protected RAM [KBytes] */
  83
  84 #define MTDIDS_DEFAULT          "nor0=boot,nor1=app"
  85 #define MTDPARTS_DEFAULT        \
  86         "mtdparts=boot:384k(u-boot),128k(env),128k(envred),3456k(free);" \
  87         "app:3m(esw0),10m(rootfs0),3m(esw1),10m(rootfs1),1m(var),5m(cfg)"
  88
  89 #ifndef CONFIG_KM_DEF_ENV               /* if not set by keymile-common.h */
  90 #define CONFIG_KM_DEF_ENV "km-common=empty\0"
  91 #endif
  92 /*
  93  * Default environment settings
  94  */
  95 #define CONFIG_EXTRA_ENV_SETTINGS       \
  96         CONFIG_KM_DEF_ENV                                               \
  97         "rootpath=/opt/eldk/ppc_82xx\0"                                 \
  98         "addcon=setenv bootargs ${bootargs} "                           \
  99                 "console=ttyCPM0,${baudrate}\0"                         \
 100         "mtdids=nor0=boot,nor1=app \0"                                  \
 101         "mtdparts=mtdparts=boot:384k(u-boot),128k(env),128k(envred),"   \
 102                 "3456k(free);app:3m(esw0),10m(rootfs0),3m(esw1),"       \
 103                 "10m(rootfs1),1m(var),5m(cfg) \0"                       \
 104         "partition=nor1,5 \0"                                           \
 105         "new_env=prot off FE060000 FE09FFFF; era FE060000 FE09FFFF \0"  \
 106         "EEprom_ivm=pca9544a:70:4 \0"                                   \
 107         "mtdparts=" MK_STR(MTDPARTS_DEFAULT) "\0"                               \
 108         ""
 109
 110 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 111 #define CONFIG_SYS_FLASH_BASE           0xFE000000
 112 #define CONFIG_SYS_FLASH_SIZE           32
 113 #define CONFIG_SYS_FLASH_CFI
 114 #define CONFIG_FLASH_CFI_DRIVER
 115 #define CONFIG_SYS_MAX_FLASH_BANKS      2       /* max num of flash banks       */
 116 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max num of sects on one chip */
 117
 118 #define CONFIG_SYS_FLASH_BASE_1 0x50000000
 119 #define CONFIG_SYS_FLASH_SIZE_1 64
 120
 121 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_1 }
 122
 123 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE
 124 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 125 #define CONFIG_SYS_RAMBOOT
 126 #endif
 127
 128 #define CONFIG_SYS_MONITOR_LEN          (384 << 10)     /* Reserve 384KB for Monitor */
 129
 130 #define CONFIG_ENV_IS_IN_FLASH
 131
 132 #ifdef CONFIG_ENV_IS_IN_FLASH
 133 #define CONFIG_ENV_SECT_SIZE    0x20000
 134 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 135 #define CONFIG_ENV_OFFSET       CONFIG_SYS_MONITOR_LEN
 136
 137 /* Address and size of Redundant Environment Sector     */
 138 #define CONFIG_ENV_OFFSET_REDUND        (CONFIG_ENV_OFFSET + CONFIG_ENV_SECT_SIZE)
 139 #define CONFIG_ENV_SIZE_REDUND          (CONFIG_ENV_SIZE)
 140 #endif /* CONFIG_ENV_IS_IN_FLASH */
 141 #define CONFIG_ENV_BUFFER_PRINT         1
 142
 143 /* enable I2C and select the hardware/software driver */
 144 #undef  CONFIG_HARD_I2C                 /* I2C with hardware support    */
 145 #define CONFIG_SOFT_I2C         1       /* I2C bit-banged               */
 146 #define CONFIG_SYS_I2C_SPEED            50000   /* I2C speed and slave address  */
 147 #define CONFIG_SYS_I2C_SLAVE            0x7F
 148
 149 /*
 150  * Software (bit-bang) I2C driver configuration
 151  */
 152
 153 #define I2C_PORT        3               /* Port A=0, B=1, C=2, D=3 */
 154 #define I2C_ACTIVE      (iop->pdir |=  0x00010000)
 155 #define I2C_TRISTATE    (iop->pdir &= ~0x00010000)
 156 #define I2C_READ        ((iop->pdat & 0x00010000) != 0)
 157 #define I2C_SDA(bit)    if(bit) iop->pdat |=  0x00010000; \
 158                         else    iop->pdat &= ~0x00010000
 159 #define I2C_SCL(bit)    if(bit) iop->pdat |=  0x00020000; \
 160                         else    iop->pdat &= ~0x00020000
 161 #define I2C_DELAY       udelay(5)       /* 1/4 I2C clock duration */
 162
 163 /* I2C SYSMON (LM75, AD7414 is almost compatible)                       */
 164 #define CONFIG_DTT_LM75         1       /* ON Semi's LM75               */
 165 #define CONFIG_DTT_SENSORS      {0}     /* Sensor addresses             */
 166 #define CONFIG_SYS_DTT_MAX_TEMP 70
 167 #define CONFIG_SYS_DTT_LOW_TEMP -30
 168 #define CONFIG_SYS_DTT_HYSTERESIS       3
 169 #define CONFIG_SYS_DTT_BUS_NUM          (CONFIG_SYS_MAX_I2C_BUS)
 170
 171 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
 172
 173 #define CONFIG_SYS_IMMR         0xF0000000
 174
 175 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_IMMR
 176 #define CONFIG_SYS_INIT_RAM_END 0x2000  /* End of used area in DPRAM    */
 177 #define CONFIG_SYS_GBL_DATA_SIZE        128     /* size in bytes reserved for initial data */
 178 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 179 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 180
 181 /* Hard reset configuration word */
 182 #define CONFIG_SYS_HRCW_MASTER          0x0604b211
 183
 184 /* No slaves */
 185 #define CONFIG_SYS_HRCW_SLAVE1          0
 186 #define CONFIG_SYS_HRCW_SLAVE2          0
 187 #define CONFIG_SYS_HRCW_SLAVE3          0
 188 #define CONFIG_SYS_HRCW_SLAVE4          0
 189 #define CONFIG_SYS_HRCW_SLAVE5          0
 190 #define CONFIG_SYS_HRCW_SLAVE6          0
 191 #define CONFIG_SYS_HRCW_SLAVE7          0
 192
 193 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 194 #define BOOTFLAG_WARM           0x02    /* Software reboot                  */
 195
 196 #define CONFIG_SYS_MALLOC_LEN           (4096 << 10)    /* Reserve 4 MB for malloc()    */
 197 #define CONFIG_SYS_BOOTMAPSZ            (8 << 20)       /* Initial Memory map for Linux */
 198
 199 #define CONFIG_SYS_CACHELINE_SIZE       32      /* For MPC8260 CPUs */
 200 #if defined(CONFIG_CMD_KGDB)
 201 #  define CONFIG_SYS_CACHELINE_SHIFT    5       /* log base 2 of the above value */
 202 #endif
 203
 204 #define CONFIG_SYS_HID0_INIT            0
 205 #define CONFIG_SYS_HID0_FINAL           (HID0_ICE | HID0_IFEM | HID0_ABE)
 206
 207 #define CONFIG_SYS_HID2         0
 208
 209 #define CONFIG_SYS_SIUMCR               0x4020c200
 210 #define CONFIG_SYS_SYPCR                0xFFFFFFC3
 211 #define CONFIG_SYS_BCR                  0x10000000
 212 #define CONFIG_SYS_SCCR         (SCCR_PCI_MODE | SCCR_PCI_MODCK)
 213
 214 /*-----------------------------------------------------------------------
 215  * RMR - Reset Mode Register                                     5-5
 216  *-----------------------------------------------------------------------
 217  * turn on Checkstop Reset Enable
 218  */
 219 #define CONFIG_SYS_RMR         0
 220
 221 /*-----------------------------------------------------------------------
 222  * TMCNTSC - Time Counter Status and Control                     4-40
 223  *-----------------------------------------------------------------------
 224  * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
 225  * and enable Time Counter
 226  */
 227 #define CONFIG_SYS_TMCNTSC     (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
 228
 229 /*-----------------------------------------------------------------------
 230  * PISCR - Periodic Interrupt Status and Control                 4-42
 231  *-----------------------------------------------------------------------
 232  * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
 233  * Periodic timer
 234  */
 235 #define CONFIG_SYS_PISCR       (PISCR_PS|PISCR_PTF|PISCR_PTE)
 236
 237 /*-----------------------------------------------------------------------
 238  * RCCR - RISC Controller Configuration                         13-7
 239  *-----------------------------------------------------------------------
 240  */
 241 #define CONFIG_SYS_RCCR        0
 242
 243 /*
 244  * Init Memory Controller:
 245  *
 246  * Bank Bus     Machine PortSz  Device
 247  * ---- ---     ------- ------  ------
 248  *  0   60x     GPCM     8 bit  FLASH
 249  *  1   60x     SDRAM   32 bit  SDRAM
 250  *  3   60x     GPCM     8 bit  GPIO/PIGGY
 251  *  5   60x     GPCM    16 bit  CFG-Flash
 252  *
 253  */
 254 /* Bank 0 - FLASH
 255  */
 256 #define CONFIG_SYS_BR0_PRELIM  ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK)    |\
 257                          BRx_PS_8                       |\
 258                          BRx_MS_GPCM_P                  |\
 259                          BRx_V)
 260
 261 #define CONFIG_SYS_OR0_PRELIM  (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE)        |\
 262                          ORxG_CSNT                      |\
 263                          ORxG_ACS_DIV2                  |\
 264                          ORxG_SCY_5_CLK                 |\
 265                          ORxG_TRLX )
 266
 267
 268 /* Bank 1 - 60x bus SDRAM
 269  */
 270 #define SDRAM_MAX_SIZE  0x08000000      /* max. 128 MB          */
 271 #define CONFIG_SYS_GLOBAL_SDRAM_LIMIT   (256 << 20)     /* less than 256 MB */
 272
 273 #define CONFIG_SYS_MPTPR       0x1800
 274
 275 /*-----------------------------------------------------------------------------
 276  * Address for Mode Register Set (MRS) command
 277  *-----------------------------------------------------------------------------
 278  */
 279 #define CONFIG_SYS_MRS_OFFS     0x00000110
 280 #define CONFIG_SYS_PSRT        0x0e
 281
 282 #define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK)  |\
 283                          BRx_PS_64                      |\
 284                          BRx_MS_SDRAM_P                 |\
 285                          BRx_V)
 286
 287 #define CONFIG_SYS_OR1_PRELIM   CONFIG_SYS_OR1
 288
 289 /* SDRAM initialization values
 290 */
 291
 292 #define CONFIG_SYS_OR1    ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
 293                          ORxS_BPD_8                     |\
 294                          ORxS_ROWST_PBI0_A7             |\
 295                          ORxS_NUMR_13)
 296
 297 #define CONFIG_SYS_PSDMR  (PSDMR_SDAM_A14_IS_A5 |\
 298                          PSDMR_BSMA_A14_A16           |\
 299                          PSDMR_SDA10_PBI0_A9            |\
 300                          PSDMR_RFRC_5_CLK               |\
 301                          PSDMR_PRETOACT_2W              |\
 302                          PSDMR_ACTTORW_2W               |\
 303                          PSDMR_LDOTOPRE_1C              |\
 304                          PSDMR_WRC_1C                   |\
 305                          PSDMR_CL_2)
 306
 307 /* GPIO/PIGGY on CS3 initialization values
 308 */
 309 #define CONFIG_SYS_PIGGY_BASE   0x30000000
 310 #define CONFIG_SYS_PIGGY_SIZE   128
 311
 312 #define CONFIG_SYS_BR3_PRELIM   ((CONFIG_SYS_PIGGY_BASE & BRx_BA_MSK) |\
 313                          BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 314
 315 #define CONFIG_SYS_OR3_PRELIM   (MEG_TO_AM(CONFIG_SYS_PIGGY_SIZE) |\
 316                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 317                          ORxG_SCY_3_CLK | ORxG_TRLX )
 318
 319 /* Board FPGA on CS4 initialization values
 320 */
 321 #define CONFIG_SYS_FPGA_BASE    0x40000000
 322 #define CONFIG_SYS_FPGA_SIZE    1 /*1KB*/
 323
 324 #define CONFIG_SYS_BR4_PRELIM ((CONFIG_SYS_FPGA_BASE & BRx_BA_MSK) |\
 325                         BRx_PS_8 | BRx_MS_GPCM_P | BRx_V)
 326
 327 #define CONFIG_SYS_OR4_PRELIM (P2SZ_TO_AM(CONFIG_SYS_FPGA_SIZE << 10) |\
 328                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 329                          ORxG_SCY_3_CLK | ORxG_TRLX )
 330
 331 /* CFG-Flash on CS5 initialization values
 332 */
 333 #define CONFIG_SYS_BR5_PRELIM   ((CONFIG_SYS_FLASH_BASE_1 & BRx_BA_MSK) |\
 334                          BRx_PS_16 | BRx_MS_GPCM_P | BRx_V)
 335
 336 #define CONFIG_SYS_OR5_PRELIM   (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE_1) |\
 337                          ORxG_CSNT | ORxG_ACS_DIV2 |\
 338                          ORxG_SCY_5_CLK | ORxG_TRLX )
 339
 340 #define CONFIG_SYS_RESET_ADDRESS 0xFDFFFFFC     /* "bad" address                */
 341
 342 /* pass open firmware flat tree */
 343 #define CONFIG_FIT              1
 344 #define CONFIG_OF_LIBFDT        1
 345 #define CONFIG_OF_BOARD_SETUP   1
 346
 347 #define OF_CPU                  "PowerPC,8247@0"
 348 #define OF_SOC                  "soc@f0000000"
 349 #define OF_TBCLK                (bd->bi_busfreq / 4)
 350 #define OF_STDOUT_PATH          "/soc/cpm/serial@11a90"
 351
 352 #endif /* __CONFIG_H */