include/configs/mpc5121ads.h

   1 /*
   2  * (C) Copyright 2007-2009 DENX Software Engineering
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 /*
  24  * MPC5121ADS board configuration file
  25  */
  26
  27 #ifndef __CONFIG_H
  28 #define __CONFIG_H
  29
  30 #define CONFIG_MPC5121ADS 1
  31 /*
  32  * Memory map for the MPC5121ADS board:
  33  *
  34  * 0x0000_0000 - 0x0FFF_FFFF    DDR RAM (256 MB)
  35  * 0x3000_0000 - 0x3001_FFFF    SRAM (128 KB)
  36  * 0x8000_0000 - 0x803F_FFFF    IMMR (4 MB)
  37  * 0x8200_0000 - 0x8200_001F    CPLD (32 B)
  38  * 0x8400_0000 - 0x82FF_FFFF    PCI I/O space (16 MB)
  39  * 0xA000_0000 - 0xAFFF_FFFF    PCI memory space (256 MB)
  40  * 0xB000_0000 - 0xBFFF_FFFF    PCI memory mapped I/O space (256 MB)
  41  * 0xFC00_0000 - 0xFFFF_FFFF    NOR Boot FLASH (64 MB)
  42  */
  43
  44 /*
  45  * High Level Configuration Options
  46  */
  47 #define CONFIG_E300             1       /* E300 Family */
  48 #define CONFIG_MPC512X          1       /* MPC512X family */
  49 #define CONFIG_FSL_DIU_FB       1       /* FSL DIU */
  50 #undef CONFIG_FSL_DIU_LOGO_BMP          /* Don't include FSL DIU binary bmp */
  51
  52 /* video */
  53 #undef CONFIG_VIDEO
  54
  55 #if defined(CONFIG_VIDEO)
  56 #define CONFIG_CFB_CONSOLE
  57 #define CONFIG_VGA_AS_SINGLE_DEVICE
  58 #endif
  59
  60 /* CONFIG_PCI is defined at config time */
  61
  62 #ifdef CONFIG_MPC5121ADS_REV2
  63 #define CONFIG_SYS_MPC512X_CLKIN        66000000        /* in Hz */
  64 #else
  65 #define CONFIG_SYS_MPC512X_CLKIN        33333333        /* in Hz */
  66 #define CONFIG_PCI
  67 #endif
  68
  69 #define CONFIG_BOARD_EARLY_INIT_F               /* call board_early_init_f() */
  70 #define CONFIG_MISC_INIT_R
  71
  72 #define CONFIG_SYS_IMMR         0x80000000
  73 #define CONFIG_SYS_DIU_ADDR             (CONFIG_SYS_IMMR+0x2100)
  74
  75 #define CONFIG_SYS_MEMTEST_START        0x00200000      /* memtest region */
  76 #define CONFIG_SYS_MEMTEST_END          0x00400000
  77
  78 /*
  79  * DDR Setup - manually set all parameters as there's no SPD etc.
  80  */
  81 #ifdef CONFIG_MPC5121ADS_REV2
  82 #define CONFIG_SYS_DDR_SIZE             256             /* MB */
  83 #else
  84 #define CONFIG_SYS_DDR_SIZE             512             /* MB */
  85 #endif
  86 #define CONFIG_SYS_DDR_BASE             0x00000000      /* DDR is system memory*/
  87 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_BASE
  88 #define CONFIG_SYS_MAX_RAM_SIZE         0x20000000
  89
  90 #define CONFIG_SYS_IOCTRL_MUX_DDR       0x00000036
  91
  92 /* DDR Controller Configuration
  93  *
  94  * SYS_CFG:
  95  *      [31:31] MDDRC Soft Reset:       Diabled
  96  *      [30:30] DRAM CKE pin:           Enabled
  97  *      [29:29] DRAM CLK:               Enabled
  98  *      [28:28] Command Mode:           Enabled (For initialization only)
  99  *      [27:25] DRAM Row Select:        dram_row[15:0] = magenta_address[25:10]
 100  *      [24:21] DRAM Bank Select:       dram_bank[1:0] = magenta_address[11:10]
 101  *      [20:19] Read Test:              DON'T USE
 102  *      [18:18] Self Refresh:           Enabled
 103  *      [17:17] 16bit Mode:             Disabled
 104  *      [16:13] Ready Delay:            2
 105  *      [12:12] Half DQS Delay:         Disabled
 106  *      [11:11] Quarter DQS Delay:      Disabled
 107  *      [10:08] Write Delay:            2
 108  *      [07:07] Early ODT:              Disabled
 109  *      [06:06] On DIE Termination:     Disabled
 110  *      [05:05] FIFO Overflow Clear:    DON'T USE here
 111  *      [04:04] FIFO Underflow Clear:   DON'T USE here
 112  *      [03:03] FIFO Overflow Pending:  DON'T USE here
 113  *      [02:02] FIFO Underlfow Pending: DON'T USE here
 114  *      [01:01] FIFO Overlfow Enabled:  Enabled
 115  *      [00:00] FIFO Underflow Enabled: Enabled
 116  * TIME_CFG0
 117  *      [31:16] DRAM Refresh Time:      0 CSB clocks
 118  *      [15:8]  DRAM Command Time:      0 CSB clocks
 119  *      [07:00] DRAM Precharge Time:    0 CSB clocks
 120  * TIME_CFG1
 121  *      [31:26] DRAM tRFC:
 122  *      [25:21] DRAM tWR1:
 123  *      [20:17] DRAM tWRT1:
 124  *      [16:11] DRAM tDRR:
 125  *      [10:05] DRAM tRC:
 126  *      [04:00] DRAM tRAS:
 127  * TIME_CFG2
 128  *      [31:28] DRAM tRCD:
 129  *      [27:23] DRAM tFAW:
 130  *      [22:19] DRAM tRTW1:
 131  *      [18:15] DRAM tCCD:
 132  *      [14:10] DRAM tRTP:
 133  *      [09:05] DRAM tRP:
 134  *      [04:00] DRAM tRPA
 135  */
 136 #ifdef CONFIG_MPC5121ADS_REV2
 137 #define CONFIG_SYS_MDDRC_SYS_CFG        0xE8604A00
 138 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x54EC1168
 139 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x35210864
 140 #else
 141 #define CONFIG_SYS_MDDRC_SYS_CFG        0xEA804A00
 142 #define CONFIG_SYS_MDDRC_TIME_CFG1      0x68EC1168
 143 #define CONFIG_SYS_MDDRC_TIME_CFG2      0x34310864
 144 #endif
 145 #define CONFIG_SYS_MDDRC_TIME_CFG0      0x06183D2E
 146
 147 #define CONFIG_SYS_MDDRC_SYS_CFG_ELPIDA         0xEA802B00
 148 #define CONFIG_SYS_MDDRC_TIME_CFG1_ELPIDA       0x690e1189
 149 #define CONFIG_SYS_MDDRC_TIME_CFG2_ELPIDA       0x35310864
 150
 151 #define CONFIG_SYS_DDRCMD_NOP           0x01380000
 152 #define CONFIG_SYS_DDRCMD_PCHG_ALL      0x01100400
 153 #define CONFIG_SYS_DDRCMD_EM2           0x01020000
 154 #define CONFIG_SYS_DDRCMD_EM3           0x01030000
 155 #define CONFIG_SYS_DDRCMD_EN_DLL        0x01010000
 156 #define CONFIG_SYS_DDRCMD_RFSH          0x01080000
 157
 158 #define DDRCMD_EMR_OCD(pr, ohm) ( \
 159         (1 << 24)          | /* MDDRC Command Request   */ \
 160         (1 << 16)          | /* MODE Reg BA[2:0]        */ \
 161         (0 << 12)          | /* Outputs 0=Enabled       */ \
 162         (0 << 11)          | /* RDQS                    */ \
 163         (1 << 10)          | /* DQS#                    */ \
 164         (pr <<  7)         | /* OCD prog 7=deflt,0=exit */ \
 165                     /* ODT Rtt[1:0] 0=0,1=75,2=150,3=50 */ \
 166         ((ohm & 0x2) <<  5)| /* Rtt1                    */ \
 167         (0 <<  3)          | /* additive posted CAS#    */ \
 168         ((ohm & 0x1) <<  2)| /* Rtt0                    */ \
 169         (0 <<  0)          | /* Output Drive Strength   */ \
 170         (0 <<  0))           /* DLL Enable 0=Normal     */
 171
 172 #define CONFIG_SYS_DDRCMD_OCD_DEFAULT   DDRCMD_EMR_OCD(7, 0)
 173 #define CONFIG_SYS_ELPIDA_OCD_EXIT      DDRCMD_EMR_OCD(0, 0)
 174
 175 #define DDRCMD_MODE_REG(cas, wr) ( \
 176         (1 << 24)    | /* MDDRC Command Request                 */ \
 177         (0 << 16)    | /* MODE Reg BA[2:0]                      */ \
 178         ((wr-1) << 9)| /* Write Recovery                        */ \
 179         (cas << 4)   | /* CAS                                   */ \
 180         (0 << 3)     | /* Burst Type:0=Sequential,1=Interleaved */ \
 181         (2 << 0))      /* 4 or 8 Burst Length:0x2=4 0x3=8       */
 182
 183 #define CONFIG_SYS_MICRON_INIT_DEV_OP   DDRCMD_MODE_REG(3, 3)
 184 #define CONFIG_SYS_ELPIDA_INIT_DEV_OP   DDRCMD_MODE_REG(4, 4)
 185 #define CONFIG_SYS_ELPIDA_RES_DLL       (DDRCMD_MODE_REG(4, 4) | (1 << 8))
 186
 187 /* DDR Priority Manager Configuration */
 188 #define CONFIG_SYS_MDDRCGRP_PM_CFG1     0x00077777
 189 #define CONFIG_SYS_MDDRCGRP_PM_CFG2     0x00000000
 190 #define CONFIG_SYS_MDDRCGRP_HIPRIO_CFG  0x00000001
 191 #define CONFIG_SYS_MDDRCGRP_LUT0_MU     0xFFEEDDCC
 192 #define CONFIG_SYS_MDDRCGRP_LUT0_ML     0xBBAAAAAA
 193 #define CONFIG_SYS_MDDRCGRP_LUT1_MU     0x66666666
 194 #define CONFIG_SYS_MDDRCGRP_LUT1_ML     0x55555555
 195 #define CONFIG_SYS_MDDRCGRP_LUT2_MU     0x44444444
 196 #define CONFIG_SYS_MDDRCGRP_LUT2_ML     0x44444444
 197 #define CONFIG_SYS_MDDRCGRP_LUT3_MU     0x55555555
 198 #define CONFIG_SYS_MDDRCGRP_LUT3_ML     0x55555558
 199 #define CONFIG_SYS_MDDRCGRP_LUT4_MU     0x11111111
 200 #define CONFIG_SYS_MDDRCGRP_LUT4_ML     0x11111122
 201 #define CONFIG_SYS_MDDRCGRP_LUT0_AU     0xaaaaaaaa
 202 #define CONFIG_SYS_MDDRCGRP_LUT0_AL     0xaaaaaaaa
 203 #define CONFIG_SYS_MDDRCGRP_LUT1_AU     0x66666666
 204 #define CONFIG_SYS_MDDRCGRP_LUT1_AL     0x66666666
 205 #define CONFIG_SYS_MDDRCGRP_LUT2_AU     0x11111111
 206 #define CONFIG_SYS_MDDRCGRP_LUT2_AL     0x11111111
 207 #define CONFIG_SYS_MDDRCGRP_LUT3_AU     0x11111111
 208 #define CONFIG_SYS_MDDRCGRP_LUT3_AL     0x11111111
 209 #define CONFIG_SYS_MDDRCGRP_LUT4_AU     0x11111111
 210 #define CONFIG_SYS_MDDRCGRP_LUT4_AL     0x11111111
 211
 212 /*
 213  * NOR FLASH on the Local Bus
 214  */
 215 #undef CONFIG_BKUP_FLASH
 216 #define CONFIG_SYS_FLASH_CFI                            /* use the Common Flash Interface */
 217 #define CONFIG_FLASH_CFI_DRIVER                 /* use the CFI driver */
 218 #ifdef CONFIG_BKUP_FLASH
 219 #define CONFIG_SYS_FLASH_BASE           0xFF800000      /* start of FLASH   */
 220 #define CONFIG_SYS_FLASH_SIZE           0x00800000      /* max flash size in bytes */
 221 #else
 222 #define CONFIG_SYS_FLASH_BASE           0xFC000000      /* start of FLASH   */
 223 #define CONFIG_SYS_FLASH_SIZE           0x04000000      /* max flash size in bytes */
 224 #endif
 225 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 226 #define CONFIG_SYS_MAX_FLASH_BANKS      1               /* number of banks */
 227 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE}
 228 #define CONFIG_SYS_MAX_FLASH_SECT       256             /* max sectors per device */
 229
 230 #undef CONFIG_SYS_FLASH_CHECKSUM
 231
 232 /*
 233  * NAND FLASH
 234  * drivers/mtd/nand/mpc5121_nfc.c (rev 2 silicon only)
 235  */
 236 #define CONFIG_CMD_NAND                                 /* enable NAND support */
 237 #define CONFIG_JFFS2_NAND                               /* with JFFS2 on it */
 238 #define CONFIG_NAND_MPC5121_NFC
 239 #define CONFIG_SYS_NAND_BASE            0x40000000
 240
 241 #define CONFIG_SYS_MAX_NAND_DEVICE      2
 242 #define NAND_MAX_CHIPS                  CONFIG_SYS_MAX_NAND_DEVICE
 243 #define CONFIG_SYS_NAND_SELECT_DEVICE   /* driver supports mutipl. chips */
 244
 245 /*
 246  * Configuration parameters for MPC5121 NAND driver
 247  */
 248 #define CONFIG_FSL_NFC_WIDTH 1
 249 #define CONFIG_FSL_NFC_WRITE_SIZE 2048
 250 #define CONFIG_FSL_NFC_SPARE_SIZE 64
 251 #define CONFIG_FSL_NFC_CHIPS CONFIG_SYS_MAX_NAND_DEVICE
 252
 253 /*
 254  * CPLD registers area is really only 32 bytes in size, but the smallest possible LP
 255  * window is 64KB
 256  */
 257 #define CONFIG_SYS_CPLD_BASE            0x82000000
 258 #define CONFIG_SYS_CPLD_SIZE            0x00010000      /* 64 KB */
 259
 260 #define CONFIG_SYS_SRAM_BASE            0x30000000
 261 #define CONFIG_SYS_SRAM_SIZE            0x00020000      /* 128 KB */
 262
 263 #define CONFIG_SYS_CS0_CFG              0x05059310      /* ALE active low, data size 4bytes */
 264 #define CONFIG_SYS_CS2_CFG              0x05059010      /* ALE active low, data size 1byte */
 265 #define CONFIG_SYS_CS_ALETIMING 0x00000005      /* Use alternative CS timing for CS0 and CS2 */
 266
 267 /* Use SRAM for initial stack */
 268 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_SRAM_BASE            /* Initial RAM address */
 269 #define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_SRAM_SIZE            /* End of used area in RAM */
 270
 271 #define CONFIG_SYS_GBL_DATA_SIZE        0x100                   /* num bytes initial data */
 272 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
 273 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 274
 275 #define CONFIG_SYS_MONITOR_BASE TEXT_BASE               /* Start of monitor */
 276 #define CONFIG_SYS_MONITOR_LEN          (512 * 1024)            /* Reserve 512 kB for Mon */
 277 #ifdef  CONFIG_FSL_DIU_FB
 278 #define CONFIG_SYS_MALLOC_LEN           (6 * 1024 * 1024)       /* Reserved for malloc */
 279 #else
 280 #define CONFIG_SYS_MALLOC_LEN           (512 * 1024)
 281 #endif
 282
 283 /*
 284  * Serial Port
 285  */
 286 #define CONFIG_CONS_INDEX     1
 287 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 288
 289 /*
 290  * Serial console configuration
 291  */
 292 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 */
 293 #if CONFIG_PSC_CONSOLE != 3
 294 #error CONFIG_PSC_CONSOLE must be 3
 295 #endif
 296 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
 297 #define CONFIG_SYS_BAUDRATE_TABLE  \
 298         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 299
 300 #define CONSOLE_FIFO_TX_SIZE    FIFOC_PSC3_TX_SIZE
 301 #define CONSOLE_FIFO_TX_ADDR    FIFOC_PSC3_TX_ADDR
 302 #define CONSOLE_FIFO_RX_SIZE    FIFOC_PSC3_RX_SIZE
 303 #define CONSOLE_FIFO_RX_ADDR    FIFOC_PSC3_RX_ADDR
 304
 305 #define CONFIG_CMDLINE_EDITING  1       /* add command line history     */
 306 /* Use the HUSH parser */
 307 #define CONFIG_SYS_HUSH_PARSER
 308 #ifdef  CONFIG_SYS_HUSH_PARSER
 309 #define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
 310 #endif
 311
 312 /*
 313  * PCI
 314  */
 315 #ifdef CONFIG_PCI
 316
 317 /*
 318  * General PCI
 319  */
 320 #define CONFIG_SYS_PCI_MEM_BASE 0xA0000000
 321 #define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
 322 #define CONFIG_SYS_PCI_MEM_SIZE 0x10000000      /* 256M */
 323 #define CONFIG_SYS_PCI_MMIO_BASE        (CONFIG_SYS_PCI_MEM_BASE + CONFIG_SYS_PCI_MEM_SIZE)
 324 #define CONFIG_SYS_PCI_MMIO_PHYS        CONFIG_SYS_PCI_MMIO_BASE
 325 #define CONFIG_SYS_PCI_MMIO_SIZE        0x10000000      /* 256M */
 326 #define CONFIG_SYS_PCI_IO_BASE          0x00000000
 327 #define CONFIG_SYS_PCI_IO_PHYS          0x84000000
 328 #define CONFIG_SYS_PCI_IO_SIZE          0x01000000      /* 16M */
 329
 330
 331 #define CONFIG_PCI_PNP                  /* do pci plug-and-play */
 332
 333 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */
 334
 335 #endif
 336
 337 /* I2C */
 338 #define CONFIG_HARD_I2C                 /* I2C with hardware support */
 339 #undef CONFIG_SOFT_I2C                  /* so disable bit-banged I2C */
 340 #define CONFIG_I2C_MULTI_BUS
 341 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address */
 342 #define CONFIG_SYS_I2C_SLAVE            0x7F
 343 #if 0
 344 #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}}      /* Don't probe these addrs */
 345 #endif
 346
 347 /*
 348  * IIM - IC Identification Module
 349  */
 350 #undef CONFIG_IIM
 351
 352 /*
 353  * EEPROM configuration
 354  */
 355 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN          2       /* 16-bit EEPROM address */
 356 #define CONFIG_SYS_I2C_EEPROM_ADDR              0x50    /* Atmel: AT24C32A-10TQ-2.7 */
 357 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS   10      /* 10ms of delay */
 358 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS       5       /* 32-Byte Page Write Mode */
 359
 360 /*
 361  * Ethernet configuration
 362  */
 363 #define CONFIG_MPC512x_FEC      1
 364 #define CONFIG_NET_MULTI
 365 #define CONFIG_PHY_ADDR         0x1
 366 #define CONFIG_MII              1       /* MII PHY management           */
 367 #define CONFIG_FEC_AN_TIMEOUT   1
 368 #define CONFIG_HAS_ETH0
 369
 370 /*
 371  * Configure on-board RTC
 372  */
 373 #define CONFIG_RTC_M41T62                       /* use M41T62 rtc via i2 */
 374 #define CONFIG_SYS_I2C_RTC_ADDR         0x68    /* at address 0x68              */
 375
 376 /*
 377  * Environment
 378  */
 379 #define CONFIG_ENV_IS_IN_FLASH  1
 380 /* This has to be a multiple of the Flash sector size */
 381 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
 382 #define CONFIG_ENV_SIZE         0x2000
 383 #ifdef CONFIG_BKUP_FLASH
 384 #define CONFIG_ENV_SECT_SIZE    0x20000 /* one sector (256K) for env */
 385 #else
 386 #define CONFIG_ENV_SECT_SIZE    0x40000 /* one sector (256K) for env */
 387 #endif
 388
 389 /* Address and size of Redundant Environment Sector     */
 390 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR + CONFIG_ENV_SECT_SIZE)
 391 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 392
 393 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download */
 394 #define CONFIG_SYS_LOADS_BAUD_CHANGE    1       /* allow baudrate change */
 395
 396 #include <config_cmd_default.h>
 397
 398 #define CONFIG_CMD_ASKENV
 399 #define CONFIG_CMD_DATE
 400 #define CONFIG_CMD_DHCP
 401 #define CONFIG_CMD_EEPROM
 402 #define CONFIG_CMD_EXT2
 403 #define CONFIG_CMD_I2C
 404 #define CONFIG_CMD_IDE
 405 #define CONFIG_CMD_JFFS2
 406 #define CONFIG_CMD_MII
 407 #define CONFIG_CMD_NFS
 408 #define CONFIG_CMD_PING
 409 #define CONFIG_CMD_REGINFO
 410
 411 #undef CONFIG_CMD_FUSE
 412
 413 #if defined(CONFIG_PCI)
 414 #define CONFIG_CMD_PCI
 415 #endif
 416
 417 /*
 418  * Dynamic MTD partition support
 419  */
 420 #define CONFIG_CMD_MTDPARTS
 421 #define CONFIG_MTD_DEVICE               /* needed for mtdparts commands */
 422 #define CONFIG_FLASH_CFI_MTD
 423 #define MTDIDS_DEFAULT          "nor0=fc000000.flash,nand0=mpc5121.nand"
 424
 425 /*
 426  * NOR flash layout:
 427  *
 428  * FC000000 - FEABFFFF 42.75 MiB        User Data
 429  * FEAC0000 - FFABFFFF  16 MiB          Root File System
 430  * FFAC0000 - FFEBFFFF   4 MiB          Linux Kernel
 431  * FFEC0000 - FFEFFFFF 256 KiB          Device Tree
 432  * FFF00000 - FFFFFFFF   1 MiB          U-Boot (up to 512 KiB) and 2 x * env
 433  *
 434  * NAND flash layout: one big partition
 435  */
 436 #define MTDPARTS_DEFAULT        "mtdparts=fc000000.flash:43776k(user)," \
 437                                                 "16m(rootfs),"          \
 438                                                 "4m(kernel),"           \
 439                                                 "256k(dtb),"            \
 440                                                 "1m(u-boot);"           \
 441                                         "mpc5121.nand:-(data)"
 442
 443
 444 #if defined(CONFIG_CMD_IDE) || defined(CONFIG_CMD_EXT2)
 445 #define CONFIG_DOS_PARTITION
 446 #define CONFIG_MAC_PARTITION
 447 #define CONFIG_ISO_PARTITION
 448 #endif /* defined(CONFIG_CMD_IDE) */
 449
 450 /*
 451  * Watchdog timeout = CONFIG_SYS_WATCHDOG_VALUE * 65536 / IPS clock.
 452  * For example, when IPS is set to 66MHz and CONFIG_SYS_WATCHDOG_VALUE is set
 453  * to 0xFFFF, watchdog timeouts after about 64s. For details refer
 454  * to chapter 36 of the MPC5121e Reference Manual.
 455  */
 456 /* #define CONFIG_WATCHDOG */           /* enable watchdog */
 457 #define CONFIG_SYS_WATCHDOG_VALUE 0xFFFF
 458
 459  /*
 460  * Miscellaneous configurable options
 461  */
 462 #define CONFIG_SYS_LONGHELP                     /* undef to save memory */
 463 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 464 #define CONFIG_SYS_PROMPT       "=> "           /* Monitor Command Prompt */
 465
 466 #ifdef CONFIG_CMD_KGDB
 467         #define CONFIG_SYS_CBSIZE       1024    /* Console I/O Buffer Size */
 468 #else
 469         #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 470 #endif
 471
 472
 473 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
 474 #define CONFIG_SYS_MAXARGS      16              /* max number of command args */
 475 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE       /* Boot Argument Buffer Size */
 476 #define CONFIG_SYS_HZ           1000            /* decrementer freq: 1ms ticks */
 477
 478 /*
 479  * For booting Linux, the board info and command line data
 480  * have to be in the first 8 MB of memory, since this is
 481  * the maximum mapped by the Linux kernel during initialization.
 482  */
 483 #define CONFIG_SYS_BOOTMAPSZ    (8 << 20)       /* Initial Memory map for Linux*/
 484
 485 /* Cache Configuration */
 486 #define CONFIG_SYS_DCACHE_SIZE          32768
 487 #define CONFIG_SYS_CACHELINE_SIZE       32
 488 #ifdef CONFIG_CMD_KGDB
 489 #define CONFIG_SYS_CACHELINE_SHIFT      5       /*log base 2 of the above value*/
 490 #endif
 491
 492 #define CONFIG_SYS_HID0_INIT    0x000000000
 493 #define CONFIG_SYS_HID0_FINAL   (HID0_ENABLE_MACHINE_CHECK | HID0_ICE)
 494 #define CONFIG_SYS_HID2 HID2_HBE
 495
 496 #define CONFIG_HIGH_BATS        1       /* High BATs supported */
 497
 498 /*
 499  * Internal Definitions
 500  *
 501  * Boot Flags
 502  */
 503 #define BOOTFLAG_COLD           0x01    /* Normal Power-On: Boot from FLASH */
 504 #define BOOTFLAG_WARM           0x02    /* Software reboot */
 505
 506 #ifdef CONFIG_CMD_KGDB
 507 #define CONFIG_KGDB_BAUDRATE    230400  /* speed of kgdb serial port */
 508 #define CONFIG_KGDB_SER_INDEX   2       /* which serial port to use */
 509 #endif
 510
 511 /*
 512  * Environment Configuration
 513  */
 514 #define CONFIG_TIMESTAMP
 515
 516 #define CONFIG_HOSTNAME         mpc5121ads
 517 #define CONFIG_BOOTFILE         mpc5121ads/uImage
 518 #define CONFIG_ROOTPATH         /opt/eldk/ppc_6xx
 519
 520 #define CONFIG_LOADADDR         400000  /* default location for tftp and bootm */
 521
 522 #define CONFIG_BOOTDELAY        5       /* -1 disables auto-boot */
 523 #undef  CONFIG_BOOTARGS                 /* the boot command will set bootargs */
 524
 525 #define CONFIG_BAUDRATE         115200
 526
 527 #define CONFIG_PREBOOT  "echo;" \
 528         "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
 529         "echo"
 530
 531 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 532         "u-boot_addr_r=200000\0"                                        \
 533         "kernel_addr_r=600000\0"                                        \
 534         "fdt_addr_r=880000\0"                                           \
 535         "ramdisk_addr_r=900000\0"                                       \
 536         "u-boot_addr=FFF00000\0"                                        \
 537         "kernel_addr=FFAC0000\0"                                        \
 538         "fdt_addr=FFEC0000\0"                                           \
 539         "ramdisk_addr=FEAC0000\0"                                       \
 540         "ramdiskfile=mpc5121ads/uRamdisk\0"                             \
 541         "u-boot=mpc5121ads/u-boot.bin\0"                                \
 542         "bootfile=mpc5121ads/uImage\0"                                  \
 543         "fdtfile=mpc5121ads/mpc5121ads.dtb\0"                           \
 544         "rootpath=/opt/eldk/ppc_6xx\n"                                  \
 545         "netdev=eth0\0"                                                 \
 546         "consdev=ttyPSC0\0"                                             \
 547         "nfsargs=setenv bootargs root=/dev/nfs rw "                     \
 548                 "nfsroot=${serverip}:${rootpath}\0"                     \
 549         "ramargs=setenv bootargs root=/dev/ram rw\0"                    \
 550         "addip=setenv bootargs ${bootargs} "                            \
 551                 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
 552                 ":${hostname}:${netdev}:off panic=1\0"                  \
 553         "addtty=setenv bootargs ${bootargs} "                           \
 554                 "console=${consdev},${baudrate}\0"                      \
 555         "flash_nfs=run nfsargs addip addtty;"                           \
 556                 "bootm ${kernel_addr} - ${fdt_addr}\0"                  \
 557         "flash_self=run ramargs addip addtty;"                          \
 558                 "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0"    \
 559         "net_nfs=tftp ${kernel_addr_r} ${bootfile};"                    \
 560                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 561                 "run nfsargs addip addtty;"                             \
 562                 "bootm ${kernel_addr_r} - ${fdt_addr_r}\0"              \
 563         "net_self=tftp ${kernel_addr_r} ${bootfile};"                   \
 564                 "tftp ${ramdisk_addr_r} ${ramdiskfile};"                \
 565                 "tftp ${fdt_addr_r} ${fdtfile};"                        \
 566                 "run ramargs addip addtty;"                             \
 567                 "bootm ${kernel_addr_r} ${ramdisk_addr_r} ${fdt_addr_r}\0"\
 568         "load=tftp ${u-boot_addr_r} ${u-boot}\0"                        \
 569         "update=protect off ${u-boot_addr} +${filesize};"               \
 570                 "era ${u-boot_addr} +${filesize};"                      \
 571                 "cp.b ${u-boot_addr_r} ${u-boot_addr} ${filesize}\0"    \
 572         "upd=run load update\0"                                         \
 573         ""
 574
 575 #define CONFIG_BOOTCOMMAND      "run flash_self"
 576
 577 #define CONFIG_OF_LIBFDT        1
 578 #define CONFIG_OF_BOARD_SETUP   1
 579 #define CONFIG_OF_SUPPORT_OLD_DEVICE_TREES      1
 580
 581 #define OF_CPU                  "PowerPC,5121@0"
 582 #define OF_SOC_COMPAT           "fsl,mpc5121-immr"
 583 #define OF_TBCLK                (bd->bi_busfreq / 4)
 584 #define OF_STDOUT_PATH          "/soc@80000000/serial@11300"
 585
 586 /*-----------------------------------------------------------------------
 587  * IDE/ATA stuff
 588  *-----------------------------------------------------------------------
 589  */
 590
 591 #undef  CONFIG_IDE_8xx_PCCARD           /* Use IDE with PC Card Adapter */
 592 #undef  CONFIG_IDE_8xx_DIRECT           /* Direct IDE    not supported  */
 593 #undef  CONFIG_IDE_LED                  /* LED   for IDE not supported  */
 594
 595 #define CONFIG_IDE_RESET                /* reset for IDE supported      */
 596 #define CONFIG_IDE_PREINIT
 597
 598 #define CONFIG_SYS_IDE_MAXBUS           1       /* max. 1 IDE bus               */
 599 #define CONFIG_SYS_IDE_MAXDEVICE        2       /* max. 1 drive per IDE bus     */
 600
 601 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 602 #define CONFIG_SYS_ATA_BASE_ADDR        get_pata_base()
 603
 604 /* Offset for data I/O                  RefMan MPC5121EE Table 28-10    */
 605 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x00A0)
 606
 607 /* Offset for normal register accesses  */
 608 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 609
 610 /* Offset for alternate registers       RefMan MPC5121EE Table 28-23    */
 611 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x00D8)
 612
 613 /* Interval between registers   */
 614 #define CONFIG_SYS_ATA_STRIDE           4
 615
 616 #define ATA_BASE_ADDR                   get_pata_base()
 617
 618 /*
 619  * Control register bit definitions
 620  */
 621 #define FSL_ATA_CTRL_FIFO_RST_B         0x80000000
 622 #define FSL_ATA_CTRL_ATA_RST_B          0x40000000
 623 #define FSL_ATA_CTRL_FIFO_TX_EN         0x20000000
 624 #define FSL_ATA_CTRL_FIFO_RCV_EN        0x10000000
 625 #define FSL_ATA_CTRL_DMA_PENDING        0x08000000
 626 #define FSL_ATA_CTRL_DMA_ULTRA          0x04000000
 627 #define FSL_ATA_CTRL_DMA_WRITE          0x02000000
 628 #define FSL_ATA_CTRL_IORDY_EN           0x01000000
 629
 630 #endif  /* __CONFIG_H */