include/configs/mx31pdk.h

   1 /*
   2  * (C) Copyright 2008 Magnus Lilja <lilja.magnus@gmail.com>
   3  *
   4  * (C) Copyright 2004
   5  * Texas Instruments.
   6  * Richard Woodruff <r-woodruff2@ti.com>
   7  * Kshitij Gupta <kshitij@ti.com>
   8  *
   9  * Configuration settings for the Freescale i.MX31 PDK board.
  10  *
  11  * See file CREDITS for list of people who contributed to this
  12  * project.
  13  *
  14  * This program is free software; you can redistribute it and/or
  15  * modify it under the terms of the GNU General Public License as
  16  * published by the Free Software Foundation; either version 2 of
  17  * the License, or (at your option) any later version.
  18  *
  19  * This program is distributed in the hope that it will be useful,
  20  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  22  * GNU General Public License for more details.
  23  *
  24  * You should have received a copy of the GNU General Public License
  25  * along with this program; if not, write to the Free Software
  26  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  27  * MA 02111-1307 USA
  28  */
  29
  30 #ifndef __CONFIG_H
  31 #define __CONFIG_H
  32
  33 #include <asm/arch/imx-regs.h>
  34
  35 /* High Level Configuration Options */
  36 #define CONFIG_ARM1136                  /* This is an arm1136 CPU core */
  37 #define CONFIG_MX31                     /* in a mx31 */
  38 #define CONFIG_MX31_HCLK_FREQ   26000000
  39 #define CONFIG_MX31_CLK32       32768
  40
  41 #define CONFIG_DISPLAY_CPUINFO
  42 #define CONFIG_DISPLAY_BOARDINFO
  43
  44 #define CONFIG_CMDLINE_TAG                      /* enable passing of ATAGs */
  45 #define CONFIG_SETUP_MEMORY_TAGS
  46 #define CONFIG_INITRD_TAG
  47
  48 #define CONFIG_MACH_TYPE        MACH_TYPE_MX31_3DS
  49
  50 #if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
  51 #define CONFIG_SKIP_LOWLEVEL_INIT
  52 #endif
  53
  54 /*
  55  * Size of malloc() pool
  56  */
  57 #define CONFIG_SYS_MALLOC_LEN           (2*CONFIG_ENV_SIZE + 2 * 128 * 1024)
  58
  59 /*
  60  * Hardware drivers
  61  */
  62
  63 #define CONFIG_MXC_UART
  64 #define CONFIG_SYS_MX31_UART1
  65 #define CONFIG_HW_WATCHDOG
  66 #define CONFIG_MXC_GPIO
  67
  68 #define CONFIG_HARD_SPI
  69 #define CONFIG_MXC_SPI
  70 #define CONFIG_DEFAULT_SPI_BUS  1
  71 #define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH)
  72
  73 #define CONFIG_FSL_PMIC
  74 #define CONFIG_FSL_PMIC_BUS     1
  75 #define CONFIG_FSL_PMIC_CS      2
  76 #define CONFIG_FSL_PMIC_CLK     1000000
  77 #define CONFIG_FSL_PMIC_MODE    (SPI_MODE_0 | SPI_CS_HIGH)
  78 #define CONFIG_RTC_MC13783
  79
  80 /* allow to overwrite serial and ethaddr */
  81 #define CONFIG_ENV_OVERWRITE
  82 #define CONFIG_CONS_INDEX               1
  83 #define CONFIG_BAUDRATE                 115200
  84 #define CONFIG_SYS_BAUDRATE_TABLE       {9600, 19200, 38400, 57600, 115200}
  85
  86 /***********************************************************
  87  * Command definition
  88  ***********************************************************/
  89
  90 #include <config_cmd_default.h>
  91
  92 #define CONFIG_CMD_MII
  93 #define CONFIG_CMD_PING
  94 #define CONFIG_CMD_DHCP
  95 #define CONFIG_CMD_SPI
  96 #define CONFIG_CMD_DATE
  97 #define CONFIG_CMD_NAND
  98
  99 /*
 100  * Disabled due to compilation errors in cmd_bootm.c (IMLS seems to require
 101  * that CFG_NO_FLASH is undefined).
 102  */
 103 #undef CONFIG_CMD_IMLS
 104
 105 #define BOARD_LATE_INIT
 106
 107 #define CONFIG_BOOTDELAY        3
 108
 109 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 110         "bootargs_base=setenv bootargs console=ttymxc0,115200\0"        \
 111         "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs "       \
 112                 "ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0"     \
 113         "bootcmd=run bootcmd_net\0"                                     \
 114         "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; "     \
 115                 "tftpboot 0x81000000 uImage-mx31; bootm\0"              \
 116         "prg_uboot=tftpboot 0x81000000 u-boot-nand.bin; "               \
 117                 "nand erase 0x0 0x40000; "                              \
 118                 "nand write 0x81000000 0x0 0x40000\0"
 119
 120 #define CONFIG_NET_MULTI
 121 #define CONFIG_SMC911X
 122 #define CONFIG_SMC911X_BASE     0xB6000000
 123 #define CONFIG_SMC911X_32_BIT
 124
 125 /*
 126  * Miscellaneous configurable options
 127  */
 128 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 129 #define CONFIG_SYS_PROMPT       "MX31PDK U-Boot > "
 130 #define CONFIG_SYS_CBSIZE       256     /* Console I/O Buffer Size */
 131 /* Print Buffer Size */
 132 #define CONFIG_SYS_PBSIZE       (CONFIG_SYS_CBSIZE + \
 133                                 sizeof(CONFIG_SYS_PROMPT)+16)
 134 /* max number of command args */
 135 #define CONFIG_SYS_MAXARGS      16
 136 /* Boot Argument Buffer Size */
 137 #define CONFIG_SYS_BARGSIZE     CONFIG_SYS_CBSIZE
 138
 139 /* memtest works on */
 140 #define CONFIG_SYS_MEMTEST_START        0x80000000
 141 #define CONFIG_SYS_MEMTEST_END          0x10000
 142
 143 /* default load address */
 144 #define CONFIG_SYS_LOAD_ADDR            0x81000000
 145
 146 #define CONFIG_SYS_HZ                   1000
 147
 148 #define CONFIG_CMDLINE_EDITING
 149
 150 /*-----------------------------------------------------------------------
 151  * Stack sizes
 152  *
 153  * The stack sizes are set up in start.S using the settings below
 154  */
 155 #define CONFIG_STACKSIZE        (128 * 1024) /* regular stack */
 156
 157 /*-----------------------------------------------------------------------
 158  * Physical Memory Map
 159  */
 160 #define CONFIG_NR_DRAM_BANKS    1
 161 #define PHYS_SDRAM_1            CSD0_BASE
 162 #define PHYS_SDRAM_1_SIZE       (128 * 1024 * 1024)
 163 #define CONFIG_BOARD_EARLY_INIT_F
 164
 165 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 166 #define CONFIG_SYS_INIT_RAM_ADDR        IRAM_BASE_ADDR
 167 #define CONFIG_SYS_INIT_RAM_SIZE        IRAM_SIZE
 168 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 169                                                 GENERATED_GBL_DATA_SIZE)
 170 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
 171                                                 CONFIG_SYS_GBL_DATA_OFFSET)
 172
 173 /*-----------------------------------------------------------------------
 174  * FLASH and environment organization
 175  */
 176 /* No NOR flash present */
 177 #define CONFIG_SYS_NO_FLASH
 178
 179 #define CONFIG_ENV_IS_IN_NAND
 180 #define CONFIG_ENV_OFFSET               0x40000
 181 #define CONFIG_ENV_OFFSET_REDUND        0x60000
 182 #define CONFIG_ENV_SIZE                 (128 * 1024)
 183
 184 /*
 185  * NAND driver
 186  */
 187 #define CONFIG_NAND_MXC
 188 #define CONFIG_MXC_NAND_REGS_BASE      NFC_BASE_ADDR
 189 #define CONFIG_SYS_MAX_NAND_DEVICE     1
 190 #define CONFIG_SYS_NAND_BASE           NFC_BASE_ADDR
 191 #define CONFIG_MXC_NAND_HWECC
 192 #define CONFIG_SYS_NAND_LARGEPAGE
 193
 194 /* NAND configuration for the NAND_SPL */
 195
 196 /* Start copying real U-boot from the second page */
 197 #define CONFIG_SYS_NAND_U_BOOT_OFFS     0x800
 198 #define CONFIG_SYS_NAND_U_BOOT_SIZE     0x30000
 199 /* Load U-Boot to this address */
 200 #define CONFIG_SYS_NAND_U_BOOT_DST      0x87f00000
 201 #define CONFIG_SYS_NAND_U_BOOT_START    CONFIG_SYS_NAND_U_BOOT_DST
 202
 203 #define CONFIG_SYS_NAND_PAGE_SIZE       0x800
 204 #define CONFIG_SYS_NAND_BLOCK_SIZE      (128 * 1024)
 205 #define CONFIG_SYS_NAND_PAGE_COUNT      64
 206 #define CONFIG_SYS_NAND_SIZE            (256 * 1024 * 1024)
 207 #define CONFIG_SYS_NAND_BAD_BLOCK_POS   0
 208
 209
 210 /* Configuration of lowlevel_init.S (clocks and SDRAM) */
 211 #define CCM_CCMR_SETUP          0x074B0BF5
 212 #define CCM_PDR0_SETUP_532MHZ   (PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | \
 213                                  PDR0_HSP_PODF(3) | PDR0_NFC_PODF(5) |     \
 214                                  PDR0_IPG_PODF(1) | PDR0_MAX_PODF(3) |     \
 215                                  PDR0_MCU_PODF(0))
 216 #define CCM_MPCTL_SETUP_532MHZ  (PLL_PD(0) | PLL_MFD(51) | PLL_MFI(10) |   \
 217                                  PLL_MFN(12))
 218
 219 #define ESDMISC_MDDR_SETUP      0x00000004
 220 #define ESDMISC_MDDR_RESET_DL   0x0000000c
 221 #define ESDCFG0_MDDR_SETUP      0x006ac73a
 222
 223 #define ESDCTL_ROW_COL          (ESDCTL_SDE | ESDCTL_ROW(2) | ESDCTL_COL(2))
 224 #define ESDCTL_SETTINGS         (ESDCTL_ROW_COL | ESDCTL_SREFR(3) | \
 225                                  ESDCTL_DSIZ(2) | ESDCTL_BL(1))
 226 #define ESDCTL_PRECHARGE        (ESDCTL_ROW_COL | ESDCTL_CMD_PRECHARGE)
 227 #define ESDCTL_AUTOREFRESH      (ESDCTL_ROW_COL | ESDCTL_CMD_AUTOREFRESH)
 228 #define ESDCTL_LOADMODEREG      (ESDCTL_ROW_COL | ESDCTL_CMD_LOADMODEREG)
 229 #define ESDCTL_RW               ESDCTL_SETTINGS
 230
 231 #endif /* __CONFIG_H */