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git.ipfire.org Git - people/ms/u-boot.git/blob - include/configs/mx6sxsabresd.h
2 * Copyright 2014 Freescale Semiconductor, Inc.
4 * Configuration settings for the Freescale i.MX6SX Sabresd board.
6 * SPDX-License-Identifier: GPL-2.0+
13 #include "mx6_common.h"
16 #define CONFIG_SPL_LIBCOMMON_SUPPORT
17 #define CONFIG_SPL_MMC_SUPPORT
21 /* Size of malloc() pool */
22 #define CONFIG_SYS_MALLOC_LEN (3 * SZ_1M)
24 #define CONFIG_BOARD_EARLY_INIT_F
26 #define CONFIG_MXC_UART
27 #define CONFIG_MXC_UART_BASE UART1_BASE
29 #ifdef CONFIG_IMX_BOOTAUX
30 /* Set to QSPI2 B flash at default */
31 #define CONFIG_SYS_AUXCORE_BOOTDATA 0x78000000
32 #define CONFIG_CMD_SETEXPR
34 #define UPDATE_M4_ENV \
35 "m4image=m4_qspi.bin\0" \
36 "loadm4image=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${m4image}\0" \
37 "update_m4_from_sd=" \
38 "if sf probe 1:0; then " \
39 "if run loadm4image; then " \
40 "setexpr fw_sz ${filesize} + 0xffff; " \
41 "setexpr fw_sz ${fw_sz} / 0x10000; " \
42 "setexpr fw_sz ${fw_sz} * 0x10000; " \
43 "sf erase 0x0 ${fw_sz}; " \
44 "sf write ${loadaddr} 0x0 ${filesize}; " \
47 "m4boot=sf probe 1:0; bootaux "__stringify(CONFIG_SYS_AUXCORE_BOOTDATA)"\0"
49 #define UPDATE_M4_ENV ""
52 #define CONFIG_EXTRA_ENV_SETTINGS \
57 "fdt_high=0xffffffff\0" \
58 "initrd_high=0xffffffff\0" \
59 "fdt_file=imx6sx-sdb.dtb\0" \
60 "fdt_addr=0x88000000\0" \
63 "videomode=video=ctfb:x:800,y:480,depth:24,pclk:29850,le:89,ri:164,up:23,lo:10,hs:10,vs:10,sync:0,vmode:0\0" \
66 "mmcroot=/dev/mmcblk0p2 rootwait rw\0" \
67 "mmcargs=setenv bootargs console=${console},${baudrate} " \
70 "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
71 "bootscript=echo Running bootscript from mmc ...; " \
73 "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
74 "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr} ${fdt_file}\0" \
75 "mmcboot=echo Booting from mmc ...; " \
77 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
78 "if run loadfdt; then " \
79 "bootz ${loadaddr} - ${fdt_addr}; " \
81 "if test ${boot_fdt} = try; then " \
84 "echo WARN: Cannot load the DT; " \
90 "netargs=setenv bootargs console=${console},${baudrate} " \
92 "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
93 "netboot=echo Booting from net ...; " \
95 "if test ${ip_dyn} = yes; then " \
96 "setenv get_cmd dhcp; " \
98 "setenv get_cmd tftp; " \
100 "${get_cmd} ${image}; " \
101 "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
102 "if ${get_cmd} ${fdt_addr} ${fdt_file}; then " \
103 "bootz ${loadaddr} - ${fdt_addr}; " \
105 "if test ${boot_fdt} = try; then " \
108 "echo WARN: Cannot load the DT; " \
115 #define CONFIG_BOOTCOMMAND \
116 "mmc dev ${mmcdev};" \
117 "mmc dev ${mmcdev}; if mmc rescan; then " \
118 "if run loadbootscript; then " \
121 "if run loadimage; then " \
123 "else run netboot; " \
126 "else run netboot; fi"
128 /* Miscellaneous configurable options */
129 #define CONFIG_SYS_MEMTEST_START 0x80000000
130 #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x10000)
132 #define CONFIG_STACKSIZE SZ_128K
134 /* Physical Memory Map */
135 #define CONFIG_NR_DRAM_BANKS 1
136 #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR
137 #define PHYS_SDRAM_SIZE SZ_1G
139 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM
140 #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR
141 #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
143 #define CONFIG_SYS_INIT_SP_OFFSET \
144 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
145 #define CONFIG_SYS_INIT_SP_ADDR \
146 (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
148 /* MMC Configuration */
149 #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
152 #define CONFIG_CMD_I2C
153 #define CONFIG_SYS_I2C
154 #define CONFIG_SYS_I2C_MXC
155 #define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */
156 #define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */
157 #define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */
158 #define CONFIG_SYS_I2C_SPEED 100000
162 #define CONFIG_POWER_I2C
163 #define CONFIG_POWER_PFUZE100
164 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
167 #define CONFIG_CMD_PING
168 #define CONFIG_CMD_DHCP
169 #define CONFIG_CMD_MII
170 #define CONFIG_FEC_MXC
173 #define IMX_FEC_BASE ENET_BASE_ADDR
174 #define CONFIG_FEC_MXC_PHYADDR 0x1
176 #define CONFIG_FEC_XCV_TYPE RGMII
177 #define CONFIG_ETHPRIME "FEC"
179 #define CONFIG_PHYLIB
180 #define CONFIG_PHY_ATHEROS
183 #define CONFIG_CMD_USB
184 #ifdef CONFIG_CMD_USB
185 #define CONFIG_USB_EHCI
186 #define CONFIG_USB_EHCI_MX6
187 #define CONFIG_USB_STORAGE
188 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
189 #define CONFIG_USB_HOST_ETHER
190 #define CONFIG_USB_ETHER_ASIX
191 #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
192 #define CONFIG_MXC_USB_FLAGS 0
193 #define CONFIG_USB_MAX_CONTROLLER_COUNT 2
196 #define CONFIG_CMD_PCI
197 #ifdef CONFIG_CMD_PCI
199 #define CONFIG_PCI_PNP
200 #define CONFIG_PCI_SCAN_SHOW
201 #define CONFIG_PCIE_IMX
202 #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(2, 0)
203 #define CONFIG_PCIE_IMX_POWER_GPIO IMX_GPIO_NR(2, 1)
206 #define CONFIG_IMX_THERMAL
208 #define CONFIG_CMD_TIME
211 #ifdef CONFIG_FSL_QSPI
212 #define CONFIG_CMD_SF
213 #define CONFIG_SYS_FSL_QSPI_LE
214 #define CONFIG_SYS_FSL_QSPI_AHB
215 #ifdef CONFIG_MX6SX_SABRESD_REVA
216 #define FSL_QSPI_FLASH_SIZE SZ_16M
218 #define FSL_QSPI_FLASH_SIZE SZ_32M
220 #define FSL_QSPI_FLASH_NUM 2
223 #ifndef CONFIG_SPL_BUILD
226 #define CONFIG_CFB_CONSOLE
227 #define CONFIG_VIDEO_MXS
228 #define CONFIG_VIDEO_LOGO
229 #define CONFIG_VIDEO_SW_CURSOR
230 #define CONFIG_VGA_AS_SINGLE_DEVICE
231 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
232 #define CONFIG_SPLASH_SCREEN
233 #define CONFIG_SPLASH_SCREEN_ALIGN
234 #define CONFIG_CMD_BMP
235 #define CONFIG_BMP_16BPP
236 #define CONFIG_VIDEO_BMP_RLE8
237 #define CONFIG_VIDEO_BMP_LOGO
238 #define MXS_LCDIF_BASE MX6SX_LCDIF1_BASE_ADDR
242 #define CONFIG_ENV_OFFSET (8 * SZ_64K)
243 #define CONFIG_ENV_SIZE SZ_8K
244 #define CONFIG_ENV_IS_IN_MMC
246 #define CONFIG_SYS_FSL_USDHC_NUM 3
247 #if defined(CONFIG_ENV_IS_IN_MMC)
248 #define CONFIG_SYS_MMC_ENV_DEV 2 /*USDHC4*/
251 #endif /* __CONFIG_H */