include/configs/neo.h

   1 /*
   2  * (C) Copyright 2007-2008
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef __CONFIG_H
  25 #define __CONFIG_H
  26
  27
  28 #define CONFIG_405EP            1       /* this is a PPC405 CPU */
  29 #define CONFIG_4xx              1       /*  member of PPC4xx family */
  30 #define CONFIG_NEO              1       /*  on a Neo board */
  31
  32 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  33
  34 /*
  35  * Include common defines/options for all AMCC eval boards
  36  */
  37 #define CONFIG_HOSTNAME         neo
  38 #include "amcc-common.h"
  39
  40 #define CONFIG_BOARD_EARLY_INIT_F       /* call board_early_init_f */
  41
  42 #define CONFIG_SYS_CLK_FREQ     33333333 /* external frequency to pll   */
  43
  44 /*
  45  * Configure PLL
  46  */
  47 #define PLLMR0_DEFAULT PLLMR0_266_133_66_33
  48 #define PLLMR1_DEFAULT PLLMR1_266_133_66_33
  49
  50 /* new uImage format support */
  51 #define CONFIG_FIT
  52 #define CONFIG_FIT_VERBOSE      /* enable fit_format_{error,warning}() */
  53
  54 #define CONFIG_ENV_IS_IN_FLASH  /* use FLASH for environment vars */
  55
  56 /*
  57  * Default environment variables
  58  */
  59 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  60         CONFIG_AMCC_DEF_ENV                                             \
  61         CONFIG_AMCC_DEF_ENV_POWERPC                                     \
  62         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
  63         "kernel_addr=fc000000\0"                                        \
  64         "fdt_addr=fc1e0000\0"                                           \
  65         "ramdisk_addr=fc200000\0"                                       \
  66         ""
  67
  68 #define CONFIG_PHY_ADDR         4       /* PHY address                  */
  69 #define CONFIG_HAS_ETH0
  70 #define CONFIG_HAS_ETH1
  71 #define CONFIG_PHY1_ADDR        0xc     /* EMAC1 PHY address            */
  72 #define CONFIG_PHY_CLK_FREQ    EMAC_STACR_CLK_66MHZ
  73
  74 /*
  75  * Commands additional to the ones defined in amcc-common.h
  76  */
  77 #define CONFIG_CMD_CACHE
  78 #define CONFIG_CMD_DATE
  79 #define CONFIG_CMD_DTT
  80 #undef CONFIG_CMD_EEPROM
  81
  82 /*
  83  * SDRAM configuration (please see cpu/ppc/sdram.[ch])
  84  */
  85 #define CONFIG_SDRAM_BANK0      1       /* init onboard SDRAM bank 0 */
  86
  87 /* SDRAM timings used in datasheet */
  88 #define CONFIG_SYS_SDRAM_CL            3        /* CAS latency */
  89 #define CONFIG_SYS_SDRAM_tRP           20       /* PRECHARGE command period */
  90 #define CONFIG_SYS_SDRAM_tRC           66       /* ACTIVE-to-ACTIVE command period */
  91 #define CONFIG_SYS_SDRAM_tRCD          20       /* ACTIVE-to-READ delay */
  92 #define CONFIG_SYS_SDRAM_tRFC           66      /* Auto refresh period */
  93
  94 /*
  95  * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
  96  * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
  97  * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
  98  * The Linux BASE_BAUD define should match this configuration.
  99  *    baseBaud = cpuClock/(uartDivisor*16)
 100  * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 101  * set Linux BASE_BAUD to 403200.
 102  */
 103 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
 104 #define CONFIG_SYS_NS16550
 105 #define CONFIG_SYS_NS16550_SERIAL
 106 #define CONFIG_SYS_NS16550_REG_SIZE     1
 107 #define CONFIG_SYS_NS16550_CLK          get_serial_clock()
 108
 109 #undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
 110 #undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
 111 #define CONFIG_SYS_BASE_BAUD            691200
 112
 113 /*
 114  * I2C stuff
 115  */
 116 #define CONFIG_SYS_I2C_SPEED            100000  /* I2C speed and slave address  */
 117
 118 /* RTC */
 119 #define CONFIG_RTC_DS1337
 120 #define CONFIG_SYS_I2C_RTC_ADDR 0x68
 121
 122 /* Temp sensor/hwmon/dtt */
 123 #define CONFIG_DTT_LM63         1       /* National LM63        */
 124 #define CONFIG_DTT_SENSORS      { 0 }   /* Sensor addresses     */
 125 #define CONFIG_DTT_PWM_LOOKUPTABLE      \
 126                 { { 40, 10 }, { 50, 20 }, { 60, 40 } }
 127 #define CONFIG_DTT_TACH_LIMIT   0xa10
 128
 129 /*
 130  * FLASH organization
 131  */
 132 #define CONFIG_SYS_FLASH_CFI                            /* The flash is CFI compatible  */
 133 #define CONFIG_FLASH_CFI_DRIVER                 /* Use common CFI driver        */
 134
 135 #define CONFIG_SYS_FLASH_BASE           0xFC000000
 136 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 137
 138 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* max number of memory banks           */
 139 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* max number of sectors on one chip    */
 140
 141 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 142 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 143
 144 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1     /* use buffered writes (20x faster)     */
 145 #define CONFIG_SYS_FLASH_PROTECTION     1       /* use hardware flash protection        */
 146
 147 #define CONFIG_SYS_FLASH_EMPTY_INFO             /* print 'E' for empty sector on flinfo */
 148 #define CONFIG_SYS_FLASH_QUIET_TEST     1       /* don't warn upon unknown flash        */
 149
 150 #ifdef CONFIG_ENV_IS_IN_FLASH
 151 #define CONFIG_ENV_SECT_SIZE    0x20000 /* size of one complete sector          */
 152 #define CONFIG_ENV_ADDR         ((-CONFIG_SYS_MONITOR_LEN)-CONFIG_ENV_SECT_SIZE)
 153 #define CONFIG_ENV_SIZE         0x2000  /* Total Size of Environment Sector     */
 154
 155 /* Address and size of Redundant Environment Sector     */
 156 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 157 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 158 #endif
 159
 160 /*
 161  * PPC405 GPIO Configuration
 162  */
 163 #define CONFIG_SYS_4xx_GPIO_TABLE { /*                          GPIO    Alternate1      */      \
 164 {                                                                                       \
 165 /* GPIO Core 0 */                                                                       \
 166 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO0   PerBLast        */      \
 167 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO1   TS1E            */      \
 168 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO2   TS2E            */      \
 169 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO3   TS1O            */      \
 170 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO4   TS2O            */      \
 171 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO5   TS3             */      \
 172 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO6   TS4             */      \
 173 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO7   TS5             */      \
 174 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO8   TS6             */      \
 175 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO9   TrcClk          */      \
 176 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10  PerCS1          */      \
 177 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11  PerCS2          */      \
 178 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12  PerCS3          */      \
 179 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13  PerCS4          */      \
 180 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO14  PerAddr03       */      \
 181 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO15  PerAddr04       */      \
 182 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO16  PerAddr05       */      \
 183 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17  IRQ0            */      \
 184 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18  IRQ1            */      \
 185 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19  IRQ2            */      \
 186 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO20  IRQ3            */      \
 187 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO21  IRQ4            */      \
 188 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO22  IRQ5            */      \
 189 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23  IRQ6            */      \
 190 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24  UART0_DCD       */      \
 191 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25  UART0_DSR       */      \
 192 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26  UART0_RI        */      \
 193 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27  UART0_DTR       */      \
 194 { GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28  UART1_Rx        */      \
 195 { GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29  UART1_Tx        */      \
 196 { GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30  RejectPkt0      */      \
 197 { GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31  RejectPkt1      */      \
 198 }                                                                                       \
 199 }
 200
 201 /*
 202  * Definitions for initial stack pointer and data area (in data cache)
 203  */
 204 /* use on chip memory (OCM) for temperary stack until sdram is tested */
 205 #define CONFIG_SYS_TEMP_STACK_OCM        1
 206
 207 /* On Chip Memory location */
 208 #define CONFIG_SYS_OCM_DATA_ADDR        0xF8000000
 209 #define CONFIG_SYS_OCM_DATA_SIZE        0x1000
 210 #define CONFIG_SYS_INIT_RAM_ADDR        CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM             */
 211 #define CONFIG_SYS_INIT_RAM_SIZE        CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM    */
 212
 213 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 214 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 215
 216 /*
 217  * External Bus Controller (EBC) Setup
 218  */
 219
 220 /* Memory Bank 0 (NOR-FLASH) initialization                    */
 221 #define CONFIG_SYS_EBC_PB0AP            0x92015480
 222 #define CONFIG_SYS_EBC_PB0CR            0xFC0DA000  /* BAS=0xFC0,BS=64MB,BU=R/W,BW=16bit */
 223
 224 /* Memory Bank 1 (NVRAM) initialization                                        */
 225 #define CONFIG_SYS_EBC_PB1AP            0x92015480
 226 #define CONFIG_SYS_EBC_PB1CR            0xFB85A000  /* BAS=0xFF8,BS=4MB,BU=R/W,BW=8bit  */
 227
 228 /* Memory Bank 2 (FPGA) initialization                 */
 229 #define CONFIG_FPGA_BASE        0x7f100000
 230 #define CONFIG_SYS_EBC_PB2AP            0x92015480
 231 #define CONFIG_SYS_EBC_PB2CR            0x7f11a000  /* BAS=0x7f1,BS=1MB,BU=R/W,BW=16bit */
 232
 233 /* Memory Bank 3 (Latches) initialization                      */
 234 #define CONFIG_SYS_EBC_PB3AP            0x92015480
 235 #define CONFIG_SYS_EBC_PB3CR            0x7f21a000  /* BAS=0x7f2,BS=1MB,BU=R/W,BW=16bit */
 236
 237 #endif  /* __CONFIG_H */