include/configs/ocotea.h

   1 /*
   2  * (C) Copyright 2004 Paul Reynolds <PaulReynolds@lhsolutions.com>
   3  *
   4  * (C) Copyright 2005
   5  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /************************************************************************
  11  * 1 March 2004  Travis B. Sawyer <tsawyer@sandburst.com>
  12  * Adapted to current Das U-Boot source
  13  ***********************************************************************/
  14
  15
  16 /************************************************************************
  17  * OCOTEA.h - configuration for AMCC 440GX Ref (Ocotea)
  18  ***********************************************************************/
  19
  20 #ifndef __CONFIG_H
  21 #define __CONFIG_H
  22
  23 /*-----------------------------------------------------------------------
  24  * High Level Configuration Options
  25  *----------------------------------------------------------------------*/
  26 #define CONFIG_OCOTEA           1           /* Board is ebony           */
  27 #define CONFIG_440GX            1           /* Specifc GX support       */
  28 #define CONFIG_440              1           /* ... PPC440 family        */
  29 #define CONFIG_BOARD_EARLY_INIT_F 1         /* Call board_pre_init      */
  30 #define CONFIG_SYS_CLK_FREQ     33333333    /* external freq to pll     */
  31
  32 #define CONFIG_SYS_TEXT_BASE    0xFFFC0000
  33
  34 /*
  35  * Include common defines/options for all AMCC eval boards
  36  */
  37 #define CONFIG_HOSTNAME         ocotea
  38 #include "amcc-common.h"
  39
  40 /*-----------------------------------------------------------------------
  41  * Base addresses -- Note these are effective addresses where the
  42  * actual resources get mapped (not physical addresses)
  43  *----------------------------------------------------------------------*/
  44 #define CONFIG_SYS_FLASH_BASE       0xff800000      /* start of FLASH           */
  45 #define CONFIG_SYS_PCI_MEMBASE      0x80000000      /* mapped pci memory        */
  46 #define CONFIG_SYS_ISRAM_BASE       0xc0000000      /* internal SRAM            */
  47 #define CONFIG_SYS_PCI_BASE         0xd0000000      /* internal PCI regs        */
  48
  49 #define CONFIG_SYS_FPGA_BASE        (CONFIG_SYS_PERIPHERAL_BASE + 0x08300000)
  50 #define CONFIG_SYS_NVRAM_BASE_ADDR (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
  51
  52 /*-----------------------------------------------------------------------
  53  * Initial RAM & stack pointer (placed in internal SRAM)
  54  *----------------------------------------------------------------------*/
  55 #define CONFIG_SYS_TEMP_STACK_OCM  1
  56 #define CONFIG_SYS_OCM_DATA_ADDR   CONFIG_SYS_ISRAM_BASE
  57 #define CONFIG_SYS_INIT_RAM_ADDR   CONFIG_SYS_ISRAM_BASE  /* Initial RAM address        */
  58 #define CONFIG_SYS_INIT_RAM_SIZE    0x2000          /* Size of used area in RAM */
  59
  60 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
  61 #define CONFIG_SYS_INIT_SP_OFFSET       (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
  62
  63 /*-----------------------------------------------------------------------
  64  * Serial Port
  65  *----------------------------------------------------------------------*/
  66 #define CONFIG_CONS_INDEX       1       /* Use UART0                    */
  67 #define CONFIG_SYS_EXT_SERIAL_CLOCK     (1843200 * 6)   /* Ext clk @ 11.059 MHz */
  68
  69 /*-----------------------------------------------------------------------
  70  * Environment
  71  *----------------------------------------------------------------------*/
  72 /*
  73  * Define here the location of the environment variables (FLASH or NVRAM).
  74  * Note: DENX encourages to use redundant environment in FLASH. NVRAM is only
  75  *       supported for backward compatibility.
  76  */
  77 #if 1
  78 #define CONFIG_ENV_IS_IN_FLASH     1    /* use FLASH for environment vars       */
  79 #else
  80 #define CONFIG_ENV_IS_IN_NVRAM  1       /* use NVRAM for environment vars       */
  81 #endif
  82
  83
  84 /*-----------------------------------------------------------------------
  85  * NVRAM/RTC
  86  *
  87  * NOTE: Upper 8 bytes of NVRAM is where the RTC registers are located.
  88  * The DS1743 code assumes this condition (i.e. -- it assumes the base
  89  * address for the RTC registers is:
  90  *
  91  *      CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE
  92  *
  93  *----------------------------------------------------------------------*/
  94 #define CONFIG_SYS_NVRAM_SIZE       (0x2000 - 8)    /* NVRAM size(8k)- RTC regs */
  95 #define CONFIG_RTC_DS174x       1                   /* DS1743 RTC               */
  96
  97 #ifdef CONFIG_ENV_IS_IN_NVRAM
  98 #define CONFIG_ENV_SIZE         0x1000      /* Size of Environment vars */
  99 #define CONFIG_ENV_ADDR         \
 100         (CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)
 101 #endif /* CONFIG_ENV_IS_IN_NVRAM */
 102
 103 /*-----------------------------------------------------------------------
 104  * FLASH related
 105  *----------------------------------------------------------------------*/
 106 #define CONFIG_SYS_MAX_FLASH_BANKS      3                   /* number of banks      */
 107 #define CONFIG_SYS_MAX_FLASH_SECT       64                  /* sectors per device   */
 108
 109 #undef  CONFIG_SYS_FLASH_CHECKSUM
 110 #define CONFIG_SYS_FLASH_ERASE_TOUT     120000  /* Timeout for Flash Erase (in ms)      */
 111 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Timeout for Flash Write (in ms)      */
 112
 113 #define CONFIG_SYS_FLASH_ADDR0         0x5555
 114 #define CONFIG_SYS_FLASH_ADDR1         0x2aaa
 115 #define CONFIG_SYS_FLASH_WORD_SIZE     unsigned char
 116
 117 #ifdef CONFIG_ENV_IS_IN_FLASH
 118 #define CONFIG_ENV_SECT_SIZE    0x10000         /* size of one complete sector  */
 119 #define CONFIG_ENV_ADDR         (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
 120 #define CONFIG_ENV_SIZE         0x4000  /* Total Size of Environment Sector     */
 121
 122 /* Address and size of Redundant Environment Sector     */
 123 #define CONFIG_ENV_ADDR_REDUND  (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
 124 #define CONFIG_ENV_SIZE_REDUND  (CONFIG_ENV_SIZE)
 125 #endif /* CONFIG_ENV_IS_IN_FLASH */
 126
 127 /*-----------------------------------------------------------------------
 128  * DDR SDRAM
 129  *----------------------------------------------------------------------*/
 130 #define CONFIG_SPD_EEPROM       1       /* Use SPD EEPROM for setup     */
 131 #define SPD_EEPROM_ADDRESS {0x53,0x52}  /* SPD i2c spd addresses        */
 132 #define CONFIG_PROG_SDRAM_TLB   1       /* setup SDRAM TLB's dynamically*/
 133
 134 /*-----------------------------------------------------------------------
 135  * I2C
 136  *----------------------------------------------------------------------*/
 137 #define CONFIG_SYS_I2C_PPC4XX_SPEED_0           400000
 138
 139 #define CONFIG_SYS_I2C_MULTI_EEPROMS
 140 #define CONFIG_SYS_I2C_EEPROM_ADDR      (0xa8>>1)
 141 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 142 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 143 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
 144
 145 /*
 146  * Default environment variables
 147  */
 148 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
 149         CONFIG_AMCC_DEF_ENV                                             \
 150         CONFIG_AMCC_DEF_ENV_PPC                                         \
 151         CONFIG_AMCC_DEF_ENV_NOR_UPD                                     \
 152         "kernel_addr=fff00000\0"                                        \
 153         "ramdisk_addr=fff10000\0"                                       \
 154         ""
 155
 156 #define CONFIG_PHY_ADDR         1       /* PHY address, See schematics  */
 157 #define CONFIG_PHY1_ADDR        2
 158 #define CONFIG_PHY2_ADDR        0x10
 159 #define CONFIG_PHY3_ADDR        0x18
 160 #define CONFIG_HAS_ETH0
 161 #define CONFIG_HAS_ETH1
 162 #define CONFIG_HAS_ETH2
 163 #define CONFIG_HAS_ETH3
 164 #define CONFIG_CIS8201_PHY      1       /* Enable 'special' RGMII mode for Cicada phy */
 165 #define CONFIG_PHY_GIGE         1       /* Include GbE speed/duplex detection */
 166 #define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
 167 #define CONFIG_PHY_RESET_DELAY  1000
 168
 169 /*
 170  * Commands additional to the ones defined in amcc-common.h
 171  */
 172 #define CONFIG_CMD_DATE
 173 #define CONFIG_CMD_PCI
 174 #define CONFIG_CMD_SDRAM
 175 #define CONFIG_CMD_SNTP
 176
 177 /*-----------------------------------------------------------------------
 178  * PCI stuff
 179  *-----------------------------------------------------------------------
 180  */
 181 /* General PCI */
 182 #define CONFIG_PCI                      /* include pci support          */
 183 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
 184 #define CONFIG_PCI_PNP                  /* do pci plug-and-play         */
 185 #define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup  */
 186 #define CONFIG_SYS_PCI_TARGBASE    0x80000000   /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
 187
 188 /* Board-specific PCI */
 189 #define CONFIG_SYS_PCI_TARGET_INIT              /* let board init pci target    */
 190
 191 #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8   /* AMCC */
 192 #define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe   /* Whatever */
 193
 194 #endif  /* __CONFIG_H */