include/configs/omap730.h

   1 /*
   2  *
   3  * BRIEF MODULE DESCRIPTION
   4  *   OMAP730 hardware map
   5  *
   6  * Copyright (C) 2004 MPC-Data Limited. (http://www.mpc-data.co.uk)
   7  * Author: MPC-Data Limited
   8  *         Dave Peverley
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __INCLUDED_OMAP730_H
  14 #define __INCLUDED_OMAP730_H
  15
  16 #include <asm/sizes.h>
  17
  18 /***************************************************************************
  19  * OMAP730 Configuration Registers
  20  **************************************************************************/
  21
  22 #define PERSEUS2_MPU_DEV_ID               ((unsigned int)(0xFFFE1000))
  23 #define PERSEUS2_GSM_DEV_ID0              ((unsigned int)(0xFFFE1000))
  24 #define PERSEUS2_GDM_DEV_ID1              ((unsigned int)(0xFFFE1002))
  25 #define DSP_CONF                          ((unsigned int)(0xFFFE1004))
  26 #define PERSEUS2_MPU_DIE_ID0              ((unsigned int)(0xFFFE1008))
  27 #define GSM_ASIC_CONF                     ((unsigned int)(0xFFFE1008))
  28 #define PERSEUS2_MPU_DIE_ID1              ((unsigned int)(0xFFFE100C))
  29 #define PERSEUS2_MODE1                    ((unsigned int)(0xFFFE1010))
  30 #define PERSEUS2_GSM_DIE_ID0              ((unsigned int)(0xFFFE1010))
  31 #define PERSEUS2_GSM_DIE_ID1              ((unsigned int)(0xFFFE1012))
  32 #define PERSEUS2_MODE2                    ((unsigned int)(0xFFFE1014))
  33 #define PERSEUS2_GSM_DIE_ID2              ((unsigned int)(0xFFFE1014))
  34 #define PERSEUS2_GSM_DIE_ID3              ((unsigned int)(0xFFFE1016))
  35 #define PERSEUS2_ANALOG_CELLS_CONF        ((unsigned int)(0xFFFE1018))
  36 #define SPECCTL                           ((unsigned int)(0xFFFE101C))
  37 #define SPARE1                            ((unsigned int)(0xFFFE1020))
  38 #define SPARE2                            ((unsigned int)(0xFFFE1024))
  39 #define GSM_PBG_IRQ                       ((unsigned int)(0xFFFE1028))
  40 #define DMA_REQ_CONF                      ((unsigned int)(0xFFFE1030))
  41 #define PE_CONF_NO_DUAL                   ((unsigned int)(0xFFFE1060))
  42 #define PERSEUS2_IO_CONF0                 ((unsigned int)(0xFFFE1070))
  43 #define PERSEUS2_IO_CONF1                 ((unsigned int)(0xFFFE1074))
  44 #define PERSEUS2_IO_CONF2                 ((unsigned int)(0xFFFE1078))
  45 #define PERSEUS2_IO_CONF3                 ((unsigned int)(0xFFFE107C))
  46 #define PERSEUS2_IO_CONF4                 ((unsigned int)(0xFFFE1080))
  47 #define PERSEUS2_IO_CONF5                 ((unsigned int)(0xFFFE1084))
  48 #define PERSEUS2_IO_CONF6                 ((unsigned int)(0xFFFE1088))
  49 #define PERSEUS2_IO_CONF7                 ((unsigned int)(0xFFFE108C))
  50 #define PERSEUS2_IO_CONF8                 ((unsigned int)(0xFFFE1090))
  51 #define PERSEUS2_IO_CONF9                 ((unsigned int)(0xFFFE1094))
  52 #define PERSEUS2_IO_CONF10                ((unsigned int)(0xFFFE1098))
  53 #define PERSEUS2_IO_CONF11                ((unsigned int)(0xFFFE109C))
  54 #define PERSEUS2_IO_CONF12                ((unsigned int)(0xFFFE10A0))
  55 #define PERSEUS2_IO_CONF13                ((unsigned int)(0xFFFE10A4))
  56 #define PERSEUS_PCC_CONF_REG              ((unsigned int)(0xFFFE10B4))
  57 #define BIST_STATUS_INTERNAL              ((unsigned int)(0xFFFE10B8))
  58 #define BIST_CONTROL                      ((unsigned int)(0xFFFE10C0))
  59 #define BOOT_ROM_REG                      ((unsigned int)(0xFFFE10C4))
  60 #define PRODUCTION_ID_REG                 ((unsigned int)(0xFFFE10C8))
  61 #define BIST_SECROM_SIGNATURE1_INTERNAL   ((unsigned int)(0xFFFE10D0))
  62 #define BIST_SECROM_SIGNATURE2_INTERNAL   ((unsigned int)(0xFFFE10D4))
  63 #define BIST_CONTROL_2                    ((unsigned int)(0xFFFE10D8))
  64 #define DEBUG1                            ((unsigned int)(0xFFFE10E0))
  65 #define DEBUG2                            ((unsigned int)(0xFFFE10E4))
  66 #define DEBUG_DMA_IRQ                     ((unsigned int)(0xFFFE10E8))
  67
  68 /***************************************************************************
  69  * OMAP730 EMIFS Registers                                       (TRM 2.5.7)
  70  **************************************************************************/
  71
  72 #define TCMIF_BASE                 0xFFFECC00
  73
  74 #define EMIFS_LRUREG               (TCMIF_BASE + 0x04)
  75 #define EMIFS_CONFIG               (TCMIF_BASE + 0x0C)
  76 #define FLASH_CFG_0                (TCMIF_BASE + 0x10)
  77 #define FLASH_CFG_1                (TCMIF_BASE + 0x14)
  78 #define FLASH_CFG_2                (TCMIF_BASE + 0x18)
  79 #define FLASH_CFG_3                (TCMIF_BASE + 0x1C)
  80 #define FL_CFG_DYN_WAIT            (TCMIF_BASE + 0x40)
  81 #define EMIFS_TIMEOUT1_REG         (TCMIF_BASE + 0x28)
  82 #define EMIFS_TIMEOUT2_REG         (TCMIF_BASE + 0x2C)
  83 #define EMIFS_TIMEOUT3_REG         (TCMIF_BASE + 0x30)
  84 #define EMIFS_ABORT_ADDR           (TCMIF_BASE + 0x44)
  85 #define EMIFS_ABORT_TYPE           (TCMIF_BASE + 0x48)
  86 #define EMIFS_ABORT_TOUT           (TCMIF_BASE + 0x4C)
  87 #define FLASH_ACFG_0_1             (TCMIF_BASE + 0x50)
  88 #define FLASH_ACFG_1_1             (TCMIF_BASE + 0x54)
  89 #define FLASH_ACFG_2_1             (TCMIF_BASE + 0x58)
  90 #define FLASH_ACFG_3_1             (TCMIF_BASE + 0x5C)
  91
  92 /***************************************************************************
  93  * OMAP730 Interrupt handlers
  94  **************************************************************************/
  95
  96 #define OMAP_IH1_BASE           0xFFFECB00     /* MPU Level 1 IRQ handler */
  97 #define OMAP_IH2_BASE           0xfffe0000
  98
  99 /***************************************************************************
 100  * OMAP730 Timers
 101  *
 102  * There are three general purpose OS timers in the 730 that can be
 103  * configured in autoreload or one-shot modes.
 104  **************************************************************************/
 105
 106 #define OMAP730_32kHz_TIMER_BASE  0xFFFB9000
 107
 108 /* 32k Timer Registers */
 109 #define TIMER32k_CR               0x08
 110 #define TIMER32k_TVR              0x00
 111 #define TIMER32k_TCR              0x04
 112
 113 /* 32k Timer Control Register definition */
 114 #define TIMER32k_TSS              (1<<0)
 115 #define TIMER32k_TRB              (1<<1)
 116 #define TIMER32k_INT              (1<<2)
 117 #define TIMER32k_ARL              (1<<3)
 118
 119 /* MPU Timer base addresses  */
 120 #define OMAP730_MPUTIMER_BASE   0xfffec500
 121 #define OMAP730_MPUTIMER_OFF    0x00000100
 122
 123 #define OMAP730_TIMER1_BASE     0xFFFEC500
 124 #define OMAP730_TIMER2_BASE     0xFFFEC600
 125 #define OMAP730_TIMER3_BASE     0xFFFEC700
 126
 127 /* MPU Timer Register offsets */
 128 #define CNTL_TIMER                 0x00   /* MPU_CNTL_TIMER */
 129 #define LOAD_TIM                   0x04   /* MPU_LOAD_TIMER */
 130 #define READ_TIM                   0x08   /* MPU_READ_TIMER */
 131
 132 /* MPU_CNTL_TIMER register bits */
 133 #define MPUTIM_FREE               (1<<6)
 134 #define MPUTIM_CLOCK_ENABLE       (1<<5)
 135 #define MPUTIM_PTV_MASK           (0x7<<MPUTIM_PTV_BIT)
 136 #define MPUTIM_PTV_BIT            2
 137 #define MPUTIM_AR                 (1<<1)
 138 #define MPUTIM_ST                 (1<<0)
 139
 140 /***************************************************************************
 141  * OMAP730 GPIO
 142  *
 143  * The GPIO control is split over 6 register bases in the OMAP730 to allow
 144  * access to all the (6 x 32) GPIO pins!
 145  **************************************************************************/
 146
 147 #define OMAP730_GPIO_BASE_1        0xFFFBC000
 148 #define OMAP730_GPIO_BASE_2        0xFFFBC800
 149 #define OMAP730_GPIO_BASE_3        0xFFFBD000
 150 #define OMAP730_GPIO_BASE_4        0xFFFBD800
 151 #define OMAP730_GPIO_BASE_5        0xFFFBE000
 152 #define OMAP730_GPIO_BASE_6        0xFFFBE800
 153
 154 #define GPIO_DATA_INPUT            0x00
 155 #define GPIO_DATA_OUTPUT           0x04
 156 #define GPIO_DIRECTION_CONTROL     0x08
 157 #define GPIO_INTERRUPT_CONTROL     0x0C
 158 #define GPIO_INTERRUPT_MASK        0x10
 159 #define GPIO_INTERRUPT_STATUS      0x14
 160
 161 #define GPIO_DATA_INPUT_1            ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_INPUT))
 162 #define GPIO_DATA_OUTPUT_1           ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DATA_OUTPUT))
 163 #define GPIO_DIRECTION_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_DIRECTION_CONTROL))
 164 #define GPIO_INTERRUPT_CONTROL_1     ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_CONTROL))
 165 #define GPIO_INTERRUPT_MASK_1        ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_MASK))
 166 #define GPIO_INTERRUPT_STATUS_1      ((unsigned int)(OMAP730_GPIO_BASE_1 + GPIO_INTERRUPT_STATUS))
 167
 168 #define GPIO_DATA_INPUT_2            ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_INPUT))
 169 #define GPIO_DATA_OUTPUT_2           ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DATA_OUTPUT))
 170 #define GPIO_DIRECTION_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_DIRECTION_CONTROL))
 171 #define GPIO_INTERRUPT_CONTROL_2     ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_CONTROL))
 172 #define GPIO_INTERRUPT_MASK_2        ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_MASK))
 173 #define GPIO_INTERRUPT_STATUS_2      ((unsigned int)(OMAP730_GPIO_BASE_2 + GPIO_INTERRUPT_STATUS))
 174
 175 #define GPIO_DATA_INPUT_3            ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_INPUT))
 176 #define GPIO_DATA_OUTPUT_3           ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DATA_OUTPUT))
 177 #define GPIO_DIRECTION_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_DIRECTION_CONTROL))
 178 #define GPIO_INTERRUPT_CONTROL_3     ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_CONTROL))
 179 #define GPIO_INTERRUPT_MASK_3        ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_MASK))
 180 #define GPIO_INTERRUPT_STATUS_3      ((unsigned int)(OMAP730_GPIO_BASE_3 + GPIO_INTERRUPT_STATUS))
 181
 182 #define GPIO_DATA_INPUT_4            ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_INPUT))
 183 #define GPIO_DATA_OUTPUT_4           ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DATA_OUTPUT))
 184 #define GPIO_DIRECTION_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_DIRECTION_CONTROL))
 185 #define GPIO_INTERRUPT_CONTROL_4     ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_CONTROL))
 186 #define GPIO_INTERRUPT_MASK_4        ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_MASK))
 187 #define GPIO_INTERRUPT_STATUS_4      ((unsigned int)(OMAP730_GPIO_BASE_4 + GPIO_INTERRUPT_STATUS))
 188
 189 #define GPIO_DATA_INPUT_5            ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_INPUT))
 190 #define GPIO_DATA_OUTPUT_5           ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DATA_OUTPUT))
 191 #define GPIO_DIRECTION_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_DIRECTION_CONTROL))
 192 #define GPIO_INTERRUPT_CONTROL_5     ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_CONTROL))
 193 #define GPIO_INTERRUPT_MASK_5        ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_MASK))
 194 #define GPIO_INTERRUPT_STATUS_5      ((unsigned int)(OMAP730_GPIO_BASE_5 + GPIO_INTERRUPT_STATUS))
 195
 196 #define GPIO_DATA_INPUT_6            ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_INPUT))
 197 #define GPIO_DATA_OUTPUT_6           ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DATA_OUTPUT))
 198 #define GPIO_DIRECTION_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_DIRECTION_CONTROL))
 199 #define GPIO_INTERRUPT_CONTROL_6     ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_CONTROL))
 200 #define GPIO_INTERRUPT_MASK_6        ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_MASK))
 201 #define GPIO_INTERRUPT_STATUS_6      ((unsigned int)(OMAP730_GPIO_BASE_6 + GPIO_INTERRUPT_STATUS))
 202
 203 /***************************************************************************
 204  * OMAP730 Watchdog timers
 205  **************************************************************************/
 206
 207 #define WDTIM_BASE                 0xFFFEC800
 208 #define WDTIM_CONTROL              (WDTIM_BASE + 0x00)    /* MPU_CNTL_TIMER */
 209 #define WDTIM_LOAD                 (WDTIM_BASE + 0x04)    /* MPU_LOAD_TIMER */
 210 #define WDTIM_READ                 (WDTIM_BASE + 0x04)    /* MPU_READ_TIMER */
 211 #define WDTIM_MODE                 (WDTIM_BASE + 0x08)    /* MPU_TIMER_MODE */
 212
 213 /***************************************************************************
 214  * OMAP730 Interrupt Registers
 215  **************************************************************************/
 216
 217 /* Interrupt Register offsets */
 218
 219 #define IRQ_ITR                               0x00
 220 #define IRQ_MIR                               0x04
 221 #define IRQ_SIR_IRQ                           0x10
 222 #define IRQ_SIR_FIQ                           0x14
 223 #define IRQ_CONTROL_REG                       0x18
 224 #define IRQ_ILR0                              0x1C  /* ILRx == ILR0 + (0x4 * x) */
 225 #define IRQ_SIR                               0x9C  /* a.k.a.IRQ_ISR */
 226 #define IRQ_GMIR                              0xA0
 227
 228 #define REG_IHL1_MIR  (OMAP_IH1_BASE + IRQ_MIR)
 229 #define REG_IHL2_MIR  (OMAP_IH2_BASE + IRQ_MIR)
 230
 231 /***************************************************************************
 232  * OMAP730 Intersystem Communication Register                      (TRM 4.5)
 233  **************************************************************************/
 234
 235 #define ICR_BASE                   0xFFFBB800
 236
 237 #define M_ICR                      (ICR_BASE + 0x00)
 238 #define G_ICR                      (ICR_BASE + 0x02)
 239 #define M_CTL                      (ICR_BASE + 0x04)
 240 #define G_CTL                      (ICR_BASE + 0x06)
 241 #define PM_BA                      (ICR_BASE + 0x0A)
 242 #define DM_BA                      (ICR_BASE + 0x0C)
 243 #define RM_BA                      (ICR_BASE + 0x0E)
 244 #define SSPI_TAS                   (ICR_BASE + 0x12)
 245
 246 #endif /* ! __INCLUDED_OMAP730_H */