include/configs/p1_twr.h

   1 /* SPDX-License-Identifier: GPL-2.0+ */
   2 /*
   3  * Copyright 2013 Freescale Semiconductor, Inc.
   4  */
   5
   6 /*
   7  * QorIQ P1 Tower boards configuration file
   8  */
   9 #ifndef __CONFIG_H
  10 #define __CONFIG_H
  11
  12 #if defined(CONFIG_TWR_P1025)
  13 #define CONFIG_BOARDNAME "TWR-P1025"
  14 #define CONFIG_SYS_LBC_LBCR     0x00080000      /* Conversion of LBC addr */
  15 #define CONFIG_SYS_LBC_LCRR     0x80000002      /* LB clock ratio reg */
  16 #endif
  17
  18 #ifdef CONFIG_SDCARD
  19 #define CONFIG_RAMBOOT_SDCARD
  20 #define CONFIG_SYS_RAMBOOT
  21 #define CONFIG_RESET_VECTOR_ADDRESS     0x110bfffc
  22 #endif
  23
  24 #ifndef CONFIG_RESET_VECTOR_ADDRESS
  25 #define CONFIG_RESET_VECTOR_ADDRESS     0xeffffffc
  26 #endif
  27
  28 #ifndef CONFIG_SYS_MONITOR_BASE
  29 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE    /* start of monitor */
  30 #endif
  31
  32 #define CONFIG_PCIE1    /* PCIE controller 1 (slot 1) */
  33 #define CONFIG_PCIE2    /* PCIE controller 2 (slot 2) */
  34 #define CONFIG_FSL_PCI_INIT     /* Use common FSL init code */
  35 #define CONFIG_PCI_INDIRECT_BRIDGE      /* indirect PCI bridge support */
  36 #define CONFIG_SYS_PCI_64BIT    /* enable 64-bit PCI resources */
  37
  38 #define CONFIG_ENV_OVERWRITE
  39
  40 #define CONFIG_SYS_SATA_MAX_DEVICE      2
  41 #define CONFIG_LBA48
  42
  43 #ifndef __ASSEMBLY__
  44 extern unsigned long get_board_sys_clk(unsigned long dummy);
  45 #endif
  46 #define CONFIG_SYS_CLK_FREQ     get_board_sys_clk(0) /*sysclk for TWR-P1025 */
  47
  48 #define CONFIG_DDR_CLK_FREQ     66666666
  49
  50 #define CONFIG_HWCONFIG
  51 /*
  52  * These can be toggled for performance analysis, otherwise use default.
  53  */
  54 #define CONFIG_L2_CACHE
  55 #define CONFIG_BTB
  56
  57 #define CONFIG_SYS_CCSRBAR              0xffe00000
  58 #define CONFIG_SYS_CCSRBAR_PHYS_LOW     CONFIG_SYS_CCSRBAR
  59
  60 /* DDR Setup */
  61
  62 #define CONFIG_SYS_SDRAM_SIZE_LAW       LAW_SIZE_512M
  63 #define CONFIG_CHIP_SELECTS_PER_CTRL    1
  64
  65 #define CONFIG_SYS_SDRAM_SIZE           (1u << (CONFIG_SYS_SDRAM_SIZE_LAW - 19))
  66 #define CONFIG_SYS_DDR_SDRAM_BASE       0x00000000
  67 #define CONFIG_SYS_SDRAM_BASE           CONFIG_SYS_DDR_SDRAM_BASE
  68
  69 #define CONFIG_DIMM_SLOTS_PER_CTLR      1
  70
  71 /* Default settings for DDR3 */
  72 #define CONFIG_SYS_DDR_CS0_BNDS         0x0000001f
  73 #define CONFIG_SYS_DDR_CS0_CONFIG       0x80014202
  74 #define CONFIG_SYS_DDR_CS0_CONFIG_2     0x00000000
  75 #define CONFIG_SYS_DDR_CS1_BNDS         0x00000000
  76 #define CONFIG_SYS_DDR_CS1_CONFIG       0x00000000
  77 #define CONFIG_SYS_DDR_CS1_CONFIG_2     0x00000000
  78
  79 #define CONFIG_SYS_DDR_DATA_INIT        0xdeadbeef
  80 #define CONFIG_SYS_DDR_INIT_ADDR        0x00000000
  81 #define CONFIG_SYS_DDR_INIT_EXT_ADDR    0x00000000
  82 #define CONFIG_SYS_DDR_MODE_CONTROL     0x00000000
  83
  84 #define CONFIG_SYS_DDR_ZQ_CONTROL       0x89080600
  85 #define CONFIG_SYS_DDR_WRLVL_CONTROL    0x8655a608
  86 #define CONFIG_SYS_DDR_SR_CNTR          0x00000000
  87 #define CONFIG_SYS_DDR_RCW_1            0x00000000
  88 #define CONFIG_SYS_DDR_RCW_2            0x00000000
  89 #define CONFIG_SYS_DDR_CONTROL          0xc70c0000      /* Type = DDR3  */
  90 #define CONFIG_SYS_DDR_CONTROL_2        0x04401050
  91 #define CONFIG_SYS_DDR_TIMING_4         0x00220001
  92 #define CONFIG_SYS_DDR_TIMING_5         0x03402400
  93
  94 #define CONFIG_SYS_DDR_TIMING_3         0x00020000
  95 #define CONFIG_SYS_DDR_TIMING_0         0x00220004
  96 #define CONFIG_SYS_DDR_TIMING_1         0x5c5b6544
  97 #define CONFIG_SYS_DDR_TIMING_2         0x0fa880de
  98 #define CONFIG_SYS_DDR_CLK_CTRL         0x03000000
  99 #define CONFIG_SYS_DDR_MODE_1           0x80461320
 100 #define CONFIG_SYS_DDR_MODE_2           0x00008000
 101 #define CONFIG_SYS_DDR_INTERVAL         0x09480000
 102
 103 /*
 104  * Memory map
 105  *
 106  * 0x0000_0000 0x1fff_ffff      DDR             Up to 512MB cacheable
 107  * 0x8000_0000 0xdfff_ffff      PCI Express Mem 1.5G non-cacheable(PCIe * 3)
 108  * 0xffc0_0000 0xffc3_ffff      PCI IO range    256k non-cacheable
 109  *
 110  * Localbus
 111  * 0xe000_0000 0xe002_0000      SSD1289         128K non-cacheable
 112  * 0xec00_0000 0xefff_ffff      FLASH           Up to 64M non-cacheable
 113  *
 114  * 0xff90_0000 0xff97_ffff      L2 SRAM         Up to 512K cacheable
 115  * 0xffd0_0000 0xffd0_3fff      init ram        16K Cacheable
 116  * 0xffe0_0000 0xffef_ffff      CCSR            1M non-cacheable
 117  */
 118
 119 /*
 120  * Local Bus Definitions
 121  */
 122 #define CONFIG_SYS_MAX_FLASH_SECT       512     /* 64M */
 123 #define CONFIG_SYS_FLASH_BASE           0xec000000
 124
 125 #define CONFIG_SYS_FLASH_BASE_PHYS      CONFIG_SYS_FLASH_BASE
 126
 127 #define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS)) \
 128         | BR_PS_16 | BR_V)
 129
 130 #define CONFIG_FLASH_OR_PRELIM  0xfc0000b1
 131
 132 #define CONFIG_SYS_SSD_BASE     0xe0000000
 133 #define CONFIG_SYS_SSD_BASE_PHYS        CONFIG_SYS_SSD_BASE
 134 #define CONFIG_SSD_BR_PRELIM    (BR_PHYS_ADDR(CONFIG_SYS_SSD_BASE_PHYS) | \
 135                                         BR_PS_16 | BR_V)
 136 #define CONFIG_SSD_OR_PRELIM    (OR_AM_64KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
 137                                  OR_GPCM_ACS_DIV2 | OR_GPCM_SCY | \
 138                                  OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
 139
 140 #define CONFIG_SYS_BR2_PRELIM CONFIG_SSD_BR_PRELIM
 141 #define CONFIG_SYS_OR2_PRELIM CONFIG_SSD_OR_PRELIM
 142
 143 #define CONFIG_SYS_FLASH_BANKS_LIST     {CONFIG_SYS_FLASH_BASE_PHYS}
 144 #define CONFIG_SYS_FLASH_QUIET_TEST
 145 #define CONFIG_FLASH_SHOW_PROGRESS      45      /* count down from 45/5: 9..1 */
 146
 147 #define CONFIG_SYS_MAX_FLASH_BANKS      1       /* number of banks */
 148
 149 #undef CONFIG_SYS_FLASH_CHECKSUM
 150 #define CONFIG_SYS_FLASH_ERASE_TOUT     60000   /* Flash Erase Timeout (ms) */
 151 #define CONFIG_SYS_FLASH_WRITE_TOUT     500     /* Flash Write Timeout (ms) */
 152
 153 #define CONFIG_SYS_FLASH_EMPTY_INFO
 154
 155 #define CONFIG_SYS_INIT_RAM_LOCK
 156 #define CONFIG_SYS_INIT_RAM_ADDR        0xffd00000
 157 /* Initial L1 address */
 158 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS   CONFIG_SYS_INIT_RAM_ADDR
 159 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0
 160 #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS
 161 /* Size of used area in RAM */
 162 #define CONFIG_SYS_INIT_RAM_SIZE        0x00004000
 163
 164 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 165                                         GENERATED_GBL_DATA_SIZE)
 166 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 167
 168 #define CONFIG_SYS_MONITOR_LEN  (768 * 1024)
 169 #define CONFIG_SYS_MALLOC_LEN   (1024 * 1024)/* Reserved for malloc */
 170
 171 #define CONFIG_SYS_BR0_PRELIM   CONFIG_FLASH_BR_PRELIM  /* NOR Base Address */
 172 #define CONFIG_SYS_OR0_PRELIM   CONFIG_FLASH_OR_PRELIM  /* NOR Options */
 173
 174 /* Serial Port
 175  * open - index 2
 176  * shorted - index 1
 177  */
 178 #undef CONFIG_SERIAL_SOFTWARE_FIFO
 179 #define CONFIG_SYS_NS16550_SERIAL
 180 #define CONFIG_SYS_NS16550_REG_SIZE     1
 181 #define CONFIG_SYS_NS16550_CLK          get_bus_freq(0)
 182
 183 #define CONFIG_SYS_BAUDRATE_TABLE       \
 184         {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
 185
 186 #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
 187 #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
 188
 189 /* I2C */
 190 #define CONFIG_SYS_I2C
 191 #define CONFIG_SYS_I2C_FSL                      /* Use FSL common I2C driver */
 192 #define CONFIG_SYS_FSL_I2C_SPEED        400000  /* I2C spd and slave address */
 193 #define CONFIG_SYS_FSL_I2C_SLAVE        0x7F
 194 #define CONFIG_SYS_FSL_I2C_OFFSET       0x3000
 195 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52
 196
 197 /*
 198  * I2C2 EEPROM
 199  */
 200 #define CONFIG_SYS_FSL_I2C2_SPEED       400000  /* I2C spd and slave address */
 201 #define CONFIG_SYS_FSL_I2C2_SLAVE       0x7F
 202 #define CONFIG_SYS_FSL_I2C2_OFFSET      0x3100
 203
 204 #define CONFIG_SYS_I2C_PCA9555_ADDR     0x23
 205
 206 /* enable read and write access to EEPROM */
 207 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
 208 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 209 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
 210
 211 #if defined(CONFIG_PCI)
 212 /*
 213  * General PCI
 214  * Memory space is mapped 1-1, but I/O space must start from 0.
 215  */
 216
 217 /* controller 2, direct to uli, tgtid 2, Base address 9000 */
 218 #define CONFIG_SYS_PCIE2_NAME           "TWR-ELEV PCIe SLOT"
 219 #define CONFIG_SYS_PCIE2_MEM_VIRT       0xa0000000
 220 #define CONFIG_SYS_PCIE2_MEM_BUS        0xa0000000
 221 #define CONFIG_SYS_PCIE2_MEM_PHYS       0xa0000000
 222 #define CONFIG_SYS_PCIE2_MEM_SIZE       0x20000000      /* 512M */
 223 #define CONFIG_SYS_PCIE2_IO_VIRT        0xffc10000
 224 #define CONFIG_SYS_PCIE2_IO_BUS         0x00000000
 225 #define CONFIG_SYS_PCIE2_IO_PHYS        0xffc10000
 226 #define CONFIG_SYS_PCIE2_IO_SIZE        0x00010000      /* 64k */
 227
 228 /* controller 1, tgtid 1, Base address a000 */
 229 #define CONFIG_SYS_PCIE1_NAME           "mini PCIe SLOT"
 230 #define CONFIG_SYS_PCIE1_MEM_VIRT       0x80000000
 231 #define CONFIG_SYS_PCIE1_MEM_BUS        0x80000000
 232 #define CONFIG_SYS_PCIE1_MEM_PHYS       0x80000000
 233 #define CONFIG_SYS_PCIE1_MEM_SIZE       0x20000000      /* 512M */
 234 #define CONFIG_SYS_PCIE1_IO_VIRT        0xffc00000
 235 #define CONFIG_SYS_PCIE1_IO_BUS         0x00000000
 236 #define CONFIG_SYS_PCIE1_IO_PHYS        0xffc00000
 237 #define CONFIG_SYS_PCIE1_IO_SIZE        0x00010000      /* 64k */
 238
 239 #define CONFIG_PCI_SCAN_SHOW    /* show pci devices on startup */
 240 #endif /* CONFIG_PCI */
 241
 242 #if defined(CONFIG_TSEC_ENET)
 243
 244 #define CONFIG_TSEC1
 245 #define CONFIG_TSEC1_NAME       "eTSEC1"
 246 #undef CONFIG_TSEC2
 247 #undef CONFIG_TSEC2_NAME
 248 #define CONFIG_TSEC3
 249 #define CONFIG_TSEC3_NAME       "eTSEC3"
 250
 251 #define TSEC1_PHY_ADDR  2
 252 #define TSEC2_PHY_ADDR  0
 253 #define TSEC3_PHY_ADDR  1
 254
 255 #define TSEC1_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 256 #define TSEC2_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 257 #define TSEC3_FLAGS     (TSEC_GIGABIT | TSEC_REDUCED)
 258
 259 #define TSEC1_PHYIDX    0
 260 #define TSEC2_PHYIDX    0
 261 #define TSEC3_PHYIDX    0
 262
 263 #define CONFIG_ETHPRIME "eTSEC1"
 264
 265 #define CONFIG_HAS_ETH0
 266 #define CONFIG_HAS_ETH1
 267 #undef CONFIG_HAS_ETH2
 268 #endif /* CONFIG_TSEC_ENET */
 269
 270 #ifdef CONFIG_QE
 271 /* QE microcode/firmware address */
 272 #define CONFIG_SYS_QE_FW_ADDR   0xefec0000
 273 #define CONFIG_SYS_QE_FMAN_FW_LENGTH    0x10000
 274 #endif /* CONFIG_QE */
 275
 276 #ifdef CONFIG_TWR_P1025
 277 /*
 278  * QE UEC ethernet configuration
 279  */
 280 #define CONFIG_MIIM_ADDRESS     (CONFIG_SYS_CCSRBAR + 0x82120)
 281
 282 #undef CONFIG_UEC_ETH
 283 #define CONFIG_PHY_MODE_NEED_CHANGE
 284
 285 #define CONFIG_UEC_ETH1 /* ETH1 */
 286 #define CONFIG_HAS_ETH0
 287
 288 #ifdef CONFIG_UEC_ETH1
 289 #define CONFIG_SYS_UEC1_UCC_NUM 0       /* UCC1 */
 290 #define CONFIG_SYS_UEC1_RX_CLK  QE_CLK12 /* CLK12 for MII */
 291 #define CONFIG_SYS_UEC1_TX_CLK  QE_CLK9 /* CLK9 for MII */
 292 #define CONFIG_SYS_UEC1_ETH_TYPE        FAST_ETH
 293 #define CONFIG_SYS_UEC1_PHY_ADDR        0x18    /* 0x18 for MII */
 294 #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII
 295 #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100
 296 #endif /* CONFIG_UEC_ETH1 */
 297
 298 #define CONFIG_UEC_ETH5 /* ETH5 */
 299 #define CONFIG_HAS_ETH1
 300
 301 #ifdef CONFIG_UEC_ETH5
 302 #define CONFIG_SYS_UEC5_UCC_NUM 4       /* UCC5 */
 303 #define CONFIG_SYS_UEC5_RX_CLK  QE_CLK_NONE
 304 #define CONFIG_SYS_UEC5_TX_CLK  QE_CLK13 /* CLK 13 for RMII */
 305 #define CONFIG_SYS_UEC5_ETH_TYPE        FAST_ETH
 306 #define CONFIG_SYS_UEC5_PHY_ADDR        0x19    /* 0x19 for RMII */
 307 #define CONFIG_SYS_UEC5_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII
 308 #define CONFIG_SYS_UEC5_INTERFACE_SPEED 100
 309 #endif /* CONFIG_UEC_ETH5 */
 310 #endif /* CONFIG_TWR-P1025 */
 311
 312 /*
 313  * Dynamic MTD Partition support with mtdparts
 314  */
 315
 316 /*
 317  * Environment
 318  */
 319 #ifdef CONFIG_SYS_RAMBOOT
 320 #ifdef CONFIG_RAMBOOT_SDCARD
 321 #define CONFIG_SYS_MMC_ENV_DEV  0
 322 #endif
 323 #endif
 324
 325 #define CONFIG_LOADS_ECHO               /* echo on for serial download */
 326 #define CONFIG_SYS_LOADS_BAUD_CHANGE    /* allow baudrate change */
 327
 328 /*
 329  * USB
 330  */
 331 #define CONFIG_HAS_FSL_DR_USB
 332
 333 #if defined(CONFIG_HAS_FSL_DR_USB)
 334 #ifdef CONFIG_USB_EHCI_HCD
 335 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET
 336 #define CONFIG_USB_EHCI_FSL
 337 #endif
 338 #endif
 339
 340 #ifdef CONFIG_MMC
 341 #define CONFIG_SYS_FSL_ESDHC_ADDR       CONFIG_SYS_MPC85xx_ESDHC_ADDR
 342 #endif
 343
 344 #undef CONFIG_WATCHDOG  /* watchdog disabled */
 345
 346 /*
 347  * Miscellaneous configurable options
 348  */
 349 #define CONFIG_SYS_LOAD_ADDR    0x2000000       /* default load address */
 350
 351 /*
 352  * For booting Linux, the board info and command line data
 353  * have to be in the first 64 MB of memory, since this is
 354  * the maximum mapped by the Linux kernel during initialization.
 355  */
 356 #define CONFIG_SYS_BOOTMAPSZ    (64 << 20)      /* Initial Memory for Linux*/
 357 #define CONFIG_SYS_BOOTM_LEN    (64 << 20)      /* Increase max gunzip size */
 358
 359 /*
 360  * Environment Configuration
 361  */
 362 #define CONFIG_HOSTNAME         "unknown"
 363 #define CONFIG_ROOTPATH         "/opt/nfsroot"
 364 #define CONFIG_BOOTFILE         "uImage"
 365 #define CONFIG_UBOOTPATH        u-boot.bin /* U-Boot image on TFTP server */
 366
 367 /* default location for tftp and bootm */
 368 #define CONFIG_LOADADDR 1000000
 369
 370 #define CONFIG_EXTRA_ENV_SETTINGS       \
 371 "netdev=eth0\0" \
 372 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0"     \
 373 "loadaddr=1000000\0"    \
 374 "bootfile=uImage\0"     \
 375 "dtbfile=twr-p1025twr.dtb\0"    \
 376 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 377 "qefirmwarefile=fsl_qe_ucode_1021_10_A.bin\0"   \
 378 "tftpflash=tftpboot $loadaddr $uboot; " \
 379         "protect off " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 380         "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; "      \
 381         "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize; " \
 382         "protect on " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
 383         "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
 384 "kernelflash=tftpboot $loadaddr $bootfile; "    \
 385         "protect off 0xefa80000 +$filesize; "   \
 386         "erase 0xefa80000 +$filesize; " \
 387         "cp.b $loadaddr 0xefa80000 $filesize; " \
 388         "protect on 0xefa80000 +$filesize; "    \
 389         "cmp.b $loadaddr 0xefa80000 $filesize\0"        \
 390 "dtbflash=tftpboot $loadaddr $dtbfile; "        \
 391         "protect off 0xefe80000 +$filesize; "   \
 392         "erase 0xefe80000 +$filesize; " \
 393         "cp.b $loadaddr 0xefe80000 $filesize; " \
 394         "protect on 0xefe80000 +$filesize; "    \
 395         "cmp.b $loadaddr 0xefe80000 $filesize\0"        \
 396 "ramdiskflash=tftpboot $loadaddr $ramdiskfile; "        \
 397         "protect off 0xeeb80000 +$filesize; "   \
 398         "erase 0xeeb80000 +$filesize; " \
 399         "cp.b $loadaddr 0xeeb80000 $filesize; " \
 400         "protect on 0xeeb80000 +$filesize; "    \
 401         "cmp.b $loadaddr 0xeeb80000 $filesize\0"        \
 402 "qefirmwareflash=tftpboot $loadaddr $qefirmwarefile; "  \
 403         "protect off 0xefec0000 +$filesize; "   \
 404         "erase 0xefec0000 +$filesize; " \
 405         "cp.b $loadaddr 0xefec0000 $filesize; " \
 406         "protect on 0xefec0000 +$filesize; "    \
 407         "cmp.b $loadaddr 0xefec0000 $filesize\0"        \
 408 "consoledev=ttyS0\0"    \
 409 "ramdiskaddr=2000000\0" \
 410 "ramdiskfile=rootfs.ext2.gz.uboot\0"    \
 411 "fdtaddr=1e00000\0"     \
 412 "bdev=sda1\0"   \
 413 "norbootaddr=ef080000\0"        \
 414 "norfdtaddr=ef040000\0" \
 415 "ramdisk_size=120000\0" \
 416 "usbboot=setenv bootargs root=/dev/sda1 rw rootdelay=5 " \
 417 "console=$consoledev,$baudrate $othbootargs ; bootm 0xefa80000 - 0xefe80000"
 418
 419 #define CONFIG_NFSBOOTCOMMAND   \
 420 "setenv bootargs root=/dev/nfs rw "     \
 421 "nfsroot=$serverip:$rootpath "  \
 422 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
 423 "console=$consoledev,$baudrate $othbootargs;" \
 424 "tftp $loadaddr $bootfile&&"    \
 425 "tftp $fdtaddr $fdtfile&&"      \
 426 "bootm $loadaddr - $fdtaddr"
 427
 428 #define CONFIG_HDBOOT   \
 429 "setenv bootargs root=/dev/$bdev rw rootdelay=30 "      \
 430 "console=$consoledev,$baudrate $othbootargs;" \
 431 "usb start;"    \
 432 "ext2load usb 0:1 $loadaddr /boot/$bootfile;"   \
 433 "ext2load usb 0:1 $fdtaddr /boot/$fdtfile;"     \
 434 "bootm $loadaddr - $fdtaddr"
 435
 436 #define CONFIG_USB_FAT_BOOT     \
 437 "setenv bootargs root=/dev/ram rw "     \
 438 "console=$consoledev,$baudrate $othbootargs " \
 439 "ramdisk_size=$ramdisk_size;"   \
 440 "usb start;"    \
 441 "fatload usb 0:2 $loadaddr $bootfile;"  \
 442 "fatload usb 0:2 $fdtaddr $fdtfile;"    \
 443 "fatload usb 0:2 $ramdiskaddr $ramdiskfile;"    \
 444 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 445
 446 #define CONFIG_USB_EXT2_BOOT    \
 447 "setenv bootargs root=/dev/ram rw "     \
 448 "console=$consoledev,$baudrate $othbootargs " \
 449 "ramdisk_size=$ramdisk_size;"   \
 450 "usb start;"    \
 451 "ext2load usb 0:4 $loadaddr $bootfile;" \
 452 "ext2load usb 0:4 $fdtaddr $fdtfile;" \
 453 "ext2load usb 0:4 $ramdiskaddr $ramdiskfile;" \
 454 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 455
 456 #define CONFIG_NORBOOT  \
 457 "setenv bootargs root=/dev/mtdblock3 rw "       \
 458 "console=$consoledev,$baudrate rootfstype=jffs2 $othbootargs;"  \
 459 "bootm $norbootaddr - $norfdtaddr"
 460
 461 #define CONFIG_RAMBOOTCOMMAND_TFTP      \
 462 "setenv bootargs root=/dev/ram rw "     \
 463 "console=$consoledev,$baudrate $othbootargs " \
 464 "ramdisk_size=$ramdisk_size;"   \
 465 "tftp $ramdiskaddr $ramdiskfile;"       \
 466 "tftp $loadaddr $bootfile;"     \
 467 "tftp $fdtaddr $fdtfile;"       \
 468 "bootm $loadaddr $ramdiskaddr $fdtaddr"
 469
 470 #define CONFIG_RAMBOOTCOMMAND   \
 471 "setenv bootargs root=/dev/ram rw "     \
 472 "console=$consoledev,$baudrate $othbootargs " \
 473 "ramdisk_size=$ramdisk_size;"   \
 474 "bootm 0xefa80000 0xeeb80000 0xefe80000"
 475
 476 #define CONFIG_BOOTCOMMAND      CONFIG_RAMBOOTCOMMAND
 477
 478 #endif /* __CONFIG_H */