include/configs/palmtreo680.h

   1 /*
   2  * Palm Treo 680 configuration file
   3  *
   4  * Copyright (C) 2013 Mike Dunn <mikedunn@newsguy.com>
   5  *
   6  * This file is released under the terms of GPL v2 and any later version.
   7  * See the file COPYING in the root directory of the source tree for details.
   8  *
   9  */
  10
  11 #ifndef __CONFIG_H
  12 #define __CONFIG_H
  13
  14 /*
  15  * High Level Board Configuration Options
  16  */
  17 #define CONFIG_CPU_PXA27X
  18 #define CONFIG_PALMTREO680
  19 #define CONFIG_MACH_TYPE                MACH_TYPE_TREO680
  20
  21 #define CONFIG_SYS_MALLOC_LEN           (4096*1024)
  22
  23 #define CONFIG_LZMA
  24
  25 /*
  26  * Serial Console Configuration
  27  */
  28 #define CONFIG_PXA_SERIAL
  29 #define CONFIG_FFUART                   1
  30 #define CONFIG_BAUDRATE                 9600
  31 #define CONFIG_SYS_BAUDRATE_TABLE       { 9600, 19200, 38400, 57600, 115200 }
  32 #define CONFIG_CONS_INDEX               3
  33
  34 /* we have nand (although technically nand *is* flash...) */
  35 #define CONFIG_SYS_NO_FLASH
  36
  37 #define CONFIG_LCD
  38 /* #define CONFIG_KEYBOARD */  /* TODO */
  39
  40 /*
  41  * Bootloader Components Configuration
  42  */
  43 #include <config_cmd_default.h>
  44 #undef  CONFIG_CMD_FPGA
  45 #undef  CONFIG_CMD_LOADS
  46 #undef  CONFIG_CMD_NET
  47 #undef  CONFIG_CMD_NFS
  48 #undef  CONFIG_CMD_IMLS
  49 #undef  CONFIG_CMD_FLASH
  50 #undef  CONFIG_CMD_SETGETDCR
  51 #undef  CONFIG_CMD_SOURCE
  52 #undef  CONFIG_CMD_XIMG
  53
  54 #define CONFIG_CMD_ENV
  55 #define CONFIG_CMD_MMC
  56 #define CONFIG_CMD_NAND
  57
  58 #define CONFIG_CMDLINE_TAG
  59 #define CONFIG_SETUP_MEMORY_TAGS
  60
  61 /*
  62  * MMC Card Configuration
  63  */
  64 #ifdef CONFIG_CMD_MMC
  65 #define CONFIG_MMC
  66 #define CONFIG_GENERIC_MMC
  67 #define CONFIG_PXA_MMC_GENERIC
  68
  69 #define CONFIG_CMD_FAT
  70 #define CONFIG_CMD_EXT2
  71 #define CONFIG_DOS_PARTITION
  72 #endif
  73
  74 /*
  75  * LCD
  76  */
  77 #ifdef CONFIG_LCD
  78 #define CONFIG_PXA_LCD
  79 #define CONFIG_ACX544AKN
  80 #define CONFIG_LCD_LOGO
  81 #define CONFIG_SYS_LCD_PXA_NO_L_BIAS /* don't configure GPIO77 as L_BIAS */
  82 #define LCD_BPP LCD_COLOR16
  83 #define CONFIG_FB_ADDR 0x5c000000    /* internal SRAM */
  84 #define CONFIG_CMD_BMP
  85 #define CONFIG_SPLASH_SCREEN         /* requires "splashimage" env var */
  86 #define CONFIG_SPLASH_SCREEN_ALIGN   /* requires "splashpos" env var */
  87 #define CONFIG_VIDEO_BMP_GZIP
  88 #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  (2 << 20)
  89
  90 #endif
  91
  92 /*
  93  * KGDB
  94  */
  95 #ifdef CONFIG_CMD_KGDB
  96 #define CONFIG_KGDB_BAUDRATE            230400  /* kgdb serial port speed */
  97 #endif
  98
  99 /*
 100  * HUSH Shell Configuration
 101  */
 102 #define CONFIG_SYS_HUSH_PARSER          1
 103 #define CONFIG_SYS_PROMPT_HUSH_PS2      "> "
 104
 105 #define CONFIG_SYS_LONGHELP
 106 #ifdef CONFIG_SYS_HUSH_PARSER
 107 #define CONFIG_SYS_PROMPT               "$ "
 108 #else
 109 #endif
 110 #define CONFIG_SYS_CBSIZE               256
 111 #define CONFIG_SYS_PBSIZE               \
 112         (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
 113 #define CONFIG_SYS_MAXARGS              16
 114 #define CONFIG_SYS_BARGSIZE             CONFIG_SYS_CBSIZE
 115 #define CONFIG_SYS_DEVICE_NULLDEV       1
 116
 117 /*
 118  * Clock Configuration
 119  */
 120 #define CONFIG_SYS_CPUSPEED             0x210           /* 416MHz ; N=2,L=16 */
 121
 122 /*
 123  * Stack sizes
 124  */
 125 #define CONFIG_STACKSIZE                (128*1024)      /* regular stack */
 126 #ifdef CONFIG_USE_IRQ
 127 #define CONFIG_STACKSIZE_IRQ            (4*1024)        /* IRQ stack */
 128 #define CONFIG_STACKSIZE_FIQ            (4*1024)        /* FIQ stack */
 129 #endif
 130
 131 /*
 132  * DRAM Map
 133  */
 134 #define CONFIG_NR_DRAM_BANKS            1               /* 1 bank of DRAM */
 135 #define PHYS_SDRAM_1                    0xa0000000      /* SDRAM Bank #1 */
 136 #define PHYS_SDRAM_1_SIZE               0x04000000      /* 64 MB */
 137
 138 #define CONFIG_SYS_DRAM_BASE            0xa0000000
 139 #define CONFIG_SYS_DRAM_SIZE            0x04000000      /* 64 MB DRAM */
 140
 141 #define CONFIG_SYS_MEMTEST_START        0xa0400000      /* memtest works on */
 142 #define CONFIG_SYS_MEMTEST_END          0xa0800000      /* 4 ... 8 MB in DRAM */
 143 #define CONFIG_SYS_LOAD_ADDR            CONFIG_SYS_DRAM_BASE
 144 #define CONFIG_SYS_SDRAM_BASE           PHYS_SDRAM_1
 145
 146 /*
 147  * GPIO settings
 148  */
 149 #define CONFIG_SYS_GAFR0_L_VAL  0x0E000000
 150 #define CONFIG_SYS_GAFR0_U_VAL  0xA500001A
 151 #define CONFIG_SYS_GAFR1_L_VAL  0x60000002
 152 #define CONFIG_SYS_GAFR1_U_VAL  0xAAA07959
 153 #define CONFIG_SYS_GAFR2_L_VAL  0x02AAAAAA
 154 #define CONFIG_SYS_GAFR2_U_VAL  0x41440F08
 155 #define CONFIG_SYS_GAFR3_L_VAL  0x56AA95FF
 156 #define CONFIG_SYS_GAFR3_U_VAL  0x00001401
 157 #define CONFIG_SYS_GPCR0_VAL    0x1FF80400
 158 #define CONFIG_SYS_GPCR1_VAL    0x03003FC1
 159 #define CONFIG_SYS_GPCR2_VAL    0x01C1E000
 160 #define CONFIG_SYS_GPCR3_VAL    0x01C1E000
 161 #define CONFIG_SYS_GPDR0_VAL    0xCFF90400
 162 #define CONFIG_SYS_GPDR1_VAL    0xFB22BFC1
 163 #define CONFIG_SYS_GPDR2_VAL    0x93CDFFDF
 164 #define CONFIG_SYS_GPDR3_VAL    0x0069FF81
 165 #define CONFIG_SYS_GPSR0_VAL    0x02000018
 166 #define CONFIG_SYS_GPSR1_VAL    0x00000000
 167 #define CONFIG_SYS_GPSR2_VAL    0x000C0000
 168 #define CONFIG_SYS_GPSR3_VAL    0x00080000
 169
 170 #define CONFIG_SYS_PSSR_VAL     0x30
 171
 172 /*
 173  * Clock settings
 174  */
 175 #define CONFIG_SYS_CKEN         0x01ffffff
 176 #define CONFIG_SYS_CCCR         0x02000210
 177
 178 /*
 179  * Memory settings
 180  */
 181 #define CONFIG_SYS_MSC0_VAL     0x7ff844c8
 182 #define CONFIG_SYS_MSC1_VAL     0x7ff86ab4
 183 #define CONFIG_SYS_MSC2_VAL     0x7ff87ff8
 184 #define CONFIG_SYS_MDCNFG_VAL   0x0B880acd
 185 #define CONFIG_SYS_MDREFR_VAL   0x201fa031
 186 #define CONFIG_SYS_MDMRS_VAL    0x00320032
 187 #define CONFIG_SYS_FLYCNFG_VAL  0x00000000
 188 #define CONFIG_SYS_SXCNFG_VAL   0x40044004
 189 #define CONFIG_SYS_MECR_VAL     0x00000003
 190 #define CONFIG_SYS_MCMEM0_VAL   0x0001c391
 191 #define CONFIG_SYS_MCMEM1_VAL   0x0001c391
 192 #define CONFIG_SYS_MCATT0_VAL   0x0001c391
 193 #define CONFIG_SYS_MCATT1_VAL   0x0001c391
 194 #define CONFIG_SYS_MCIO0_VAL    0x00014611
 195 #define CONFIG_SYS_MCIO1_VAL    0x0001c391
 196
 197 /*
 198  * USB
 199  */
 200 #define CONFIG_USB_DEVICE
 201 #define CONFIG_USB_TTY
 202 #define CONFIG_USB_DEV_PULLUP_GPIO 114
 203
 204 /*
 205  * SPL
 206  */
 207 #define CONFIG_SPL_TEXT_BASE    0xa1700000 /* IPL loads SPL here */
 208 #define CONFIG_SPL_STACK        0x5c040000 /* end of internal SRAM */
 209 #define CONFIG_SPL_NAND_SUPPORT /* build libnand for spl */
 210 #define CONFIG_SPL_NAND_DOCG4   /* use lean docg4 nand spl driver */
 211 #define CONFIG_SPL_LIBGENERIC_SUPPORT  /* spl uses memcpy */
 212
 213 /*
 214  * NAND
 215  */
 216 #define CONFIG_NAND_DOCG4
 217 #define CONFIG_SYS_NAND_SELF_INIT
 218 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* only one device */
 219 #define CONFIG_SYS_NAND_BASE 0x00000000 /* mapped to reset vector */
 220 #define CONFIG_SYS_NAND_PAGE_SIZE 0x200
 221 #define CONFIG_SYS_NAND_BLOCK_SIZE 0x40000
 222 #define CONFIG_BITREVERSE       /* needed by docg4 driver */
 223 #define CONFIG_BCH              /* needed by docg4 driver */
 224
 225 /*
 226  * IMPORTANT NOTE: this is the size of the concatenated spl + u-boot image.  It
 227  * will be rounded up to the next 64k boundary (the spl flash block size), so it
 228  * does not have to be exact, but you must ensure that it is not less than the
 229  * actual image size, or it may fail to boot (bricked phone)!
 230  * (Tip: reduces to three blocks with lcd and mmc support removed from u-boot.)
 231 */
 232 #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 /* four 64k flash blocks */
 233
 234 /*
 235  * This is the byte offset into the flash at which the concatenated spl + u-boot
 236  * image is placed.  It must be at the start of a block (256k boundary).  Blocks
 237  * 0 - 5 are write-protected, so we start at block 6.
 238  */
 239 #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x180000  /* block 6 */
 240
 241 /* DRAM address to which u-boot proper is loaded (before it relocates itself) */
 242 #define CONFIG_SYS_NAND_U_BOOT_DST  0xa0000000
 243 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST
 244
 245 /* passed to linker by Makefile as arg to -Ttext option */
 246 #define CONFIG_SYS_TEXT_BASE 0xa0000000
 247
 248 #define CONFIG_SYS_INIT_SP_ADDR         0x5c040000 /* end of internal SRAM */
 249
 250 /*
 251  * environment
 252  */
 253 #define CONFIG_ENV_IS_NOWHERE
 254 #define CONFIG_BUILD_ENVCRC
 255 #define CONFIG_ENV_SIZE 0x200
 256 #define CONFIG_SYS_CONSOLE_IS_IN_ENV
 257 #define CONFIG_EXTRA_ENV_SETTINGS  \
 258         "stdin=usbtty\0"           \
 259         "stdout=usbtty\0"          \
 260         "stderr=usbtty"
 261 #define CONFIG_BOOTARGS "mtdparts=Msys_Diskonchip_G4:1536k(protected_part)ro,1024k(bootloader_part),-(filesys_part) \
 262 ip=192.168.11.102:::255.255.255.0:treo:usb0"
 263 #define CONFIG_BOOTDELAY   3
 264
 265 #if 0 /* example: try 2nd mmc partition, then nand */
 266 #define CONFIG_BOOTCOMMAND                                              \
 267         "mmc rescan; "                                                  \
 268         "if mmcinfo && ext2load mmc 0:2 0xa1000000 uImage; then "       \
 269             "bootm 0xa1000000; "                                        \
 270         "elif nand read 0xa1000000 0x280000 0x240000; then "            \
 271             "bootm 0xa1000000; "                                        \
 272         "fi; "
 273 #endif
 274
 275 /* u-boot lives at end of SDRAM, so use start of SDRAM for stand alone apps */
 276 #define CONFIG_STANDALONE_LOAD_ADDR 0xa0000000
 277
 278 #define CONFIG_SYS_DCACHE_OFF
 279 #define CONFIG_SYS_ICACHE_OFF
 280
 281 #endif  /* __CONFIG_H */