include/configs/pcm030.h

   1 /*
   2  * (C) Copyright 2003-2005
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Eric Schumann, Phytec Messatechnik GmbH
   7  *
   8  * (C) Copyright 2009
   9  * Jon Smirl <jonsmirl@gmail.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #ifndef __CONFIG_H
  15 #define __CONFIG_H
  16
  17 #define CONFIG_BOARDINFO         "phyCORE-MPC5200B-tiny"
  18 #define CONFIG_SYS_GENERIC_BOARD
  19
  20 /*-----------------------------------------------------------------------------
  21 High Level Configuration Options
  22 (easy to change)
  23 -----------------------------------------------------------------------------*/
  24 #define CONFIG_MPC5200          1       /* This is an MPC5200 CPU */
  25 #define CONFIG_MPC5200_DDR      1       /* (with DDR-SDRAM) */
  26 #define CONFIG_PHYCORE_MPC5200B_TINY 1  /* phyCORE-MPC5200B -> */
  27                                         /* FEC configuration and IDE */
  28
  29 /*
  30  * Valid values for CONFIG_SYS_TEXT_BASE are:
  31  * 0xFFF00000   boot high (standard configuration)
  32  * 0xFF000000   boot low
  33  * 0x00100000   boot from RAM (for testing only)
  34  */
  35 #ifndef CONFIG_SYS_TEXT_BASE
  36 #define CONFIG_SYS_TEXT_BASE    0xFFF00000
  37 #endif
  38
  39 #define CONFIG_SYS_MPC5XXX_CLKIN 33333333 /* ... running at 33.333333MHz */
  40
  41 /*-----------------------------------------------------------------------------
  42 Serial console configuration
  43 -----------------------------------------------------------------------------*/
  44 #define CONFIG_PSC_CONSOLE      3       /* console is on PSC3 -> */
  45                                         /*define gps port conf. */
  46                                         /* register later on to */
  47                                         /*enable UART function! */
  48 #define CONFIG_BAUDRATE         115200  /* ... at 115200 bps */
  49 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
  50
  51 /*
  52  * Command line configuration.
  53  */
  54 #define CONFIG_CMD_DATE
  55 #define CONFIG_CMD_DHCP
  56 #define CONFIG_CMD_EEPROM
  57 #define CONFIG_CMD_I2C
  58 #define CONFIG_CMD_JFFS2
  59 #define CONFIG_CMD_MII
  60 #define CONFIG_CMD_PCI
  61
  62 #define CONFIG_TIMESTAMP        1       /* Print image info with timestamp */
  63
  64 #if (CONFIG_SYS_TEXT_BASE == 0xFF000000)        /* Boot low */
  65 #define CONFIG_SYS_LOWBOOT 1
  66 #endif
  67 /* RAMBOOT will be defined automatically in memory section */
  68
  69 #define CONFIG_JFFS2_CMDLINE
  70 #define MTDIDS_DEFAULT          "nor0=physmap-flash.0"
  71 #define MTDPARTS_DEFAULT        "mtdparts=physmap-flash.0:256k(ubootl)," \
  72         "1792k(kernel),13312k(jffs2),256k(uboot)ro,256k(oftree),-(space)"
  73
  74 /*-----------------------------------------------------------------------------
  75 Autobooting
  76 -----------------------------------------------------------------------------*/
  77 #define CONFIG_BOOTDELAY        3       /* autoboot after 3 seconds */
  78 #define CONFIG_ZERO_BOOTDELAY_CHECK     /* allow stopping of boot process */
  79                                         /* even with bootdelay=0 */
  80 #undef  CONFIG_BOOTARGS
  81
  82
  83 #define CONFIG_PREBOOT  "echo;" \
  84         "echo Type \"run bootcmd_net\" to load Kernel over TFTP and to "\
  85                 "mount root filesystem over NFS;" \
  86         "echo"
  87
  88 #define CONFIG_EXTRA_ENV_SETTINGS                                       \
  89         "netdev=eth0\0"                                                 \
  90         "uimage=uImage-pcm030\0"                                        \
  91         "oftree=oftree-pcm030.dtb\0"                                    \
  92         "jffs2=root-pcm030.jffs2\0"                                     \
  93         "uboot=u-boot-pcm030.bin\0"                                     \
  94         "bargs_base=setenv bootargs console=ttyPSC0,$(baudrate)"        \
  95                 " $(mtdparts) rw\0"                                     \
  96         "bargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2"   \
  97                 " rootfstype=jffs2\0"                                   \
  98         "bargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs"           \
  99                 " ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)::"   \
 100                 "$(netdev):off nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \
 101         "bcmd_net=run bargs_base bargs_nfs; tftpboot 0x500000 $(uimage);" \
 102                 " tftp 0x400000 $(oftree); bootm 0x500000 - 0x400000\0" \
 103         "bcmd_flash=run bargs_base bargs_flash; bootm 0xff040000 - "    \
 104                 "0xfff40000\0"                                          \
 105                 " cp.b 0x400000 0xff040000 $(filesize)\0"               \
 106         "prg_jffs2=tftp 0x400000 $(jffs2); erase 0xff200000 0xffefffff; " \
 107                 "cp.b 0x400000 0xff200000 $(filesize)\0"                \
 108         "prg_oftree=tftp 0x400000 $(oftree); erase 0xfff40000 0xfff5ffff;" \
 109                 " cp.b 0x400000 0xfff40000 $(filesize)\0"               \
 110         "update=tftpboot 0x400000 $(uboot);erase 0xFFF00000 0xfff3ffff;" \
 111                 " cp.b 0x400000 0xFFF00000 $(filesize)\0"               \
 112         "unlock=yes\0"                                                  \
 113         ""
 114
 115 #define CONFIG_BOOTCOMMAND              "run bcmd_flash"
 116
 117 /*--------------------------------------------------------------------------
 118 IPB Bus clocking configuration.
 119  ---------------------------------------------------------------------------*/
 120 #define CONFIG_SYS_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */
 121
 122 /*-------------------------------------------------------------------------
 123  * PCI Mapping:
 124  * 0x40000000 - 0x4fffffff - PCI Memory
 125  * 0x50000000 - 0x50ffffff - PCI IO Space
 126  * -----------------------------------------------------------------------*/
 127 #define CONFIG_PCI                      1
 128 #define CONFIG_PCI_PNP                  1
 129 #define CONFIG_PCI_SCAN_SHOW            1
 130 #define CONFIG_PCI_MEM_BUS              0x40000000
 131 #define CONFIG_PCI_MEM_PHYS             CONFIG_PCI_MEM_BUS
 132 #define CONFIG_PCI_MEM_SIZE             0x10000000
 133 #define CONFIG_PCI_IO_BUS               0x50000000
 134 #define CONFIG_PCI_IO_PHYS              CONFIG_PCI_IO_BUS
 135 #define CONFIG_PCI_IO_SIZE              0x01000000
 136 #define CONFIG_SYS_XLB_PIPELINING       1
 137
 138 /*---------------------------------------------------------------------------
 139  I2C configuration
 140 ---------------------------------------------------------------------------*/
 141 #define CONFIG_HARD_I2C 1 /* I2C with hardware support */
 142 #define CONFIG_SYS_I2C_MODULE 2 /* Select I2C module #1 or #2 */
 143 #define CONFIG_SYS_I2C_SPEED 100000 /* 100 kHz */
 144 #define CONFIG_SYS_I2C_SLAVE 0x7F
 145
 146 /*---------------------------------------------------------------------------
 147  EEPROM CAT24WC32 configuration
 148 ---------------------------------------------------------------------------*/
 149 #define CONFIG_SYS_I2C_EEPROM_ADDR      0x52    /* 1010100x */
 150 #define CONFIG_SYS_I2C_FACT_ADDR        0x52    /* EEPROM CAT24WC32 */
 151 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  2       /* Bytes of address */
 152 #define CONFIG_SYS_EEPROM_SIZE          2048
 153 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
 154 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 15
 155
 156 /*---------------------------------------------------------------------------
 157 RTC configuration
 158 ---------------------------------------------------------------------------*/
 159 #define RTC
 160 #define CONFIG_RTC_PCF8563              1
 161 #define CONFIG_SYS_I2C_RTC_ADDR         0x51
 162
 163 /*---------------------------------------------------------------------------
 164  Flash configuration
 165 ---------------------------------------------------------------------------*/
 166
 167 #define CONFIG_SYS_FLASH_BASE           0xff000000
 168 #define CONFIG_SYS_FLASH_SIZE           0x01000000
 169 #define CONFIG_SYS_FLASH_BANKS_LIST     { CONFIG_SYS_FLASH_BASE }
 170
 171 #define CONFIG_SYS_FLASH_CFI            1       /* Flash is CFI conformant */
 172 #define CONFIG_FLASH_CFI_DRIVER 1       /* Use the common driver */
 173 #define CONFIG_SYS_FLASH_EMPTY_INFO
 174 #define CONFIG_SYS_MAX_FLASH_SECT 260 /* max num of sects on one chip */
 175 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of flash banks */
 176                                                 /* (= chip selects) */
 177 #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
 178
 179 /*
 180  * Use also hardware protection. This seems required, as the BDI uses
 181  * hardware protection. Without this, U-Boot can't work with this sectors,
 182  * as its protection is software only by default
 183  */
 184 #define CONFIG_SYS_FLASH_PROTECTION     1
 185
 186 /*---------------------------------------------------------------------------
 187  Environment settings
 188 ---------------------------------------------------------------------------*/
 189
 190 /* pcm030 ships with environment is EEPROM by default */
 191 #define CONFIG_ENV_IS_IN_EEPROM 1
 192 #define CONFIG_ENV_OFFSET       0x00    /* environment starts at the */
 193                                         /*beginning of the EEPROM */
 194 #define CONFIG_ENV_SIZE         CONFIG_SYS_EEPROM_SIZE
 195
 196 #define CONFIG_ENV_OVERWRITE    1
 197
 198 /*-----------------------------------------------------------------------------
 199   Memory map
 200 -----------------------------------------------------------------------------*/
 201 #define CONFIG_SYS_MBAR 0xF0000000      /* MBAR has to be switched by other */
 202                                         /* bootloader or debugger config */
 203 #define CONFIG_SYS_SDRAM_BASE           0x00000000
 204 #define CONFIG_SYS_DEFAULT_MBAR         0x80000000
 205 /* Use SRAM until RAM will be available */
 206 #define CONFIG_SYS_INIT_RAM_ADDR        MPC5XXX_SRAM
 207 #define CONFIG_SYS_INIT_RAM_SIZE        MPC5XXX_SRAM_SIZE       /* Size of used */
 208                                                                 /* area in DPRAM */
 209 #define CONFIG_SYS_GBL_DATA_OFFSET      (CONFIG_SYS_INIT_RAM_SIZE - \
 210                                                 GENERATED_GBL_DATA_SIZE)
 211 #define CONFIG_SYS_INIT_SP_OFFSET       CONFIG_SYS_GBL_DATA_OFFSET
 212
 213 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
 214 #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
 215 #       define CONFIG_SYS_RAMBOOT               1
 216 #endif
 217
 218 #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
 219 #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
 220 #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
 221
 222 /*-----------------------------------------------------------------------------
 223  Ethernet configuration
 224 -----------------------------------------------------------------------------*/
 225 #define CONFIG_MPC5xxx_FEC              1
 226 #define CONFIG_MPC5xxx_FEC_MII100
 227 #define CONFIG_PHY_ADDR                 0x01
 228
 229 /*---------------------------------------------------------------------------
 230  GPIO configuration
 231  ---------------------------------------------------------------------------*/
 232
 233 /* GPIO port configuration
 234  *
 235  * Pin mapping:
 236  *
 237  * [29:31] = 01x
 238  * PSC1_0 -> AC97 SDATA out
 239  * PSC1_1 -> AC97 SDTA in
 240  * PSC1_2 -> AC97 SYNC out
 241  * PSC1_3 -> AC97 bitclock out
 242  * PSC1_4 -> AC97 reset out
 243  *
 244  * [25:27] = 001
 245  * PSC2_0 -> CAN 1 Tx out
 246  * PSC2_1 -> CAN 1 Rx in
 247  * PSC2_2 -> CAN 2 Tx out
 248  * PSC2_3 -> CAN 2 Rx in
 249  * PSC2_4 -> GPIO (claimed for ATA reset, active low)
 250  *
 251  *
 252  * [20:23] = 1100
 253  * PSC3_0 -> UART Tx out
 254  * PSC3_1 -> UART Rx in
 255  * PSC3_2 -> UART RTS (in/out FIXME)
 256  * PSC3_3 -> UART CTS (in/out FIXME)
 257  * PSC3_4 -> LocalPlus Bus CS6 \
 258  * PSC3_5 -> LocalPlus Bus CS7 / --> see [4] and [5]
 259  * PSC3_6 -> dedicated SPI MOSI out (master case)
 260  * PSC3_7 -> dedicated SPI MISO in (master case)
 261  * PSC3_8 -> dedicated SPI SS out (master case)
 262  * PSC3_9 -> dedicated SPI CLK out (master case)
 263  *
 264  * [18:19] = 01
 265  * USB_0 -> USB OE out
 266  * USB_1 -> USB Tx- out
 267  * USB_2 -> USB Tx+ out
 268  * USB_3 -> USB RxD (in/out FIXME)
 269  * USB_4 -> USB Rx+ in
 270  * USB_5 -> USB Rx- in
 271  * USB_6 -> USB PortPower out
 272  * USB_7 -> USB speed out
 273  * USB_8 -> USB suspend (in/out FIXME)
 274  * USB_9 -> USB overcurrent in
 275  *
 276  * [17] = 0
 277  * USB differential mode
 278  *
 279  * [16] = 0
 280  * PCI enabled
 281  *
 282  * [12:15] = 0101
 283  * ETH_0 -> ETH Txen
 284  * ETH_1 -> ETH TxD0
 285  * ETH_2 -> ETH TxD1
 286  * ETH_3 -> ETH TxD2
 287  * ETH_4 -> ETH TxD3
 288  * ETH_5 -> ETH Txerr
 289  * ETH_6 -> ETH MDC
 290  * ETH_7 -> ETH MDIO
 291  * ETH_8 -> ETH RxDv
 292  * ETH_9 -> ETH RxCLK
 293  * ETH_10 -> ETH Collision
 294  * ETH_11 -> ETH TxD
 295  * ETH_12 -> ETH RxD0
 296  * ETH_13 -> ETH RxD1
 297  * ETH_14 -> ETH RxD2
 298  * ETH_15 -> ETH RxD3
 299  * ETH_16 -> ETH Rxerr
 300  * ETH_17 -> ETH CRS
 301  *
 302  * [9:11] = 101
 303  * PSC6_0 -> UART RxD in
 304  * PSC6_1 -> UART CTS (in/out FIXME)
 305  * PSC6_2 -> UART TxD out
 306  * PSC6_3 -> UART RTS (in/out FIXME)
 307  *
 308  * [2:3/6:7] = 00/11
 309  * TMR_0 -> ATA_CS0 out
 310  * TMR_1 -> ATA_CS1 out
 311  * TMR_2 -> GPIO
 312  * TMR_3 -> GPIO
 313  * TMR_4 -> GPIO
 314  * TMR_5 -> GPIO
 315  * TMR_6 -> GPIO
 316  * TMR_7 -> GPIO
 317  * I2C_0 -> I2C 1 Clock out
 318  * I2C_1 -> I2C 1 IO in/out
 319  * I2C_2 -> I2C 2 Clock out
 320  * I2C_3 -> I2C 2 IO in/out
 321  *
 322  * [4] = 1
 323  * PSC3_5 is used as CS7
 324  *
 325  * [5] = 1
 326  * PSC3_4 is used as CS6
 327  *
 328  * [1] = 0
 329  * gpio_wkup_7 is GPIO
 330  *
 331  * [0] = 0
 332  * gpio_wkup_6 is GPIO
 333  *
 334  */
 335 #define CONFIG_SYS_GPS_PORT_CONFIG      0x0f551c12
 336
 337 /*-----------------------------------------------------------------------------
 338  Miscellaneous configurable options
 339 -------------------------------------------------------------------------------*/
 340 #define CONFIG_SYS_LONGHELP     /* undef to save memory */
 341
 342 #define CONFIG_CMDLINE_EDITING 1 /* add command line history */
 343
 344 #define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */
 345 #if defined(CONFIG_CMD_KGDB)
 346 #define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
 347 #endif
 348
 349 #if defined(CONFIG_CMD_KGDB)
 350 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
 351 #else
 352 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
 353 #endif
 354 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
 355                                                         /* Print Buffer Size */
 356 #define CONFIG_SYS_MAXARGS 16 /* max number of command args */
 357 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
 358
 359 #define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
 360 #define CONFIG_SYS_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */
 361
 362 #define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */
 363
 364 #define CONFIG_DISPLAY_BOARDINFO 1
 365
 366 /*-----------------------------------------------------------------------------
 367  Various low-level settings
 368 -----------------------------------------------------------------------------*/
 369 #define CONFIG_SYS_HID0_INIT            HID0_ICE | HID0_ICFI
 370 #define CONFIG_SYS_HID0_FINAL           HID0_ICE
 371
 372 /* no burst access on the LPB */
 373 #define CONFIG_SYS_CS_BURST             0x00000000
 374 /* one deadcycle for the 33MHz statemachine */
 375 #define CONFIG_SYS_CS_DEADCYCLE         0x33333331
 376 /* one additional waitstate for the 33MHz statemachine */
 377 #define CONFIG_SYS_BOOTCS_CFG           0x0001dd00
 378 #define CONFIG_SYS_BOOTCS_START         CONFIG_SYS_FLASH_BASE
 379 #define CONFIG_SYS_BOOTCS_SIZE          CONFIG_SYS_FLASH_SIZE
 380
 381 #define CONFIG_SYS_RESET_ADDRESS        0xff000000
 382
 383 /*-----------------------------------------------------------------------
 384  * USB stuff
 385  *-----------------------------------------------------------------------
 386  */
 387 #define CONFIG_USB_CLOCK                0x0001BBBB
 388 #define CONFIG_USB_CONFIG               0x00001000
 389
 390 /*---------------------------------------------------------------------------
 391  IDE/ATA stuff Supports IDE harddisk
 392 ----------------------------------------------------------------------------*/
 393
 394 #undef  CONFIG_IDE_8xx_PCCARD   /* Use IDE with PC Card Adapter */
 395 #undef  CONFIG_IDE_8xx_DIRECT   /* Direct IDE not supported */
 396 #undef  CONFIG_IDE_LED          /* LED for ide not supported */
 397 #define CONFIG_SYS_ATA_CS_ON_TIMER01
 398 #define CONFIG_IDE_RESET 1      /* reset for ide supported */
 399 #define CONFIG_IDE_PREINIT
 400 #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
 401 #define CONFIG_SYS_IDE_MAXDEVICE 2 /* max. 2 drives per IDE bus */
 402 #define CONFIG_SYS_ATA_IDE0_OFFSET      0x0000
 403 #define CONFIG_SYS_ATA_BASE_ADDR        MPC5XXX_ATA
 404 /* Offset for data I/O                  */
 405 #define CONFIG_SYS_ATA_DATA_OFFSET      (0x0060)
 406 /* Offset for normal register accesses  */
 407 #define CONFIG_SYS_ATA_REG_OFFSET       (CONFIG_SYS_ATA_DATA_OFFSET)
 408 /* Offset for alternate registers       */
 409 #define CONFIG_SYS_ATA_ALT_OFFSET       (0x005C)
 410 /* Interval between registers */
 411 #define CONFIG_SYS_ATA_STRIDE           4
 412 #define CONFIG_ATAPI                    1
 413
 414 /* we enable IDE and FAT support, so we also need partition support */
 415 #define CONFIG_DOS_PARTITION 1
 416
 417 /* USB */
 418 #define CONFIG_USB_OHCI
 419 #define CONFIG_USB_STORAGE
 420
 421 /* pass open firmware flat tree */
 422 #define CONFIG_OF_LIBFDT                1
 423 #define CONFIG_OF_BOARD_SETUP           1
 424
 425 #define OF_CPU                          "PowerPC,5200@0"
 426 #define OF_TBCLK                        CONFIG_SYS_MPC5XXX_CLKIN
 427 #define OF_SOC                          "soc5200@f0000000"
 428 #define OF_STDOUT_PATH                  "/soc5200@f0000000/serial@2400"
 429
 430 #endif /* __CONFIG_H */