include/configs/pcu_e.h

   1 /*
   2  * (C) Copyright 2001
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 /*
  25  * board/config.h - configuration options, board specific
  26  */
  27
  28 #ifndef __CONFIG_H
  29 #define __CONFIG_H
  30
  31 /*
  32  * Workaround for layout bug on prototype board
  33  */
  34 #define PCU_E_WITH_SWAPPED_CS   1
  35
  36 /*
  37  * High Level Configuration Options
  38  * (easy to change)
  39  */
  40
  41 #define CONFIG_MPC860           1       /* This is a MPC860T CPU        */
  42 #define CONFIG_MPC860T          1
  43 #define CONFIG_PCU_E            1       /* ...on a PCU E board          */
  44
  45 #define CONFIG_8xx_CONS_SMC1    1       /* Console is on SMC1           */
  46
  47 #define CONFIG_BAUDRATE         9600
  48 #if 0
  49 #define CONFIG_BOOTDELAY        -1      /* autoboot disabled            */
  50 #else
  51 #define CONFIG_BOOTDELAY        5       /* autoboot after 5 seconds     */
  52 #endif
  53
  54 #define CONFIG_CLOCKS_IN_MHZ    1       /* clocks passsed to Linux in MHz */
  55
  56 #undef  CONFIG_BOOTARGS
  57 #define CONFIG_BOOTCOMMAND                                                      \
  58         "bootp;"                                                                \
  59         "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) "     \
  60         "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;"    \
  61         "bootm"
  62
  63 #define CONFIG_LOADS_ECHO       1       /* echo on for serial download  */
  64 #undef  CFG_LOADS_BAUD_CHANGE           /* don't allow baudrate change  */
  65
  66 #undef  CONFIG_WATCHDOG                 /* watchdog disabled            */
  67
  68 #define CONFIG_STATUS_LED       1       /* Status LED enabled           */
  69
  70 #define CONFIG_PRAM             2048    /* reserve 2 MB "protected RAM" */
  71
  72 #define CONFIG_RTC_MPC8xx               /* use internal RTC of MPC8xx   */
  73
  74 #define CONFIG_SPI                      /* enable SPI driver            */
  75 #define CONFIG_SPI_X                    /* 16 bit EEPROM addressing     */
  76
  77 #define CONFIG_HARD_I2C         1       /* I2C with hardware support    */
  78 #define CFG_I2C_SPEED           400000  /* I2C speed and slave address  */
  79 #define CFG_I2C_SLAVE           0x7F
  80
  81
  82 /* ----------------------------------------------------------------
  83  * Offset to initial SPI buffers in DPRAM (used if the environment
  84  * is in the SPI EEPROM): We need a 520 byte scratch DPRAM area to
  85  * use at an early stage. It is used between the two initialization
  86  * calls (spi_init_f() and spi_init_r()). The value 0xB00 makes it
  87  * far enough from the start of the data area (as well as from the
  88  * stack pointer).
  89  * ---------------------------------------------------------------- */
  90 #define CFG_SPI_INIT_OFFSET             0xB00
  91
  92 #define CONFIG_COMMANDS         (       CONFIG_CMD_DFL  | \
  93                                         CFG_CMD_DATE    | \
  94                                         CFG_CMD_EEPROM  | \
  95                                         CFG_CMD_BSP     )
  96
  97 #define CONFIG_BOOTP_MASK \
  98     ((CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) & ~CONFIG_BOOTP_GATEWAY)
  99
 100 /* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
 101 #include <cmd_confdefs.h>
 102
 103 /*----------------------------------------------------------------------*/
 104
 105 /*
 106  * Miscellaneous configurable options
 107  */
 108 #define CFG_LONGHELP                    /* undef to save memory         */
 109 #define CFG_PROMPT      "=> "           /* Monitor Command Prompt       */
 110 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 111 #define CFG_CBSIZE      1024            /* Console I/O Buffer Size      */
 112 #else
 113 #define CFG_CBSIZE      256             /* Console I/O Buffer Size      */
 114 #endif
 115 #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
 116 #define CFG_MAXARGS     16              /* max number of command args   */
 117 #define CFG_BARGSIZE    CFG_CBSIZE      /* Boot Argument Buffer Size    */
 118
 119 #define CFG_MEMTEST_START       0x00100000      /* memtest works on     */
 120 #define CFG_MEMTEST_END         0x00F00000      /* 1 ... 15MB in DRAM   */
 121
 122 #define CFG_LOAD_ADDR           0x00100000      /* default load address */
 123
 124 #define CFG_PIO_MODE            0       /* IDE interface in PIO Mode 0  */
 125
 126 /* Ethernet hardware configuration done using port pins */
 127 #define CFG_PB_ETH_RESET        0x00000020              /* PB 26        */
 128 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 129 #define CFG_PA_ETH_MDDIS        0x4000                  /* PA  1        */
 130 #define CFG_PB_ETH_POWERDOWN    0x00000800              /* PB 20        */
 131 #define CFG_PB_ETH_CFG1         0x00000400              /* PB 21        */
 132 #define CFG_PB_ETH_CFG2         0x00000200              /* PB 22        */
 133 #define CFG_PB_ETH_CFG3         0x00000100              /* PB 23        */
 134 #else /* XXX */
 135 #define CFG_PB_ETH_MDDIS        0x00000010              /* PB 27        */
 136 #define CFG_PB_ETH_POWERDOWN    0x00000100              /* PB 23        */
 137 #define CFG_PB_ETH_CFG1         0x00000200              /* PB 22        */
 138 #define CFG_PB_ETH_CFG2         0x00000400              /* PB 21        */
 139 #define CFG_PB_ETH_CFG3         0x00000800              /* PB 20        */
 140 #endif /* XXX */
 141
 142 /* Ethernet settings:
 143  * MDIO enabled, autonegotiation, 10/100Mbps, half/full duplex
 144  */
 145 #define CFG_ETH_MDDIS_VALUE     0
 146 #define CFG_ETH_CFG1_VALUE      1
 147 #define CFG_ETH_CFG2_VALUE      1
 148 #define CFG_ETH_CFG3_VALUE      1
 149
 150 /* PUMA configuration */
 151 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 152 #define CFG_PB_PUMA_PROG        0x00000010              /* PB 27        */
 153 #else /* XXX */
 154 #define CFG_PA_PUMA_PROG        0x4000                  /* PA  1        */
 155 #endif /* XXX */
 156 #define CFG_PC_PUMA_DONE        0x0008                  /* PC 12        */
 157 #define CFG_PC_PUMA_INIT        0x0004                  /* PC 13        */
 158
 159 #define CFG_HZ          1000            /* decrementer freq: 1 ms ticks */
 160
 161 #define CFG_BAUDRATE_TABLE      { 9600, 19200, 38400, 57600, 115200 }
 162
 163 /*
 164  * Low Level Configuration Settings
 165  * (address mappings, register initial values, etc.)
 166  * You should know what you are doing if you make changes here.
 167  */
 168 /*-----------------------------------------------------------------------
 169  * Internal Memory Mapped Register
 170  */
 171 #define CFG_IMMR                0xFE000000
 172
 173 /*-----------------------------------------------------------------------
 174  * Definitions for initial stack pointer and data area (in DPRAM)
 175  */
 176 #define CFG_INIT_RAM_ADDR       CFG_IMMR
 177 #define CFG_INIT_RAM_END        0x2F00  /* End of used area in DPRAM    */
 178 #define CFG_GBL_DATA_SIZE       64  /* size in bytes reserved for initial data */
 179 #define CFG_GBL_DATA_OFFSET     (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
 180 #define CFG_INIT_SP_OFFSET      CFG_GBL_DATA_OFFSET
 181
 182 /*-----------------------------------------------------------------------
 183  * Address accessed to reset the board - must not be mapped/assigned
 184  */
 185 #define CFG_RESET_ADDRESS       0xFEFFFFFF
 186
 187 /*-----------------------------------------------------------------------
 188  * Start addresses for the final memory configuration
 189  * (Set up by the startup code)
 190  * Please note that CFG_SDRAM_BASE _must_ start at 0
 191  */
 192 #define CFG_SDRAM_BASE          0x00000000
 193 /* this is an ugly hack needed because of the silly non-constant address map */
 194 #define CFG_FLASH_BASE          (0-flash_info[0].size-flash_info[1].size)
 195
 196 #if defined(DEBUG)
 197 #define CFG_MONITOR_LEN         (256 << 10)     /* Reserve 256 kB for Monitor   */
 198 #else
 199 #define CFG_MONITOR_LEN         (192 << 10)     /* Reserve 192 kB for Monitor   */
 200 #endif
 201 #define CFG_MONITOR_BASE        TEXT_BASE
 202 #define CFG_MALLOC_LEN          (128 << 10)     /* Reserve 128 kB for malloc()  */
 203
 204 /*
 205  * For booting Linux, the board info and command line data
 206  * have to be in the first 8 MB of memory, since this is
 207  * the maximum mapped by the Linux kernel during initialization.
 208  */
 209 #define CFG_BOOTMAPSZ           (8 << 20)       /* Initial Memory map for Linux */
 210 /*-----------------------------------------------------------------------
 211  * FLASH organization
 212  */
 213 #define CFG_MAX_FLASH_BANKS     2       /* max number of memory banks           */
 214 #define CFG_MAX_FLASH_SECT      160     /* max number of sectors on one chip    */
 215
 216 #define CFG_FLASH_ERASE_TOUT    180000  /* Timeout for Flash Erase (in ms)      */
 217 #define CFG_FLASH_WRITE_TOUT    1000    /* Timeout for Flash Write (in ms)      */
 218
 219 #if 0
 220 /* Start port with environment in flash; switch to SPI EEPROM later */
 221 #define CFG_ENV_IS_IN_FLASH     1
 222 #define CFG_ENV_SIZE            0x2000  /* Total Size of Environment            */
 223 #define CFG_ENV_ADDR        0xFFFFE000  /* Address    of Environment Sector     */
 224 #define CFG_ENV_SECT_SIZE       0x2000  /* use the top-most 8k boot sector      */
 225 #define CFG_ENV_IS_EMBEDDED     1       /* short-cut compile-time test          */
 226 #else
 227 /* Final version: environment in EEPROM */
 228 #define CFG_ENV_IS_IN_EEPROM    1
 229 #define CFG_I2C_EEPROM_ADDR     0
 230 #define CFG_I2C_EEPROM_ADDR_LEN 2
 231 #define CFG_ENV_OFFSET          1024
 232 #define CFG_ENV_SIZE            1024
 233 #endif
 234
 235 /*-----------------------------------------------------------------------
 236  * Cache Configuration
 237  */
 238 #define CFG_CACHELINE_SIZE      16      /* For all MPC8xx CPUs                  */
 239 #define CFG_CACHELINE_SHIFT     4       /* log base 2 of the above value        */
 240
 241 /*-----------------------------------------------------------------------
 242  * SYPCR - System Protection Control                            11-9
 243  * SYPCR can only be written once after reset!
 244  *-----------------------------------------------------------------------
 245  * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 246  */
 247 #if defined(CONFIG_WATCHDOG)
 248 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
 249                          SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
 250 #else
 251 #define CFG_SYPCR       (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
 252 #endif
 253
 254 /*-----------------------------------------------------------------------
 255  * SIUMCR - SIU Module Configuration                            11-6
 256  *-----------------------------------------------------------------------
 257  * External Arbitration max. priority (7),
 258  * Debug pins configuration '11',
 259  * Asynchronous external master enable.
 260  */
 261 /* => 0x70600200 */
 262 #define CFG_SIUMCR      (SIUMCR_EARP7 | SIUMCR_DBGC11 | SIUMCR_AEME)
 263
 264 /*-----------------------------------------------------------------------
 265  * TBSCR - Time Base Status and Control                         11-26
 266  *-----------------------------------------------------------------------
 267  * Clear Reference Interrupt Status, Timebase freezing enabled
 268  */
 269 #define CFG_TBSCR       (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)
 270
 271 /*-----------------------------------------------------------------------
 272  * PISCR - Periodic Interrupt Status and Control                11-31
 273  *-----------------------------------------------------------------------
 274  * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 275  */
 276 #define CFG_PISCR       (PISCR_PS | PISCR_PITF)
 277
 278 /*-----------------------------------------------------------------------
 279  * PLPRCR - PLL, Low-Power, and Reset Control Register          15-30
 280  *-----------------------------------------------------------------------
 281  * Reset PLL lock status sticky bit, timer expired status bit and timer
 282  * interrupt status bit, set PLL multiplication factor !
 283  */
 284 /* 0x00004080 */
 285 #define CFG_PLPRCR_MF   0       /* (0+1) * 50 = 50 MHz Clock */
 286 #define CFG_PLPRCR                                                      \
 287                 (       (CFG_PLPRCR_MF << PLPRCR_MF_SHIFT) |            \
 288                         PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST |    \
 289                         /*PLPRCR_CSRC|*/ PLPRCR_LPM_NORMAL |            \
 290                         PLPRCR_CSR    /*| PLPRCR_LOLRE|PLPRCR_FIOPD*/   \
 291                 )
 292
 293 #define CONFIG_8xx_GCLK_FREQ    ((CFG_PLPRCR_MF+1)*50000000)
 294
 295 /*-----------------------------------------------------------------------
 296  * SCCR - System Clock and reset Control Register               15-27
 297  *-----------------------------------------------------------------------
 298  * Set clock output, timebase and RTC source and divider,
 299  * power management and some other internal clocks
 300  *
 301  * Note: PITRTCLK is 50MHz / 512 = 97'656.25 Hz
 302  */
 303 #define SCCR_MASK       SCCR_EBDF11
 304 /* 0x01800000 */
 305 #define CFG_SCCR        (SCCR_COM00     | /*SCCR_TBS|*/         \
 306                          SCCR_RTDIV     |   SCCR_RTSEL    |     \
 307                          /*SCCR_CRQEN|*/  /*SCCR_PRQEN|*/       \
 308                          SCCR_EBDF00 |   SCCR_DFSYNC00 |        \
 309                          SCCR_DFBRG00   |   SCCR_DFNL000  |     \
 310                          SCCR_DFNH000   |   SCCR_DFLCD100 |     \
 311                          SCCR_DFALCD01)
 312
 313 /*-----------------------------------------------------------------------
 314  * RTCSC - Real-Time Clock Status and Control Register          11-27
 315  *-----------------------------------------------------------------------
 316  *
 317  * Note: RTC counts at PITRTCLK / 8'192 = 11.920928 Hz !!!
 318  *
 319  * Don't expect the "date" command to work without a 32kHz clock input!
 320  */
 321 /* 0x00C3 => 0x0003 */
 322 #define CFG_RTCSC       (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)
 323
 324
 325 /*-----------------------------------------------------------------------
 326  * RCCR - RISC Controller Configuration Register                19-4
 327  *-----------------------------------------------------------------------
 328  */
 329 #define CFG_RCCR 0x0000
 330
 331 /*-----------------------------------------------------------------------
 332  * RMDS - RISC Microcode Development Support Control Register
 333  *-----------------------------------------------------------------------
 334  */
 335 #define CFG_RMDS 0
 336
 337 /*-----------------------------------------------------------------------
 338  *
 339  * Interrupt Levels
 340  *-----------------------------------------------------------------------
 341  */
 342 #define CFG_CPM_INTERRUPT       13      /* SIU_LEVEL6   */
 343
 344 /*-----------------------------------------------------------------------
 345  *
 346  *-----------------------------------------------------------------------
 347  *
 348  */
 349 #define CFG_DER 0
 350
 351 /*
 352  * Init Memory Controller:
 353  *
 354  * BR0/1 and OR0/1 (FLASH) - second Flash bank optional
 355  */
 356
 357 #define FLASH_BASE0_PRELIM      0xFF800000      /* FLASH bank #0        */
 358 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 359 #define FLASH_BASE6_PRELIM      0xFF000000      /* FLASH bank #1        */
 360 #else /* XXX */
 361 #define FLASH_BASE1_PRELIM      0xFF000000      /* FLASH bank #1        */
 362 #endif /* XXX */
 363
 364 /*
 365  * used to re-map FLASH: restrict access enough but not too much to
 366  * meddle with FLASH accesses
 367  */
 368 #define CFG_REMAP_OR_AM         0xFF800000      /* OR addr mask */
 369 #define CFG_PRELIM_OR_AM        0xFF800000      /* OR addr mask */
 370
 371 /* FLASH timing: CSNT = 0, ACS = 00, SCY = 8, EHTR = 1                  */
 372 #define CFG_OR_TIMING_FLASH     (OR_SCY_8_CLK | OR_EHTR)
 373
 374 #define CFG_OR0_REMAP   ( CFG_REMAP_OR_AM | OR_ACS_DIV1 | OR_BI | \
 375                                 CFG_OR_TIMING_FLASH)
 376 #define CFG_OR0_PRELIM  (CFG_PRELIM_OR_AM | OR_ACS_DIV1 | OR_BI | \
 377                                 CFG_OR_TIMING_FLASH)
 378 /* 16 bit, bank valid */
 379 #define CFG_BR0_PRELIM  ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 380
 381 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 382 #define CFG_OR6_REMAP   CFG_OR0_REMAP
 383 #define CFG_OR6_PRELIM  CFG_OR0_PRELIM
 384 #define CFG_BR6_PRELIM  ((FLASH_BASE6_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 385 #else /* XXX */
 386 #define CFG_OR1_REMAP   CFG_OR0_REMAP
 387 #define CFG_OR1_PRELIM  CFG_OR0_PRELIM
 388 #define CFG_BR1_PRELIM  ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )
 389 #endif /* XXX */
 390
 391 /*
 392  * BR2/OR2: SDRAM
 393  *
 394  * Multiplexed addresses, GPL5 output to GPL5_A (don't care)
 395  */
 396 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 397 #define SDRAM_BASE5_PRELIM      0x00000000      /* SDRAM bank */
 398 #else /* XXX */
 399 #define SDRAM_BASE2_PRELIM      0x00000000      /* SDRAM bank */
 400 #endif /* XXX */
 401 #define SDRAM_PRELIM_OR_AM      0xF8000000      /* map 128 MB (>SDRAM_MAX_SIZE!) */
 402 #define SDRAM_TIMING            OR_CSNT_SAM     /* SDRAM-Timing */
 403
 404 #define SDRAM_MAX_SIZE          0x04000000      /* max 64 MB SDRAM */
 405
 406 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 407 #define CFG_OR5_PRELIM  (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 408 #define CFG_BR5_PRELIM  ((SDRAM_BASE5_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 409 #else /* XXX */
 410 #define CFG_OR2_PRELIM  (SDRAM_PRELIM_OR_AM | SDRAM_TIMING )
 411 #define CFG_BR2_PRELIM  ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V )
 412 #endif /* XXX */
 413
 414 /*
 415  * BR3/OR3: CAN Controller
 416  *      BR3: 0x10000401         OR3: 0xffff818a
 417  */
 418 #define CAN_CTRLR_BASE          0x10000000      /* CAN Controller */
 419 #define CAN_CTRLR_OR_AM         0xFFFF8000      /* 32 kB */
 420 #define CAN_CTRLR_TIMING        (OR_BI | OR_SCY_8_CLK | OR_SETA | OR_EHTR)
 421
 422 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 423 #define CFG_BR4_PRELIM          ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 424 #define CFG_OR4_PRELIM          (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
 425 #else /* XXX */
 426 #define CFG_BR3_PRELIM          ((CAN_CTRLR_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 427 #define CFG_OR3_PRELIM          (CAN_CTRLR_OR_AM | CAN_CTRLR_TIMING)
 428 #endif /* XXX */
 429
 430 /*
 431  * BR4/OR4: PUMA Config
 432  *
 433  * Memory controller will be used in 2 modes:
 434  *
 435  * - "read" mode:
 436  *      BR4: 0x10100801         OR4: 0xffff8530
 437  * - "load" mode (chip select on UPM B):
 438  *      BR4: 0x101008c1         OR4: 0xffff8630
 439  *
 440  * Default initialization is in "read" mode
 441  */
 442 #define PUMA_CONF_BASE          0x10100000      /* PUMA Config */
 443 #define PUMA_CONF_OR_AM         0xFFFF8000      /* 32 kB */
 444 #define PUMA_CONF_LOAD_TIMING   (OR_ACS_DIV2     | OR_SCY_3_CLK)
 445 #define PUMA_CONF_READ_TIMING   (OR_G5LA | OR_BI | OR_SCY_3_CLK)
 446
 447 #define PUMA_CONF_BR_LOAD       ((PUMA_CONF_BASE & BR_BA_MSK) | \
 448                                         BR_PS_16 | BR_MS_UPMB | BR_V)
 449 #define PUMA_CONF_OR_LOAD       (PUMA_CONF_OR_AM | PUMA_CONF_LOAD_TIMING)
 450
 451 #define PUMA_CONF_BR_READ       ((PUMA_CONF_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 452 #define PUMA_CONF_OR_READ       (PUMA_CONF_OR_AM | PUMA_CONF_READ_TIMING)
 453
 454 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 455 #define CFG_BR3_PRELIM          PUMA_CONF_BR_READ
 456 #define CFG_OR3_PRELIM          PUMA_CONF_OR_READ
 457 #else /* XXX */
 458 #define CFG_BR4_PRELIM          PUMA_CONF_BR_READ
 459 #define CFG_OR4_PRELIM          PUMA_CONF_OR_READ
 460 #endif /* XXX */
 461
 462 /*
 463  * BR5/OR5: PUMA: SMA Bus 8 Bit
 464  *      BR5: 0x10200401         OR5: 0xffe0010a
 465  */
 466 #define PUMA_SMA8_BASE          0x10200000      /* PUMA SMA Bus 8 Bit */
 467 #define PUMA_SMA8_OR_AM         0xFFE00000      /* 2 MB */
 468 #define PUMA_SMA8_TIMING        (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 469
 470 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 471 #define CFG_BR2_PRELIM          ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 472 #define CFG_OR2_PRELIM          (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
 473 #else /* XXX */
 474 #define CFG_BR5_PRELIM          ((PUMA_SMA8_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)
 475 #define CFG_OR5_PRELIM          (PUMA_SMA8_OR_AM | PUMA_SMA8_TIMING | OR_SETA)
 476 #endif /* XXX */
 477
 478 /*
 479  * BR6/OR6: PUMA: SMA Bus 16 Bit
 480  *      BR6: 0x10600801         OR6: 0xffe0010a
 481  */
 482 #define PUMA_SMA16_BASE         0x10600000      /* PUMA SMA Bus 16 Bit */
 483 #define PUMA_SMA16_OR_AM        0xFFE00000      /* 2 MB */
 484 #define PUMA_SMA16_TIMING       (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 485
 486 #if PCU_E_WITH_SWAPPED_CS /* XXX */
 487 #define CFG_BR1_PRELIM          ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 488 #define CFG_OR1_PRELIM          (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
 489 #else /* XXX */
 490 #define CFG_BR6_PRELIM          ((PUMA_SMA16_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 491 #define CFG_OR6_PRELIM          (PUMA_SMA16_OR_AM | PUMA_SMA16_TIMING | OR_SETA)
 492 #endif /* XXX */
 493
 494 /*
 495  * BR7/OR7: PUMA: external Flash
 496  *      BR7: 0x10a00801         OR7: 0xfe00010a
 497  */
 498 #define PUMA_FLASH_BASE         0x10A00000      /* PUMA external Flash */
 499 #define PUMA_FLASH_OR_AM        0xFE000000      /* 32 MB */
 500 #define PUMA_FLASH_TIMING       (OR_BI | OR_SCY_0_CLK | OR_EHTR)
 501
 502 #define CFG_BR7_PRELIM          ((PUMA_FLASH_BASE & BR_BA_MSK) | BR_PS_16 | BR_V)
 503 #define CFG_OR7_PRELIM          (PUMA_FLASH_OR_AM | PUMA_FLASH_TIMING | OR_SETA)
 504
 505 /*
 506  * Memory Periodic Timer Prescaler
 507  */
 508
 509 /* periodic timer for refresh */
 510 #define CFG_MPTPR       0x0200
 511
 512 /*
 513  * MAMR settings for SDRAM
 514  * 0x30104118 = Timer A period 0x30, MAMR_AMB_TYPE_1, MAMR_G0CLB_A10,
 515  *              MAMR_RLFB_1X, MAMR_WLFB_1X, MAMR_TLFB_8X
 516  * 0x30904114 = - " - | Periodic Timer A Enable, MAMR_TLFB_4X
 517  */
 518 /* periodic timer for refresh */
 519 #define CFG_MAMR_PTA    0x30    /* = 48 */
 520
 521 #define CFG_MAMR        ( (CFG_MAMR_PTA << MAMR_PTA_SHIFT) | \
 522                           MAMR_AMA_TYPE_1       | \
 523                           MAMR_G0CLA_A10        | \
 524                           MAMR_RLFA_1X          | \
 525                           MAMR_WLFA_1X          | \
 526                           MAMR_TLFA_8X          )
 527
 528 /*
 529  * Internal Definitions
 530  *
 531  * Boot Flags
 532  */
 533 #define BOOTFLAG_COLD   0x01            /* Normal Power-On: Boot from FLASH     */
 534 #define BOOTFLAG_WARM   0x02            /* Software reboot                      */
 535
 536 #endif  /* __CONFIG_H */